thermal stresses in 3d ic inter-wafer interconnects

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Microelectronic Engineering xxx (2005) xxx–xxx

www.elsevier.com/locate/mee

Thermal stresses in 3D IC inter-wafer interconnects

Jing Zhang 1, Max O. Bloomfield, Jian -Qiang Lu,Ronald J. Gutmann, Timothy S. Cale *

Focus Center – New York, Rensselaer: Interconnections for Gigascale Integration, Rensselaer Polytechnic Institute, 110 8th Street,

Troy, NY 12180, USA

Abstract

We present a finite element based analysis to determine if thermally induced stresses in inter-wafer Cu via structures in3D ICs using BCB-bonded wafers is a potential reliability problem. Experimental information on thermal stresses orstress-induced failures of 3D ICs is not available in the literature. Therefore we first partially validate our approachby comparing computed results against experimental data on via test structures from planar ICs. Computed von Misesstresses show that the predicted failure agrees with the results of thermal cycle experiments when SiLK is used as a dielec-tric [R.G. Filippi, J.F. McGrath, T.M. Shaw, et al. Thermal cycle reliability of stacked via structures with coppermetallization and an organic low-k dielectric, in: 2004 IEEE International Reliability Physics Symposium. Proceedings,25–29 April, 2004. IEEE, Phoenix, AZ, USA, p. 61–67]. Simulations show that no yielding is expected in vias embeddedin SiCOH, which is also in agreement with experiment [D. Edelstein, H. Rathore, C. Davis, et al. Comprehensive reli-ability evaluation of a 90 nm CMOS technology with Cu/PECVD low-k BEOL, in 2004 IEEE International ReliabilityPhysics Symposium. Proceedings, 25–29 April, 2004, IEEE, Phoenix, AZ, USA, p. 316–319]. The approach is thenemployed to study thermal stresses in inter-wafer Cu vias in 3D IC structures bonded with BCB using a process devel-oped at the Focus Center–New York. We conclude that there is a concern regarding the stability of inter-wafer Cu vias.Target values for design parameters, e.g., inter-wafer via size, pitch, and the thickness of BCB, are estimated. Simulationsshow that the vonMises stresses in inter-wafer Cu vias decrease with decreasing pitch length at constant via size, increasewith decreasing via size at constant pitch, and decrease with decreasing BCB thickness. For 1 lm via diameter and 5 lmpitch, computations indicate that the thickness of BCB should be less than 1 lm to avoid plastic yield of Cu vias.� 2005 Elsevier B.V. All rights reserved.

0167-9317/$ - see front matter � 2005 Elsevier B.V. All rights reserv

doi:10.1016/j.mee.2005.07.053

* Corresponding author. Tel.: +1 518 276 8676; fax: +1 518276 4030.

E-mail addresses: [email protected] (J. Zhang), [email protected](T.S. Cale).1 Present address: Mechanical Engineering Department, Uni-

versity of Alaska Fairbanks, Fairbanks 99775. Tel.: +1 907 4746135; fax: +1 907 474 6141.

1. Introduction

Wafer-level 3D integration offers improved per-formance and functionality over conventional pla-nar integrated circuits (ICs). A primary driver for

ed.

mailto:[email protected]

mailto:[email protected]

2 J. Zhang et al. / Microelectronic Engineering xxx (2005) xxx–xxx

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3D ICs is the promise of reduced signal delaythrough shortened interconnects [3]. Moreover,monolithic wafer-level 3D integration promises in-creased functionality through the integration of di-verse technologies, while maintaining the costadvantage of monolithically fabricated intercon-nects [4]. Fig. 1 shows a schematic of an approachto 3D integration developed in the Focus Center–New York (FC–NY) [5]. A processed wafer (top)is bonded to another processed wafer (bottom)using benzocyclobutene (BCB). The top wafer isbackside thinned to a few microns of Si. Cu in-ter-wafer interconnects are formed by intercon-necting specified points in the multi-levelmetallization (MLM) layers of these two wafers,by etching, liner and Cu deposition, and chemi-cal-mechanical polishing.

There are several design and/or processing con-cerns surrounding 3D chips. One primary concernfor 3D ICs is the mechanical stability of the struc-tures [6]. It is not feasible to predict total stresses inICs, nor adhesion of the layers in ICs, and it iseven difficult to relate structural failures to specificstress levels. Standardized tests are performed toevaluate the stability of ICs. Tests have been doneto show that BCB bonding and thinning, as donein the FC–NY process flow, does not impact (pla-nar) IC performance [7], and the wafers do notdelaminate during standard reliability testing [8].It is clear that the BCB-bonded wafers are stable;

Fig. 1. 3D chip cross-sectional structure

however, the wafers in those studies did not haveinter-wafer vias. One open question is the effectof thermally induced stresses, and whether theyare significant during processing and during 3DIC operation, on inter-wafer Cu vias, as they canbe for planar ICs [1,2]. Thermally induced stressescan be predicted using structural models that rep-resent proposed structures reasonably well, andthe coefficients of thermal expansion (CTEs) ofthe materials present. In this paper, we summarizethe status of our finite element (FE) based model-ing to address the question of thermally inducedstresses in inter-wafer Cu vias to determine if theyare a cause for concern for the stability of 3D ICs,and whether more quantitative work is warranted.Computations using our FE model indicate thatthere is reason to be concerned about the reliabil-ity of inter-wafer Cu vias. However, these compu-tations had no experiments against which tocompare predicted results.

Thermal stresses in MLM structures in planarICs have been studied both experimentally andby modeling. In XRD based studies [9–11], stressesin the metal lines can be derived from the mea-sured strain due to the change of lattice spacing.Wafer curvature methods [12,13] measure thechanges in the curvature of the substrate on whicha thin film is deposited. These experiments are use-ful for comparing with averages of stresses pre-dicted by models. On the other hand they are

using ‘‘face-to-face’’ bonding [5].

J. Zhang et al. / Microelectronic Engineering xxx (2005) xxx–xxx 3

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not used to identify localized failures, e.g., individ-ual failed vias. Direct imaging of the failures incarefully prepared samples using a SEM providesdirect evidence for �qualitative comparison� withmodel predictions. Finite element based analysescan provide predictions of detailed stress distribu-tions and have been used to model the stresses anddeformation in interconnect structures. Somemodels are based on the two-dimensional planestrain assumption [14–17], in which vias and/ormetal lines extend infinitely in and out of theplane. Such models are useful for studying longmetal lines. Three-dimensional models [16,18] havebeen also used to simulate thermal stress distribu-tions in interconnect structures with complicatedgeometries. If model-predicted stresses exceed, oreven approach, the yield strength of one or morematerials, then there is cause for concern aboutthe stability. Of course, it should be kept in mindthat several assumptions routinely used in suchanalyses make quantitative comparison withexperiment tenuous [16,18], and thermally inducedstresses are only part of the total stress.

This paper is organized as follows. Reliabilitydata on 3D ICs are not available in the literature,so we first partially validate our modeling approachby comparing computed results with data on viachain test structures made with SiLK [1] or car-bon-doped silicon oxide (SiCOH) [2] as the dielec-tric. These structures are used to test reliability ofMLM in planar ICs. The failure criterion we use iswhether or not the computed von Mises stress ex-ceeds the yield strength of materials in the structure[19–21]. Then we present modeling results from ourstudy of thermal stresses in inter-wafer Cu vias thatwould form part of 3D ICs, as in the process devel-oped in the FC–NY; i.e., bonded with BCB. Targetvalues for design parameters (see Fig. 1), e.g., inter-wafer via size and pitch, and the thickness of BCB,are estimated.

2. Experimental data

In this section we review two experiments fromthe recent literature that examine the reliability ofplanar IC MLM test structures using low-k dielec-trics. Both Filippi et al. [1] and Edelstein et al. [2]

performed thermal cycle tests on via chain struc-tures. The geometry of the via chain test structureused in [1] is shown in Fig. 2 (SEM on the left).The geometry of the test structures was not com-pletely specified, and we were forced to choose rea-sonable values for some dimensions. The details ofthe structure used in [2] were not provided; in thefollowing we assume the structures are the same,with Filippi et al. [1] using SiLK as a dielectricand Edelstein et al. [2] using carbonized glass(SiCOH).

As described in [1], the repeated unit in the teststructure consists of three metal levels (MC, M1,and M2) connected by two level of vias (V1 andV2). MC and M2 are local interconnects in thechain, and M1 is a landing pad in the stackedvia structure. V1 connects MC and M1, and V2connects M1 and M2. In the experiment, the viachain is 50 units long. Some of the followingdimensions of the metal and barrier films werenot reported, and had to be assumed. Metaldimensions do not include liner thicknesses. Inter-connects (M2 and MC) are taken to be 0.35 lmlong, 0.31 lm wide lines, with an assumed heightof 0.25 lm. M1 is a 0.31 lm · 0.31 lm squarelanding pad, with an assumed 0.25 lm height.The vias are taken to be tapered cylinders0.22 lm (assumed) in diameter at the bottom and0.3 lm in diameter at the top, and 0.35 lm tall.V1, V2, M1, and M2 are Cu embedded in thelow-k dielectrics (SiLK or SiCOH). MC is tung-sten embedded in silicon dioxide. Metal lines arepassivated with a Si3N4 cap layer. Interconnectsand vias are covered with Ta-based liners at theirbottoms and side walls. Barriers and capping lay-ers are taken to be of uniform 20 nm thickness.

Both groups [1,2] cycled the temperature be-tween �65 and 150 �C at rates of 22 �C per minute(up) and �14 �C per minute (down). Filippi et al.observe statistically significant distributions ofelectrical failures of the SiLK-based system, withapproximately 50% of samples failing by 1000 cy-cles (as estimated from Fig. 5 of [1]). Fig. 3 (left)shows a failed V2 via, after the dielectric was re-moved by oxygen ashing [1]. The crack appearsto coincide with a shear plane [1]. No failure wasobserved in the SiCOH system after 1000 cycles[2].

Fig. 2. (left) Cross-sectional SEM image (with labels removed) (see Filippi et al. [1]) of the stacked via test structure using SiLK.(middle) Schematic of test structure, labeling substructures as used in the text. Note that only one quarter of the pictured structure onleft is shown in the schematic in the middle. (right) Localized details of the test structure.

Fig. 3. (left) SEM image from Filippi et al. [1] showing shearing and cracking along the bottom of a V2 via. (right) Computed vonMises stresses in Cu for SiLK-based via test structures. Note the stress concentrations near the top of the M1 landing pad and thebottom of the V2 via. Point P is 0.115 lm above the M1 along the centerline of the top via, and is at or near the point of the maximumstress in V2.


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3. Finite element model

We constructed a model in FEMLAB that issuitable for finite element analyses of the test struc-ture described above. As shown in Fig. 2 our geo-

metric model represents one quarter of the via-chain repeat unit described above. We then usedFEM-based thermoelastic analysis to computestresses and strains due to temperature changesthat are similar to those performed in the experi-


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ments [1,2]. The details of equations appropriatefor thermoelastic models can be found in manyplaces, e.g. [22]. The materials are assumed to beisotropic and linear elastic with the material prop-erties listed in Table 1. Linearity of deformationwith temperature change has been confirmed forCu by X-ray diffraction measurements over a largetemperature range (25–400 �C) [14]. The Young�smoduli, CTEs and Poisson ratios of Cu and othermaterials are considered to be temperature inde-pendent within the temperature range considered.Note that we use material properties at roomtemperature.

In order to evaluate if computed stresses indi-cate possible failure, a yield strength of Cu shouldbe chosen. The mechanical properties of thin filmscan be significantly different from bulk samples ofthe same materials. In fact, there is a large varia-tion of yield strength of Cu in the literature, andhas been reported to depend upon film thickness,grain size and temperature. For example, the yieldstrength of thin film Cu was measured from225 MPa for 3.015 lm film thickness to 300 MPafor 0.885 lm thick using a bulge test [23]. In an-other study, micromachined Cu thin film beamswere deflected until inelastic deformation was de-tected [24]. The yield strength was estimated tobe 2.8–3.09 GPa.

In order to proceed in the presence of this diver-sity, we consider a range of yield strength. Theyield strength of bulk materials is the lower limitand one estimate for thin films is the upper limit.

Table 1Materials properties used in via chain test structure simulations

Material Thickness(lm)

CTE(ppm/�C)

Young�smodulus(GPa)

Poisson�sratio

SiO2 0.6 0.5 70 0.22W 0.25 4.5 344.7 0.28SiLK 1.2 66 2.5 0.40BCB 1.2 52 2.9 0.34SiCOH 1.2 12 16.2 0.30Cu (V1, V2) 0.35 17 120.5 0.35Cu(M1, M2, MC)

0.25 17 120.5 0.35

Ta 0.02 6.5 185 0.30Si3N4 0.02 3.2 221 0.27

For bulk Cu, the yield strength of hard drawnCu wires was measured between 414 and483 MPa [25], assuming the yield strength is sameas the tensile strength. In the following, we use500 MPa, a round number, to be the lower limitof yield strength at room temperature for verysmall Cu films with small grains. For upper limitof yield strength, we assume the grain size is thesame as the via diameter in our planar IC MLMstudy, i.e., 0.22 lm. Using a Hall–Petch formula[23], the upper limit of yield strength for Cu inter-connects at room temperature is about 600 MPa.Although the lower limit is usually of most inter-est, for conservative estimates, the upper limitplays a role when comparing computed stresseswith experimental results [1,2].

We use a static analysis, which assumes that thestructure is in thermal equilibrium at the initialand final temperatures. This method has theadvantage of being quickly applied, although itdoes not take into account transient aspects ofthe temperature trajectory. Simulations are carriedout for a single temperature change. No creep/fa-tigue model related to multiple cycle tests is con-sidered in our model.

We use linear, tetrahedral finite elements withinFEMLAB [26] to obtain numerical solutions. Welocally refine the mesh in some regions to resolvethe stresses and strains in certain substructures,such as the barrier and capping layers, as shownin Fig. 4. Mesh refinement adequacy is confirmedby the lack of significant change in local stressesupon varying the mesh density used to solve themodel. A temperature change of 215 �C was im-posed on the structure, from an initial stress-freestate at 150 to �65 �C, the same as the cyclicchanges made in [1] and [2]. The periodic natureof the repeating via-chain unit is represented byapplying symmetric boundary conditions on thesides of the simulation cells that cut transverselythrough the chain direction (the ‘‘transversesides’’), allowing points on these sides to remainin-plane. The simulation cell sides that cut verti-cally through the chain and are parallel to its direc-tion (the ‘‘parallel sides’’) are also treatedsymmetrically. This set of symmetries means thatthe full linewidth of the interconnects and circularcross-section of the vias are accounted for, and

Fig. 4. Tetrahedral finite element mesh with local refinement toresolve the stresses in the barrier and capping layers.


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that the model represents a large bank of viachains fabricated in parallel lines on a 0.6 lmpitch. The bottom surface of the model is consid-ered to be bonded to a thick silicon substrateand constrained to move in-plane to remove com-ponents of rigid body motion of the cell from

Fig. 5. Computed von Mises stresses in SiLK-based system (left) andM1, and M2 Cu is above the top range of yield strength (600 MPa) irange of yield strength (500 MPa) for the SiCOH system.

entering the FEM computation. The top surfaceis free to move, and the structure is taken to beat a stress-free reference state at its maximumtemperature.

Fig. 5 shows calculated von Mises stressesthroughout both the SiLK-based and SiCOH-based structures, and Fig. 3 (right) shows thevon Mises stresses in just the Cu on an expandedscale for the SiLK system. Points where the vonMises stress exceeds the yield stress of Cu indicatesites of potential failure. The thermoelastic modelpredicts that the stresses in the Cu vias in SiLK ex-ceed the upper limit of yield strength of Cu(600 MPa). However, the stresses in Cu in SiCOHare below the lower limit of yield strength(500 MPa). The CTE of SiLK over temperatureranges common to BEOL processing is about66 ppm/�C [27], which is considerably larger thanthat of Cu (approximately 17 ppm/�C [17]) in thesame temperature range. From our results, it isnot surprising that the strain induced in Cu metal-lization during temperature changes can lead todegradation and failure. Compared with SiLK,the CTE of SiCOH (12 ppm/�C [28]) is close tothat of Cu. The thermal stresses in the Cu viaare substantially lower.

Some parametric studies were performed todetermine the sensitivity of our computed resultsto the model parameter values used; i.e., we varymaterials� properties within reasonable ranges toidentify the effects on thermal stresses. Fig. 6shows computed von Mises stresses at point P inFig. 3, which is 0.115 lm above M1 along the axisof V2. This point is at or near the point of the max-

SiCOH-based system (right). Note that almost of all of the V1,n the SiLK system. None of the Cu is above the bottom of the

Fig. 6. Calculated stress at point P from Fig. 3, as a function ofthe Young�s modulus and CTE of the surrounding dielectric.Poisson�s ratio is taken to be 0.4.

Fig. 7. Stress distributions along the Cu via embedded in SiLKwith and without barrier layers. The thick dark line in the insertshows the positions along the via where the stress values weretaken.


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imum stress in V2, and the stress here increaseswith increasing Young�s modulus, CTE, and Pois-son�s ratio. This figure, in combination with yieldstrength, provides a failure criterion for Cu viasunder different combinations of materials proper-ties. As is reasonable, the figure also suggests thatdielectric materials with lower Young�s moduli andCTEs can reduce stresses in the Cu.

One concern in our simulation study is thetreatment of the very thin barrier and cappingfilms; e.g., we assume they are of uniform thick-ness, and ignore their granularity. That is consis-tent with using idealized geometries for the viasand lines. However, small variations will have alarger effect on them than for the thicker materials.It is also not clear how the various material inter-faces impact results. We assume ideal, perfectlyadhesive films. We feel that it is important togauge the effect of including barrier and cappingfilms on the stresses calculated in our simulations.Simulations show that the stresses along the centerof the top and bottom vias are about 10% higherwhen the volume occupied by barriers is replacedby Cu (Fig. 7). It is higher because barrier filmsare stiffer than Cu, and the stresses are higher inthe barrier films when they are included. As longas the barrier layers are thin, it does not mattermuch if they are included, or ignored, in the com-putations. They do not substantially change the

stress distributions in the vias. It should also benoted that the stresses computed in the barrierssurrounding the failed vias are larger than the yieldstrength of Ta (�350 MPa) [29] and the barrierscould be expected to fail. In that case, ignoringthem may provide a reasonable model for the localmechanical structure. The barrier and etch stoplayers are not considered in the models of 3D ICstructures discussed in the next section.

4. Thermal stress in 3D IC structures

We perform 3D IC simulations to calculatestress in a representative unit cell. The model con-sists of seven layers with embedded Cu intercon-nects (Fig. 8). In order to derive design relatedparameters and make the simulation tractable,we choose a repeated unit cell in the 3D IC struc-tures (Fig. 8). The top silicon wafer (L3) is thinnedto 10 lm thick and bonded to the bottom waferusing a 2.6 lm thick BCB (L5). The bottom siliconwafer is not included in the unit cell model due toits large volume. Circular Cu vias, with an as-sumed 23.6 lm height, connect 10 lm thickMLMs (L4, L7) in the two wafers. Square landingpads are used at the end of Cu vias and embeddedin the oxide layers (L1, L2, L7). Due to symmetryin the x–z and y–z planes (Fig. 8), only one quarterof unit cell is used in the simulations. Barrier mate-

Fig. 8. 3D IC structure. (a) Schematic of several cylindrical via connecting square landing pads through the layered structure (not toscale). The dot-marked block is the unit cell. (b) A typical finite element mesh. Taking advantage of symmetry, only one quarter of avia and pad has been included in the geometric model.


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rials are not considered in the model due to theirsmall thicknesses, and as discussed above theirpresence does not significantly affect computedstresses in our model of planar IC structures.The structure is assumed stress-free at 250 �C (wa-fer bonding temperature). The material propertiesand dimensions of the model are given in Table 2.Young�s modulus of BCB is found to decrease withtemperature from 2.5 GPa at 25 �C to 0.3 GPa at180 �C [30]. To be conservative, we use the valueat 25 �C, which will tend to over-predict the stres-ses in the Cu. We use the room temperature valueof CTE for BCB, which wafer-curvature experi-ments [31] show to be largely temperature indepen-dent. For other material properties of purematerials, e.g., Poisson�s ratio of Cu, we use mate-

Table 2Material properties used in 3D IC simulations

Material Thickness(lm)

CTE(ppm/�C)

Young�smodulus (GPa)

Poisson�sratio

SiO2 1 0.5 70 0.22Si 10 3.725 130.1 0.278MLM 10 5 85 0.26BCB 2.6 52 2.9 0.34Cu (via) 23.6 17 120.5 0.35Cu (pad) 1 17 120.5 0.35

rial properties widely reported at room tempera-ture. The material properties of the MLM layerare determined by the volume average of eachcomponent (30% Cu and 70% SiO2) [32]. Formechanical boundary conditions, the side wallsof the unit cell are only allowed to shift withintheir respective planes due to symmetry, as is thebottom surface, which is assumed perfectly bondedto the thick silicon substrate below. The top sur-face is left free to move. As seen in the right halfof Fig. 8, the finite element mesh is refined in areaswhere large stress gradients are expected.

Fig. 9 shows the distribution of von Mises stressin the unit cell for via sizes from 1 to 6 lm in diam-eter and a pitch of 20 lm, for an initial tempera-ture of 250 �C and a final temperature of 25 �C.The stresses in the via decrease as the via diameterincreases. Fig. 10 shows the von Mises stress at thecenter the Cu vias half way up the BCB layer forvias from 1 to 6 lm in diameter and pitches of10, 20 and 40 lm. The order of CTEs of the mate-rials is: BCB > Cu > MLM > Si > SiO2, and theBCB layer is quite thin. A back-of-the-envelopecalculation shows that the unconstrained thermalcontraction of the Cu vias were they not in thestack is �84 nm. This is significantly larger thanthe unconstrained thermal contraction of the stack

Fig. 9. Computed von Mises stresses in 3D IC structure with via size of 1, 2, 4 and 6 lm for 20 lm pitch.

0

0.4

0.8

1.2

1.6

0 2 4 6 8Via size, micron

von

M is

es s

tres

s, G

Pa

pitch 40 micronpitch 20 micronpitch 10 micron Yield strength of Cu

Fig. 10. Computed maximum von Mises stress in Cu vias ofdifferent diameter and different pitch with a BCB thickness of2.6 lm.


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of material in parallel with the Cu vias (�55 nm).Thus, in the 3D IC stack in which the vias are cou-pled to the other materials, the Cu vias act to con-strain the vertical expansion of the entire structure.At each pitch, the maximum von Mises stress inthe Cu increases as the via size decreases. Thistrend makes sense; as the cross-section of the Cudecreases the amount of stack it must constrain in-creases. The calculated von Mises stress decreaseswith decreasing pitch at constant via size, as theforce per unit area is distributed to more vias.Our simulations indicate that plastic deformationof the vias is a concern. Combining yield strengthsof Cu discussed in Section 3, we can estimate sometarget values for design parameters. The lower lim-

it of yield strength (500 MPa) can be used for aconservative design. As shown in Fig. 10, the viasize should be larger than 3 lm at a pitch of10 lm, and 3.5 lm at a pitch of 40 lm.

Simulations were performed to evaluate the useof BCB bonding with small Cu vias at smallpitches, such as might be used to bond logic andmemory circuits. We assume a via diameter of1 lm, vary the via pitch from 5 to 20 lm, and varythe BCB thickness from 0.5 to 3 lm. As shown inFig. 11, the stress 0.5 lm along the centerlineabove the lower landing pad, the thickness ofBCB should be less than 1 lm, using yield strengthof Cu 500 MPa, to avoid plastic yield of Cu viasfor even the smallest pitch studied. This is due tothe relatively high CTE of BCB compared to Cu.Although the ‘‘unconstrained stack’’ discussedabove contracts approximately 55 nm, approxi-mately 60% of that motion would come from the2.6 lm of BCB. Over that same length, Cu con-tracts only 10 nm when unconstrained, so whenthey are coupled to each other, a significant com-pressive stress is induced in the lowest part of thevia during cooling. By reducing the thickness ofthe BCB layer, this expansion can be reduced inmagnitude, and the stress in the bottom of thevia is reduced.

We also studied the effect of imposed tempera-ture changes on the thermal stresses. Simulationsof different initial stress-free temperatures, 150and 350 �C, and cooling down to room tempera-

0

0.4

0.8

1.2

1.6

0 1 2 3 4Thickness of BCB, micron

von

Mis

es s

tres

s, G

Pa

pitch 20 micronpitch 10 micronpitch 5 micronYield strength of Cu

Fig. 11. Computed maximum von Mises stress in Cu vias fordifferent BCB thickness and pitch with vias 1 lm in diameter.


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ture were performed to study thermal stress levels.The maximum von Mises stress in the Cu via isshown in Fig. 12. As expected, the stress increasesas the initial temperature increases. In [1], a thresh-old temperature range of 145.3 �C (Table 1 in [1])was found from statistical analysis of mean-cycle-to-failure, N50, as a function of temperaturechanges DT (Tmax was 150 �C, DT varied from150 to 300 �C) (Fig. 8 in [1]). Below this thresholdtemperature the test structures did not fail. Oursimulations also show that the magnitude of tem-perature change is a major factor determining thestress level in the inter-wafer vias. If the structurescool down to room temperature, the maximumprocessing temperatures determine the thermalstress levels. The stress data are normalized bythe temperature difference between initial and final

0

0.5

1

1.5

2

2.5


von

Mis

es s

tres

s, G

Pa

350->25C

250->25C

150->25C

Yield strength of Cu

Fig. 12. Computed maximum von Mises stress in Cu vias ofdifferent size cooling from 150, 250 and 350 to 25 �C.

temperatures and plotted in Fig. 13. As expectedfor a linear analysis, the stresses at different initialtemperature collapse into a single curve. There-fore, when thermally induced stress informationis available for some temperature ranges, it is pos-sible to extend this information into other temper-ature windows through this procedure.

Issues in addition to stresses in Cu can be ofinterest. As discussed above, Cu vias contractmore than the surrounding materials, thus pullingdown on these neighboring materials to which theyare coupled. For example, Fig. 14 shows thatroughness is introduced into the top surface ofthe 3D IC structure; the vias and their surround-ings are lower than areas away from the vias. Thisroughness, which can be on the order of 100 nm,may affect the downstream processes, and theadhesion of layers on deposited after bondingand thinning. Fig. 14 also shows the side view ofdisplacement in the vertical direction. The samesimulation was repeated with different via sizes,ranging from 2 to 6 lm. The resulting vertical dis-placements of the top surface are shown in Fig. 15.The size of the depressed area increases with viasize due to both the larger via diameters and theincreased constraining forces transmitted by thevia.

As indicated in Fig. 9, at constant via pitch(20 lm), the maximum von Mises stress shifts fromthe Cu vias to the top Si substrate as the via sizeincreases. At relatively low via densities (<6% areafraction), the maximum stress was observed in theCu vias. Results suggest that Cu vias smaller thana critical size will yield plastically. As the via den-sity increases (>10%), the maximum stress gradu-ally shifts to the top, thinned, Si substrate.Potential yield or failure locations (e.g., failure inCu versus Si) are also related to this critical viadensity. For brittle materials, such as Si, the criti-cal fracture stress is a function of any flaw or exist-ing damage to the specimen [33]. Such damage canbe caused by wafer processing, such as grinding,etching. A carefully polished Si specimen has anaverage fracture stress as high as 800 MPa [34].On the other hand, a backside processed waferhas the fracture stress only 175 MPa [34]. In oursimulations, the maximum stresses in Si occur inthe vicinity of the interface between the Si and

0

1

2

3

4

5

6

7


Nor

mal

ized

von

Mis

es s

tres

s, M

Pa/

˚C 350->25C

250->25C

150->25C

Fig. 13. Normalized maximum von Mises stress by temperature change in Cu vias of different size, cooling from 150, 250 and 350 to25 �C.

Fig. 14. (left) Contour and isosurface (white curves) of vertical displacement (z) of the top surface of the 3D IC structures calculatedfor vias of 6 lm, a pitch of 20 lm, and a BCB thickness of 2.6 lm. The structure contains 15 unit cells (see Fig. 8(b)). A unit cell isremoved to reveal internal displacement. The black dashed line indicates the top of the slice shown on the right side of the figure. Theblack dashed line is also the location where the vertical displacements are measured in Fig. 15. (right) Side view of vertical displacement(z) calculated with via of 6 lm. The white curves indicate isosurfaces of vertical displacements. The black lines delineate theundeformed structure.


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the Cu vias. As the via density reaches approxi-mately 10%, the stress in Si exceeds the above esti-mate of the critical fracture stress. The shift in thelocation of the maximum stress can be understoodby considering that the Cu via is in parallel with

the other materials; i.e., the Cu vias need to dealwith the forces exerted by their surroundings. Asvia size increases or via density increases, the totalCu area increases. So, stresses are lower for thesame forces.

-0.13

-0.125

-0.12

-0.115

-0.11

-0.105

-0.1

-15 -10 -5 0 5 10 15Diagonal distance, micron

Ver

tica

l dis

plac

emen

t, m

icro

n

via size 2 micron

via size 4 micron

via size 6 micron

Fig. 15. Vertical displacement along the diagonal direction (seeFig. 14 pitch is 20 lm). Note the expanded vertical axis.


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Several avenues to improve our analysis havebeen identified. First, in this paper, we partiallyvalidated our model using planar IC data [1] bycomparison with experimental failure information– a qualitative response. The stress level at whichvias fractured rather than just underwent plasticdeformation was not studied in [1], and we arenot aware of any such data in the literature. Previ-ous studies [15,35,36] show that stresses predictedusing FEM are higher than measured volume-averaged stresses. Though conservative computa-tions are better than those that produce falseassurances of stability, it would be better to ex-plain the differences, and refine the models. Thiseffort will also be useful to evaluate assumptionsin our model that the initial stress at high temper-atures in the structure is zero. Thermal stress mea-surements using XRD of Cu lines passivated withTEOS oxide and methyl silsesquioxane dielectricsshow that, depending on the processing condi-tions, initial stress at 400 �C may be on the orderof 100 MPa [36]. A careful evaluation of initialstresses is necessary for proper prediction of ther-mal stresses. Second, in our simulations, materialsare assumed to be homogeneous and no informa-tion on microstructure is explicitly included. Ithas been shown that stress levels increase withincreasing average grain size for 0.35 lm Cu lineswith passivation [37]. Grain boundaries are inter-faces which serve as stress relaxation sites. Increas-ing the grain size reduces the number of grainboundaries and lead to the higher stresses. A mod-

el linking stress and microstructure would be use-ful to our analysis. In addition, any gaps in thestructure, such as might occur during depositionin features, will decrease thermally induced stres-ses. In order to improve our understanding oftopography, microstructure and/or failures of Cuvias during thermal cycles, process models, e.g.,EVOLVE [38,39] or PLENTE [40,41] should beincorporated into the computations. Finally, thestatic analysis performed in this study does not ac-count for any effects of creep or fatigue. Von Misesstresses are used to predict plastic deformation,but not all structures destined to fail due to ther-mally induced stress do so with a simple tempera-ture change, nor does plastic deformation alwayslead to electrical failure.

5. Conclusions

We presented a finite element based model inorder to evaluate whether thermally induced stres-ses in Cu inter-wafer vias used in BCB-bonded(wafer level) 3D ICs are a reliability concern.Our modeling approach was first tested againstdata obtained from thermal cycling experimentson planar IC MLM via structures with Cu inter-connects and low-k dielectrics. Computed vonMises stresses, assuming a single cooling step ofthe same magnitude as the experiments, are at amaximum near the bottom of vias in the test struc-ture, which coincides with experimental observa-tions of failure when SiLK was used. No failurein the via is predicted when SiCOH was used asthe dielectric, which is consistent with experiments.

We then calculated thermal stresses in 3D ICstructures bonded with BCB using a process devel-oped at FC–NY, due to changing temperaturefrom 250 to 25 �C. Simulations show that thevon Mises stresses in the Cu vias decrease withdecreasing pitch at constant via size, increase withdecreasing via size at constant pitch, and decreaseswith decreasing BCB thickness. We found that fur-ther study is indeed warranted; i.e., the stresses inCu vias either exceed or are close to the yield stressfor temperature changes similar to those used inBEOL processing and inter-wafer via pitches andvia sizes that may reasonably be used in 3D ICs.


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Our results also support the goal of using thinBCB. In general thin BCB has been targeted in or-der to keep via aspect ratios down; however, ithelps also keep the via stresses due to BCB con-tractions and expansions down as shown byFig. 11, and discussed in Section 4. Target valuesfor design parameters, e.g., inter-wafer via size,pitch, and the thickness of BCB, were estimated.To improve upon the reliability of such design ori-ented computations, more quantitative simulationwork is needed; i.e., to compare computed stresseswith measured stresses.

Acknowledgements

The authors acknowledge support for this workfrom MARCO, DARPA and NYSTAR throughthe Interconnect Focus Center.

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thermal stresses in 3d ic inter-wafer interconnects

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