cu nanolines for rf interconnects: electrical characterization

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This article has been accepted for inclusion in a future issue of this journal. Content is final as presented, with the exception of pagination. IEEE TRANSACTIONS ON ELECTRON DEVICES 1 Cu Nanolines for RF Interconnects: Electrical Characterization Panagiotis Sarafis, Chuan-Lu Hsu, Philippe Benech, and Androula G. Nassiopoulou Abstract—In this paper, we investigated the RF properties of Cu nanolines that are arranged in a coplanar waveguide (CPW) configuration. The signal tracks for the CPW transmission lines (CPW TLines) were either single Cu nanolines or multiple parallel Cu nanolines of equal total width and varying number. The total width was kept constant in order to study the validity of the litz-wire concept on the on-chip integrated CPW TLines. The metallization thickness was 100 nm and their width ranged from 50 nm to 1 μm. The RF characteristics of the nanolines were measured in the frequency range 40 MHz–40 GHz and the results were compared with those obtained from electromagnetic simulations. For these frequencies and nanolines dimensions, no improvement was observed when splitting the single line into multiple parallel lines. On the contrary, the resistance was increased according to the corresponding resistivity increase. Index Terms— Coplanar waveguides (CPWs), Cu transmission lines, nanolines, RF. I. I NTRODUCTION I T IS well known that CMOS technology evolved by scaling down the transistor dimensions. This evolution improves the performance of the integrated circuits (ICs) and reduces the power consumption and the cost of a single chip. The scaling of the transistor unavoidably leads to the continuous scaling of interconnects to a level where their response becomes increasingly crucial for the total system performance. This is because size reduction of interconnect lines compromises their performance [1] and the interconnect length increases as the integration density of the ICs increases. As the dimensions decrease, both the resistivity of the lines increases [2] and the electromigration resistance deteriorates. According to the International Technology Roadmap for Semiconductors [3], the lateral dimensions of the interconnects in logic circuits are expected to be greatly reduced in the coming years. Namely, the minimum pitch of the local interconnects that lay in the first metal layer (M1) and the Manuscript received September 11, 2014; revised January 16, 2015 and February 20, 2015; accepted February 28, 2015. This work was supported by the European Network of Excellence Nanofunction through the European Seventh Framework Programme for Research under Contract 257375. The review of this paper was arranged by Editor M. S. Bakir. P. Sarafis and A. G. Nassiopoulou are with the Institute of Nanoscience and Nanotechnology, National Centre for Scientific Research Demokritos, Athens 60228, Greece (e-mail: p.sarafi[email protected]; [email protected]). C.-L. Hsu and P. Benech are with the Institut de Microélectronique Electromagnétisme et Photonique-Laboratoire d’Hyperfréquences et de Caractérisation, Université de Grenoble, Grenoble 38016, France (e-mail: [email protected]; [email protected]). Color versions of one or more of the figures in this paper are available online at http://ieeexplore.ieee.org. Digital Object Identifier 10.1109/TED.2015.2409478 intermediate level interconnects (M2–M4) will be 42 nm in 2015 and 24 nm in 2020. For the case of semiglobal and global interconnects, the projected minimum pitch starts from two times the M1 pitch up to almost 2 μm. The thickness of these layers varies from 100 nm of Cu for the lower layers to >2 μm of Cu or Al for the top metal layers. Toward minimizing the ICs’ latency introduced by the interconnects, part of the effort is put into the investigation of using alternative materials for replacing the current Cu technology [4]. The main focus is on carbon nanotubes (CNTs), as they exhibit almost ballistic transport and increased electromigration immunity compared with Cu [5]. However, the integration of the CNTs into the well-established CMOS technology is still a challenging task [6] and is not projected to take place within the next few years. This is why it is still interesting to study the properties of Cu, especially in the crucial dimensions that were mentioned above. Up to now, intense research was devoted to the investigation of the dc characteristics of Cu and other metal nanowires [2], [7]. The resistivity of Cu nanolines has been thoroughly investigated during the previous decade, as it was one of the crucial factors for the continuing CMOS scaling [8]–[12]. However, the RF properties of thin metal nanowires are only recently studied [13]–[17] and the main focus is on the accuracy of the measurements and the deembedding procedure in order to separate the contact resistance effect from the actual nanowire properties. Only few works are devoted to the RF properties of nanoscaled Cu [17]–[21]. The feasibility of using in RF-CMOS the lower level metal layers in the back-end-of-line, with smaller thickness than the top metal layers, is of great interest for the next-generation CMOS nodes. In this paper, we focused on the RF properties of thin Cu nanolines with linewidth below 1 μm. Getting inspired from the idea used in the litz wires, we studied the effect of using multiple parallel nanolines for the signal track instead of a single one with the same total width. The presented Cu nanolines had a varying linewidth from 50 nm to 1 μm and a thickness equal to 100 nm. The nanolines were in single and multiple lines configuration and were used as the signal track of a coplanar waveguide transmission line (CPW TLine). All the devices were fabricated on a thick porous Si layer in order to eliminate the RF losses into the substrate, as it has been demonstrated in [22]–[26]. The CPW configuration on porous Si has been chosen instead of the microstrip one, because of the possibility it offers to design and realize transmission lines with high characteristic 0018-9383 © 2015 IEEE. Personal use is permitted, but republication/redistribution requires IEEE permission. See http://www.ieee.org/publications_standards/publications/rights/index.html for more information.

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This article has been accepted for inclusion in a future issue of this journal. Content is final as presented, with the exception of pagination.

IEEE TRANSACTIONS ON ELECTRON DEVICES 1

Cu Nanolines for RF Interconnects:Electrical Characterization

Panagiotis Sarafis, Chuan-Lu Hsu, Philippe Benech, and Androula G. Nassiopoulou

Abstract— In this paper, we investigated the RF properties ofCu nanolines that are arranged in a coplanar waveguide (CPW)configuration. The signal tracks for the CPW transmissionlines (CPW TLines) were either single Cu nanolines or multipleparallel Cu nanolines of equal total width and varying number.The total width was kept constant in order to study the validityof the litz-wire concept on the on-chip integrated CPW TLines.The metallization thickness was 100 nm and their width rangedfrom 50 nm to 1 µm. The RF characteristics of the nanolineswere measured in the frequency range 40 MHz–40 GHz and theresults were compared with those obtained from electromagneticsimulations. For these frequencies and nanolines dimensions,no improvement was observed when splitting the single lineinto multiple parallel lines. On the contrary, the resistance wasincreased according to the corresponding resistivity increase.

Index Terms— Coplanar waveguides (CPWs), Cu transmissionlines, nanolines, RF.

I. INTRODUCTION

IT IS well known that CMOS technology evolved byscaling down the transistor dimensions. This evolution

improves the performance of the integrated circuits (ICs) andreduces the power consumption and the cost of a singlechip. The scaling of the transistor unavoidably leads to thecontinuous scaling of interconnects to a level where theirresponse becomes increasingly crucial for the total systemperformance. This is because size reduction of interconnectlines compromises their performance [1] and the interconnectlength increases as the integration density of the ICs increases.As the dimensions decrease, both the resistivity of the linesincreases [2] and the electromigration resistance deteriorates.According to the International Technology Roadmap forSemiconductors [3], the lateral dimensions of the interconnectsin logic circuits are expected to be greatly reduced in thecoming years. Namely, the minimum pitch of the localinterconnects that lay in the first metal layer (M1) and the

Manuscript received September 11, 2014; revised January 16, 2015 andFebruary 20, 2015; accepted February 28, 2015. This work was supportedby the European Network of Excellence Nanofunction through the EuropeanSeventh Framework Programme for Research under Contract 257375. Thereview of this paper was arranged by Editor M. S. Bakir.

P. Sarafis and A. G. Nassiopoulou are with the Institute ofNanoscience and Nanotechnology, National Centre for Scientific ResearchDemokritos, Athens 60228, Greece (e-mail: [email protected];[email protected]).

C.-L. Hsu and P. Benech are with the Institut de MicroélectroniqueElectromagnétisme et Photonique-Laboratoire d’Hyperfréquences et deCaractérisation, Université de Grenoble, Grenoble 38016, France (e-mail:[email protected]; [email protected]).

Color versions of one or more of the figures in this paper are availableonline at http://ieeexplore.ieee.org.

Digital Object Identifier 10.1109/TED.2015.2409478

intermediate level interconnects (M2–M4) will be 42 nmin 2015 and 24 nm in 2020. For the case of semiglobal andglobal interconnects, the projected minimum pitch starts fromtwo times the M1 pitch up to almost 2 μm. The thickness ofthese layers varies from 100 nm of Cu for the lower layersto >2 μm of Cu or Al for the top metal layers.

Toward minimizing the ICs’ latency introduced by theinterconnects, part of the effort is put into the investigationof using alternative materials for replacing the currentCu technology [4]. The main focus is on carbonnanotubes (CNTs), as they exhibit almost ballistic transportand increased electromigration immunity compared withCu [5]. However, the integration of the CNTs into thewell-established CMOS technology is still a challengingtask [6] and is not projected to take place within the nextfew years. This is why it is still interesting to study theproperties of Cu, especially in the crucial dimensions thatwere mentioned above. Up to now, intense research wasdevoted to the investigation of the dc characteristics of Cu andother metal nanowires [2], [7]. The resistivity of Cu nanolineshas been thoroughly investigated during the previous decade,as it was one of the crucial factors for the continuingCMOS scaling [8]–[12]. However, the RF properties of thinmetal nanowires are only recently studied [13]–[17] andthe main focus is on the accuracy of the measurements andthe deembedding procedure in order to separate the contactresistance effect from the actual nanowire properties. Onlyfew works are devoted to the RF properties of nanoscaledCu [17]–[21].

The feasibility of using in RF-CMOS the lower level metallayers in the back-end-of-line, with smaller thickness than thetop metal layers, is of great interest for the next-generationCMOS nodes. In this paper, we focused on the RF propertiesof thin Cu nanolines with linewidth below 1 μm. Gettinginspired from the idea used in the litz wires, we studiedthe effect of using multiple parallel nanolines for the signaltrack instead of a single one with the same total width. Thepresented Cu nanolines had a varying linewidth from 50 nmto 1 μm and a thickness equal to 100 nm. The nanolineswere in single and multiple lines configuration and wereused as the signal track of a coplanar waveguide transmissionline (CPW TLine). All the devices were fabricated on a thickporous Si layer in order to eliminate the RF losses intothe substrate, as it has been demonstrated in [22]–[26]. TheCPW configuration on porous Si has been chosen insteadof the microstrip one, because of the possibility it offers todesign and realize transmission lines with high characteristic

0018-9383 © 2015 IEEE. Personal use is permitted, but republication/redistribution requires IEEE permission.See http://www.ieee.org/publications_standards/publications/rights/index.html for more information.

This article has been accepted for inclusion in a future issue of this journal. Content is final as presented, with the exception of pagination.

2 IEEE TRANSACTIONS ON ELECTRON DEVICES

impedance and low losses [27]. The nanolines werecharacterized from 40 MHz up to 40 GHz and the results werecompared with those obtained from full-wave electromagneticsimulations.

II. FABRICATION

A. Substrate

The use of a thick porous Si layer underneath anRF component has been demonstrated to provide efficientshielding from the lossy Si substrate in the whole fre-quency range from dc to millimeter-wave frequencies [27],[28]. The Cu nanolines were, thus, fabricated on a 150-μm thick porous Si layer. The characteristics of the spe-cific layer used were a porosity of 72%, a relative permit-tivity of εr ∼ 3.5, and a loss tangent of tanδ = 0.03.The porous Si layer was capped with a 500-nm thickTEOS (tetraethyl orthosilicate) oxide in order to stabilize itover the time.

B. Copper Nanolines

The devices-under-test included both dc and RF teststructures. The dc structures were used to measure theresistivity of the Cu nanolines. The RF test structures wereCPW TLines, where the Cu nanolines were used as the centralsignal track. They were fabricated on a porous Si substrateusing e-beam patterning, followed by Cu deposition and liftoff.For Cu deposition, electron gun evaporation [physical vapordeposition (PVD)] was used. The metal pads were made ofthe same 100-nm thick Cu metal layer as the nanolines andwere fabricated in the same process step with the nanolines.For enhancing Cu adhesion on the capping SiO2 layer,a thin Ti layer (∼10-nm thick) was first deposited on theoxide layer.

Two different CPW TLine configurations were used. In thefirst configuration, the CPW signal track was composed of asingle nanoline of changing width. In the second configuration,the signal track was composed of a changing number of mul-tiple parallel nanolines of the same linewidth, while keepingconstant the total width of the signal track (wT ) as well as thetotal width of the metal without the interline spacing (wCu).The single nanolines had different widths, namely, 50, 75,100, 150, 200, 250, 300, 400, 500, and 1000 nm andtwo different lengths, 92 and 492 μm. The multiple nanolineshad four different widths, i.e., 100, 200, 500, 1000 nm andtwo different lengths as in the case of the single lines. Severalsets of CPW TLines were fabricated for each linewidth inorder to verify the repeatability of the results.

The lateral size of the standard RF probe tips is ∼50 μmand their characteristic impedance (Zc) is 50 �. On the otherhand, the width of the nanolines is as low as 50 nm andtheir characteristic impedance is Zc > 1000 �. The largeimpedance mismatch between the nanolines and the measuringsystem affects the accuracy of the measurements. In order toreduce the effect of the mismatch and improve measurementaccuracy, the pad design should be carefully chosen. In thisrespect, a tapered feed is used [14], [29]. Top view scanning

Fig. 1. Left (top to bottom): top view SEM image of a CPW TLinewith multiple parallel Cu nanolines of width 200 nm (top image) and withzoomed-in view at the interface areas between the tapered contact pad and theCu nanolines (middle and bottom images). Right (top to bottom): top viewSEM image of a Cu CPW TLine with a single 200-nm wide Cu nanoline asthe signal track (top image) and zoomed-in view at the interface areas betweenthe tapered contact pad and the Cu nanolines (middle and bottom images).The dimension wT denotes the total width of the signal track incorporatingthe interline spacing and s the gap between the signal track and the ground.

Fig. 2. Simplified RLC circuit model of a conventional transmission line.Because of the good RF shielding by the thick porous Si layer, we can neglectsubstrate losses.

electron microscopy (SEM) images of the fabricated devicesare shown in Fig. 1.

III. MODELING OF THE TRANSMISSION LINE

A. Transmission Line Model

The most commonly used model of a conventionaltransmission line is the RLCG circuit model. As the fabricatedCPW TLine is placed on thick porous silicon layer, thesubstrate losses are negligible [22] and we can neglectthe conductance term (G) of the RLCG model, resultingin the simplified RLC model shown in Fig. 2. Theper-unit-length (p.u.l.) series resistance (R) represents theconductor losses, the shunt p.u.l. capacitance (C) representsthe capacitance between the line and the ground planes, andthe p.u.l. inductance (L) represents the sum of the magneticinductance caused by the magnetic field and the kineticinductance caused by the momentum of the moving electrons.

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SARAFIS et al.: Cu NANOLINES FOR RF INTERCONNECTS 3

The conventional RLCG model is valid as long as thekinetic inductance (L K ) is very small compared with themagnetic one (L M/L K � 1). This occurs when the numberof propagation modes is above a critical value Mc ∼ 104 [19].This condition is fulfilled when the cross section of thenanolines is >10 nm × 10 nm. For smaller dimensions,a new model has to be used, considering L K and thequantum capacitance. These last effects, well studied in thecase of CNTs [30]–[32], are negligible for the Cu nanolinesunder investigation as their minimum dimensions are50 nm × 100 nm [19].

In order to have a complete description of the CPW TLine,it is useful to present the correlation between the RLC modeland the values of Zc and the propagation constant (γ)

γ = α + jβ = √(R + jωL)( jωC) (1)

Zc =√

R + jωL

jωC(2)

where a is the attenuation constant, β is the phase constant,and ω is the angular frequency of the wave.

B. Contact Impedance

One of the most critical points in the characterization of aCPW TLine is the impedance of the pad-nanoline contact [14].The contact effect is extensively studied in the literature for thecase of CNTs and individual metal nanowires (see for examplereferences [13], [33]). For an individual nanowire, the contactimpedance can be described by a parallel combination of acontact resistance and a contact capacitance [20].

In the present experiments, both the host CPW TLine(containing the contact pads and the ground lines) andthe Cu nanolines (signal track) were fabricated in a singledeposition step in order to avoid any contact impedancebetween the lines and pads. Therefore, the analysis presentedhere is not affected by the contact impedance. The removal ofthe effect of the surrounding structures (hosting CPW, taper)and the isolation of the line characteristics is performedthrough the deembedding procedure.

IV. MEASUREMENTS, DEEMBEDDING, AND SIMULATIONS

A. Resistivity Measurements

In order to have an accurate analysis of the RF propertiesof the Cu nanolines, the resistivity of these lines should beextracted first. The decrease of the width and the thicknessof a metal line down to nanometer dimensions leads tohigher resistivity due to the increased contribution of thesurface and grain boundaries scattering. This effect is knownin the literature for Cu nanolines. Such an example fornanolines, fabricated by electroplating, is given in [34]. Wedetermined the resistivity of the specific Cu nanolines usedin this paper following a method that is not based on adirect measurement of the geometrical dimensions of thenanoline, but uses the temperature variation of the nanolineresistance (dR/dT) to deduce its resistivity [11]. With thismethod, we avoid the effect of inaccuracies in the dimensionsthat become significant when the thickness and width of

Fig. 3. Measured (points and black dashed line) and literature roomtemperature resistivity values (red dotted line) [2] of 100-nm thickCu nanolines as a function of their linewidth. The Cu in this paper wasfabricated by PVD, while in the literature by electroplating. The differencein resistivity of the two materials is a result of the larger grains of theelectroplated Cu compared with the PVD Cu.

the nanoline decreases. We first extracted dR/dT fromcurrent–voltage measurements in the temperaturerange 200–350 K and then we used this value for eachnanoline in order to extract the corresponding resistivity.

Fig. 3 shows the obtained results of the resistivity at roomtemperature of our Cu nanolines, fabricated by electron gunPVD, in comparison with literature results for electroplatedCu [2]. In both cases, the thickness of the lines was 100 nm.The same trend of resistivity increase with decreasing theline width below ∼400 nm is observed. It can be also seenthat the resistivity of our PVD lines is slightly higher thanthat of the electroplated lines [2]. This difference can beunderstood by differences in the grain size of the electroplatedand PVD Cu material. The grains in the electroplated materialare larger than the ones obtained by PVD [35], leading tolower resistivity. As the linewidth gets smaller than two timesthe thickness of the line, the grain size of the electroplatedlines in the lateral dimension is equal to the linewidth [8].This is expected to be the same in the PVD films of thispaper. The similar grain size of Cu nanolines (obtained byboth techniques) narrower than the double of their thickness(<200 nm) explains the convergence of the resistivity ofCu nanolines for these linewidths.

B. RF Measurements, Deembedding, and HFSS Simulation

Device characterization was performed through S-parametermeasurements for frequencies up to 40 GHz with anAnritsu 37269D vector network analyzer and Cascade Ground-Signal-Ground Infinity probes with 100-μm pitch. As theoutput resistance of the measurement equipment is 50 �and the line characteristic impedance can be >1000 �, theextraction of the intrinsic RF parameters of the nanoline isquite challenging. The deembedding was based on a two-linesmethod [37], as it has been proved to provide more accurateresults [36].

All the measured devices were also simulated usingAnsys HFSS (High Frequency Structural Simulator) v.13 inorder to compare the simulated results with the experimental

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4 IEEE TRANSACTIONS ON ELECTRON DEVICES

Fig. 4. Attenuation (left graph) and phase constant (right graph) versusfrequency of the single track CPW TLines for various linewidths. Thenon-monotonicity of the 50-nm line is probably due to inaccuracies ofmeasurements caused by the large impedance mismatch in that case.

results. This software is a 3-D electromagnetic solver basedon the finite-element method. The dimensions that were usedfor the geometrical model were extracted from the methoddescribed in [2], combined with accurate thickness measure-ments. The Cu resistivity used for each line was the oneextracted by the method described in Section IV-A.

V. RESULTS AND COMPARISON WITH SIMULATIONS

A. RF Results for Single Lines

In this section, we present a comparative RF analysis ofdifferent CPW TLines with a single Cu nanoline of varyingwidth as the signal track. The aim of this comparison is toexamine if there is a slow-wave effect related to the lateralsize of the nanoline. At first, we present the attenuation andphase constant versus frequency of the investigated single trackCPW TLines for different linewidths (Fig. 4).

The results of the attenuation constant (a) and the phaseconstant (β) are presented in Fig. 5. It is clearly seen thatwhen the linewidth decreases below ∼300 nm, the values ofboth a and β increase. The increase of α is due to the increaseof the series resistance of the nanoline. To our opinion, theincrease of β with decreasing linewidth can be attributed tothe decrease of the wT /s ratio, where wT is the nanolinewidth and s is the distance between the signal track and theground plane. The decrease of this ratio leads to higher Zc ofthe CPW TLine [38] (Fig. 6).

This is expected within the RLC model, since the dominantpropagation mode (quasi-TEM) is based on the transverseelectric field between the signal and the two grounds.In particular, the decrease of the wT /s ratio leads to a slightdecrease of the line capacitance and a large increase inline inductance and resistance. According to themeasurements, the decrease in C is ∼50% for linewidthsfrom 1000 nm down to 50 nm, while the increase in L and Rfor the same linewidths is ∼700% and ∼800%, respectively.Thus, from (1) and (2), it is deduced that reduced wT /s leadsto increased β and Zc.

In order to isolate the effect of the linewidth on thepropagation parameters, we compare nanolines with thesame Zc, as this is presented in Section V-B.

Fig. 5. Measured and simulated values of the attenuation and phaseconstant (beta) of CPW TLines on porous Si as a function of the Cu nanolinewidth for a frequency of 40 GHz.

Fig. 6. Measured and simulated values (at 40 GHz) of the characteristicimpedance Zc of the CPW TLines as a function of the Cu nanoline width.

Fig. 7. Attenuation (left graph) and phase constant (right graph) versusfrequency of the CPW TLines, composed of nanolines with total Cu widthequal to 2 μm. We see that the curves of the lines 10 nm × 200 nm,4 nm × 500 nm, and 2 × 1000 nm overlap, while the line with20 nm × 100 nm has higher a and β.

B. RF Results for Multiple CPW TLines With Constant Zc

The aim of this comparison was to examine the effect ofthe nanolines width on the CPW TLine performance, whenkeeping wT constant. The sum of the widths of the parallelCu nanolines (wCu) was also kept constant at 1 and 2 μm. Thecombinations that we compared were the following (numberof nanolines × linewidth): 1) 2 μm × 1 μm, 4 μm × 0.5 μm,10 μm × 0.2 μm, 20 μm × 0.1 μm for lines with wCu = 2 μmand 2) 1 μm × 1 μm, 2 μm × 0.5 μm, 5 μm × 0.2 μm,10 μm × 0.1 μm for lines with wCu = 1 μm. It has to

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SARAFIS et al.: Cu NANOLINES FOR RF INTERCONNECTS 5

Fig. 8. Measured and simulated attenuation and phase constant as afunction of the number of parallel nanolines (bottom axis) and the nanolinewidth (top axis). All values refer to 40 GHz. (a) wCu = 1 μm.(b) wCu = 2 μm. For comparison reasons, the scale is kept the same asin Fig. 5.

be pointed out that in the investigated lines, the wT /s ratiowas constant, resulting in almost constant Zc for each set oflines, i.e., 160 and 120 � at 40 GHz for wCu = 1 μm andwCu = 2 μm, respectively.

The attenuation and the phase constant versus frequency ofthe investigated multiple nanolines (only with wCu = 2 μm)are presented in Fig. 7. Focusing on the values thatcorrespond to 40 GHz, the attenuation and the phase constantof the above lines versus the number of the lines and thelinewidth are shown in Fig. 8. In this case, the phase constantincreases only slightly (∼20%) with decreasing linewidth,compared with the results of the single lines (Fig. 5). Thisproves that for the linewidths under investigation, the criticalparameter was wT /s and not the nanoline width.

The small increase in the attenuation constant with decreas-ing linewidth can be attributed to the higher resistivity of thenarrower lines, which is at the origin of the increase of theseries resistance (R) of the line. Indeed, in Fig. 9, we can seethat the R of the narrower parallel nanolines is slightly higherthan that of the wider ones. The increase in R between thelinewidths 1 μm and 100 nm is from 0.31 to 0.34 k�/mm inthe case of wCu = 1 μm. In the case of the wCu = 2 μm,R increases from 0.168 to 0.184 k�/mm. In both cases, theincrease is ∼10%, exactly equal to the percent increase ofresistivity between 1 μm and 100 nm (2.67 and 2.92 μ�·cm,respectively).

Fig. 9. Measured (extracted from the RLC model) and simulated (HFSS)p.u.l. resistance as a function of the number of lines (bottom axis) andlinewidth (top axis) of nanolines in multiline configuration. wCu is keptconstant at 1 and 2 μm. The values correspond to 40 GHz.

VI. DISCUSSION

The idea of splitting a single wire into several wires ofsmaller cross section is widely applied in high-frequencymacroscopic wires, e.g., the litz wires in order to increasethe active conduction area and reduce ohmic losses. It is thusinteresting to examine the implementation of the same ideain the case of CPW TLines with nanoscale signal tracks.In this case, the total effect is a combination of two differentphenomena: 1) the skin effect and 2) the proximity effect.

The skin effect is due to eddy currents inside the conductorand is described by the skin depth, which is the distance fromthe surface where the current density drops to 1/e of its valuenear the surface. The skin depth is calculated from

δ = √2ρ/(ωμrμ0) (3)

where μr is the relative permeability of Cu and μ0 isthe vacuum permeability. At 40 GHz, the skin depth (δ)is ∼406 nm for the resistivity of the 1-μm wide nanoline(ρ = 2.6 μ�·cm). If we consider the skin depth from eachside of the Cu nanoline, we see that 2δ = 812 nm, whichis smaller than the 1-μm wide line. When 2δ is smallerthan the linewidth, the current density cannot be considereduniform throughout the cross section of the conductor and theactive conduction cross section is reduced. On the other hand,the proximity effect, in the case of a CPW TLine, appearsbetween the signal track and the ground plane. As the currentflows in opposite directions in the above two conductors,it results in current crowding in the closer edges of theseconductors. These two effects act additively, resulting in anincrease in R [39].

The analogy to the litz wire with the parallel nanolineswould imply that when we split the signal track into sev-eral parallel nanolines of the same total linewidth, the cur-rent crowding effect is inhibited and the conducting area isincreased. However, as we can see in Fig. 9, in narrowerlinewidths, the increase of the value of R is simply deduced byjust considering the increase in resistivity due to the smallerlinewidth, without presenting a reduction of R with increasingnumber of parallel lines. This result shows that in the con-sidered frequency range, the litz-wire concept, applied to

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6 IEEE TRANSACTIONS ON ELECTRON DEVICES

CPW TLines with signal track composed of parallel nanolines,is not beneficial, compared with the case of a single line.Further investigations using HFSS simulations are on-going.

VII. CONCLUSION

In this paper, the RF properties of Cu nanolines inCPW TLine configuration were presented and the possibleperformance improvement of the application of the litz-wireconcept was assessed. The width of each discrete nanoline wasbetween 50 nm and 1 μm. Two categories of CPW TLineswere studied; CPW TLines with a single nanoline signal trackand CPW TLines with a signal track of constant wT and wCu,consisting of a varying number of multiple parallel nanolines.The following results were obtained.

In the case of single nanolines, narrower lines show higherattenuation constant and higher phase constant, this last beingattributed to the change of the signal-to-spacing ratio betweenthe signal line and ground plane. We thus claim that thereis no slow-wave effect due to the narrowing of the nanolinewidth. The measurements were in very good agreement withsimulation results, for lines down to 100 nm.

In the case of multiple parallel nanolines for the signaltrack with constant wT and wCu, we elucidated the originof the increased phase constant for narrower linewidths.The total resistance p.u.l. in this case increases by decreas-ing their linewidth, following the increase of Cu resis-tivity due to the nanometer size of the lines. The latterproves that splitting the signal track of a CPW TLineinto smaller lines does not improve the performance of thetransmission line.

Conclusively, for frequencies up to 40 GHz the applicationof the litz-wire concept for the specific nanolines studieddoes not yield any improvement in the performance of theCPW TLine. As no obvious reduction of R is observed, thereis no reason for splitting the signal track of the CPW TLinein multiple lines for the specific frequencies and dimensionsstudied in this paper.

ACKNOWLEDGMENT

The authors would like to thank A. Olziersky fromthe National Centre of Scientific Research Demokritos forperforming the e-beam lithography for Cu patterning.

REFERENCES

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[2] Y. Hanaoka, K. Hinode, K. Takeda, and D. Kodama, “Increase inelectrical resistivity of copper and aluminum fine lines,” Mater. Trans.,vol. 43, no. 7, pp. 1621–1623, 2002.

[3] Interconnect, ITRS, Denver, CO, USA, 2011.[4] S. Rakheja and A. Naeemi, “Modeling interconnects for post-CMOS

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This article has been accepted for inclusion in a future issue of this journal. Content is final as presented, with the exception of pagination.

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Panagiotis Sarafis was born in 1985. He receivedthe Diploma degree in electrical and computer engi-neering from the National Technical University ofAthens (NTUA), Athens, Greece, in 2010. He iscurrently pursuing the Ph.D. degree with the Insti-tute of Nanoscience and Nanotechnology, NationalCenter for Scientific Research Demokritos, Athens,in collaboration with NTUA.

Chuan-Lu Hsu received the Ph.D. degree from the Institut NationalPolytechnique de Grenoble, Grenoble, France, in 2013.

Philippe Benech is currently with the Institut National Polytechnique deGrenoble, Grenoble, France, and the IMEP Laboratory, Minatec ResearchCenter, Grenoble.

Androula G. Nassiopoulou received theDiploma degree in physics from the Universityof Athens, Athens, Greece, the M.Sc. andPh.D. degrees from the University of Paris XI, Orsay,France, and the Habilitation (Doctorat d’Etat) degreefrom the University of Reims, Reims, France.

She is currently the Director of Research with theNational Centre for Scientific Research Demokritos,Athens.