Super Stretched Solder Interconnects for Wafer Level Packaging

R. Rajoo, E.H. Wong, S.S. Lim, W. Y. Hnin, S.K.W. Seah Institute of Microelectronics, 11 Science Park Road, Science Park II, Singapore 117685

Tel: (65) 67705420, Email: ranjan@ime.a-star.edu.sg

**A.A.O. Tay **National University of Singapore, Department of Mechanical & Production Engineering

10 Kent Ridge Crescent, Singapore 119260

***Mahadevan Iyer, ***Rao R. Tummala ***Packaging Research Centre, Georgia Institute of Technology

813 Ferst Dr, Atlanta, GA 30332-560, USA

Abstract A cost-effective wafer level packaging technique termed

“stretch and break”, based on stretching and detachment of solder interconnections, has been established. Excellent co-planarity, essential for wafer level test and burn-in, is inherent in the process. The technique allows the freedom to use solder materials of up to 4000C melting temperature for forming the interconnection. The shape of the interconnection can also be easily manipulated for optimum performance. The mechanical and thermal cycling reliabilities of the stretched solder interconnection has been found to be significantly better than those of conventional solder joints.

1. Introduction In the drive towards low cost packaging technology,

Wafer Level Packaging (WLP) has emerged as a promising solution. WLP is an advanced packaging technology in which the die and package interconnections are fabricated and tested at the wafer level before singulation. By performing packaging, testing and burn-in at the wafer level, the processing costs can be brought down significantly. Subsequently, the wafer is singulated and the resulting dies are mounted onto printed circuit boards (PCBs).

One of the key concerns for any WLP interconnection scheme is the co-planarity of the interconnections on the wafer. Poor joint co-planarity hinders the process of wafer level burn-in and test. Another concern is the reliability of the interconnection, which should be enhanced or at the very least maintained at current accepted levels. The scheme should also be cost effective since cost is the major driving force behind WLP.

To date, no satisfactory WLP interconnection scheme has been developed which can adequately address all these issues simultaneously. The Stacked Solder [1-3] technique has the disadvantage of low process efficiency due to the sequential stacking process. Similarly, the Copper Post [4-6] Technique has a high process cost due to the lengthy and expensive electroplating process. The Copper Post technique also has problems with co-planarity. The Stress Buffer [7-9] technique has both an expensive lithography process as well as limited thermal cycling reliability.

As highlighted in the recent ITRS 2005 roadmap, WLP development is gradually moving from low I/O, small die applications to larger die, finer pitch and higher functionality

applications. Consequently, the reliability of the interconnections in WLP will become more critical.

This paper presents a cost effective technique for the fabrication of “super stretched” solder joints suitable for wafer level packaging. The reliability of the joints are enhanced through two mechanisms. Firstly, the super stretched solder joints have a standoff height several times higher than the conventional flip chip bumps [11-15]. Secondly, hourglass shape of the interconnections adds to the compliance and is capable of alleviating the stress concentrations on the solder joint, leading to further improvement in reliability [16-21]. The resultant array of interconnections has a high compliance that can potentially eliminate the need for underfill at first level packaging as well as remove the process dependency on moisture sensitivity, temperature humidity, and autoclave reliability factors.

Results from mechanical and thermal fatigue tests are shown to demonstrate the improved reliability of the super stretched solder joint as compared to the conventional flip chip solder bump. Scanning electron microscopy (SEM) and energy dispersive X-ray (EDX) analyses are used to examine the integrity of the joint and to detect cracks and other defects during the fatigue tests. Good joint co-planarity is also demonstrated using this new technique.

2. Stretchability and Shape Prediction The solder interconnections are described by two non-

dimensional parameters, the aspect ratio and the shape factor. Aspect ratio (AR) is defined as the ratio of the height of the solder joint to its pad diameter. The shape factor (SF) is defined as the ratio of the midpoint diameter to the pad diameter. The shape factor essentially describes the profile of the solder joint. For example, a value of 1.0 corresponds to a columnar joint. A shape factor greater than 1.0 describes a spherical or barrel shape. A shape factor less than 1.0 describes an hourglass shaped joint. Furthermore, the magnitude indicates the degree of curvature of the joint profile.

As stated above, the ability of the solder joint to withstand large numbers of continuous thermal and mechanical cycling without fatigue failure improves with greater standoff height and therefore aspect ratio. The stretching process proposed in the current interconnection scheme is able to easily achieve a aspect ratio of 4.5, for stretching of solder bumps having

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initial bump height of 95 µm on a pad diameter of 100 µm. Some images of the stretched solder joints are shown in Figure 1. Excellent co-planarity can also be observed from the images.

Figure 1: Images for Stretched Solder Interconnections

Aspect ratio Simulated profile Actual profile

3.0

3.5

Figure 2: Comparison between Actual Profile and Simulated Profile

The exact shape of the solder joint is dependent on its pad

diameter, volume, density, height and surface energy. Surface Evolver [22] been used to study the shape of molten solder under the influence of surface tension and gravity. This modelling work allows specific variables to be determined for achieving desired joint profiles before embarking on the fabrication process, thus helping to reduce both time and cost. The simulated profile obtained from modelling is comparable to the actual profile as shown in Figure 2.

3. Wafer Level Super Stretch Solder Fabrication Process This WLP interconnection scheme requires the use of two

types of wafers. The first type is termed the “functional wafer” and the second is the “dummy wafer”.

The functional wafer is a standard VLSI wafer containing the integrated circuits that will eventually be attached to the printed circuit board (PCB). The dummy wafer is a blank wafer without any standard under-bump metallization or passivation layer. However, it has a unique weak metallization layer deposited on the surface that is specially designed for this scheme. The purpose of the weak metallization layer will be explained below.

The fabrication process of this scheme is illustrated in Fig. 3 and can be divided into three distinct steps: 1) preparation of bumped wafers; 2) merging and stretching of solder bumps; and 3) detachment of stretched solder joints from the dummy wafer. In the first step, functional and dummy wafers are bumped using the standard process that involves either solder paste stencil printing, solder ball placement or electroplating followed by reflow. The use of solder balls is generally preferred due to better volume control. The solder bump array on the dummy wafer should be a mirror image of that on the functional wafer so that when the one wafer is aligned on top of the other, the vertical axes of corresponding solder bumps should coincide.

Subsequently, one of the wafers is positioned a shorter distance above the other and aligned with reference to the locations of the solder bumps (Fig. 3). Both arrays of solder bumps are melted simultaneously and the separation between the wafers is gradually reduced until each corresponding top-bottom pair of molten solder bumps merge to form a single larger solder bump. Thus, the resulting solder bump is bonded to both the functional and dummy wafers. Next, the wafers are slowly pulled apart resulting in the transformation of the solder joint shape from spherical to barrel to cylindrical and finally to hourglass as stretching progresses. During the process of stretching, the molten solder is progressively solidified through precise temperature control which facilitates the formation of solder joints with large height to pad diameter aspect ratios. The stretching is terminated when the desired profile of the solder joint is achieved. The solder joints are then allowed to solidify completely while maintaining the separation distance between the wafers in order to avoid the collapse of the joints. The resultant product after this process is an array of stretched solder joints sandwiched between a functional and a dummy wafer. Once the stretched solder joints have fully solidified, they are detached from the dummy wafer by mechanical breaking. The wafers are displaced slightly and the stretched solder joints break away at the weak metallization interface. The detachment of the solder joints from the dummy wafer is possible due to the presence of a weak metallization layer between the solder joint and dummy wafer. This weak metallization is specifically designed so that it is strong enough to adhere to the molten solder during the process of stretching but weak enough to detach from the solidified solder joint once an appropriate amount of force is applied to the assembly. As a result, one detached end of the solder joint is exposed and can be readily attached for burn-in and test process. Subsequently, the functional wafer packages together with interconnections are ready to be diced and attached individually to PCBs.

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Figure 3: Fabrication Processes for WLP Interconnection

Scheme

It is necessary to point out that solder bumping on the dummy wafer is optional. In the case where bumping is not present on the dummy wafer, the solder bump array on the functional wafer should be aligned and bonded to the corresponding weak metallization pads on the dummy wafer during the stretching process.

The new WLP interconnection scheme developed offers several attractive features. It is cost-effective due to its low material cost and short process time and has excellent solder joint co-planarity that is crucial for wafer level burn-in and test processes. Furthermore, it offers better reliability in terms of greater standoff height and more compliant hourglass shapes and can potentially eliminate the use of underfill, leading to further cost reduction. Finally, this scheme also offers design flexibility in terms of shape control and height control during the fabrication process to achieve the desired profile of the solder joint.

4. Reliability Test Procedures Mechanical fatigue and thermal cycling tests were

performed to assess the reliability of the stretched solder joints. The test setups are described below.

4.1 Micro-fatigue Test A unique setup with sub-micron displacement control has

been developed to assess the mechanical fatigue life of the stretched solder joints [23].

Figure 4: Micro-fatigue Test Setup

This setup is based on a universal microtester with a custom designed shear fatigue loading head that integrates a load cell and a precision displacement sensor (Figure 4). The tests are conducted under displacement control and maintains a constant strain amplitude range. During the tests, load-displacement data are recorded after every 50 cycles. In addition, the microtester was also used to measure the static shear strength of the solder joints. Samples used in the fatigue and static shear tests are chip-to-chip stretch solder samples with dimensions of 5mm by 5 mm.

Wafer (Functional)

Wafer (Dummy)

Heating elements

Base holder

Top holder

Solder merging

Controlled movement downwards

Controlled movement upwards

Solder stretching

Mechanical Detachment Process

Separation

Solidified solder column

Wafer (Functional)

Probe card

Substrate / Board

Chip

Displacement sensor

reference micrometer

Precision x-y base for

specimen setup

Built-in load cell

Displacement sensor in device

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4.2 Thermal Cycling Test For the thermal cycling tests, the test samples were built

using chip-to-board stretching. The thermal cycling test conditions used follow the JEDEC standard thermal cycling test condition G and soak mode 4. Other details of the chip and test board used for testing is provided in Table 1.

Table 1: Chip and Test Board Details Chip Test Board

Size 20mm by 20mm 40mm by 50mm Pitch 600µm Pad

diameter 300µm 300µm SMD

I/Os 1024 (Full array) Thickness 0.675mm 0.8mm Finishing UBM: TiNiCuAu ENIG

CTE 2.5 ppm0C 15 ppm0C

Material Solder alloy: Sn95.5/Ag3.8/Cu0.7

Board Grade: E679FGB

Solder Mask: AUS308

5. Reliability Assessment and Failure Analysis

5.1 Mechanical Fatigue Results The results from the mechanical fatigue tests for stretched

solder joints of various aspect ratios are tabulated in Table 2. It should be noted that the aspect ratio of 0.9 corresponds to the control case of a conventional solder bump without stretching. For all other stretched cases, double solder bump volume is used. For this series of tests, the fatigue life is defined as the number of cycles required for the shear load to reach 4N while maintaining a constant displacement amplitude. SEM images of the solder joint cross-sections are included in Table 2 to illustrate the variations of the shapes for different aspect ratios with identical solder volume. As aspect ratio increases, the shape of the solder joint changes progressively from ball to barrel to column and subsequently, to hourglass.

The results obtained from the mechanical fatigue tests demonstrate significant improvement in the number of fatigue life cycles of stretched solder joint with increasing aspect ratio. For a stretched solder joint with aspect ratio of 3.9, the fatigue life is enhanced by about 14 times compared to the control case. The improvement in the fatigue life is attributed to the higher standoff height and more compliant hourglass shape. From Table 2, it is observed that the static shear strength is inversely related to the fatigue life of the solder joints for the range of aspect ratios investigated, also because of the different compliances.

The fatigue failure locations for each aspect ratio are also indicated in Table 2. There is an apparent shift in the failure locations from the chip-solder interface to the midpoint of the solder joint with increasing aspect ratio. For the control case, failure occurs at the chip-solder interface. For stretched solder joints of relatively low aspect ratio, the failure site shifts to the under-bump metallization (UBM) of the chip-solder interface. At the aspect ratio of 3.9, majority of the solder joint failures occurred at the bulk solder at or near the midpoint of the joints. SEM fractographs of the failed surfaces are shown in Fig. 5.

Figure 5: Fatigue Failure Location for Stretched Solder Interconnections at (a) Solder end (b) UBM and (c)

Midpoint

Table 2: Micro-fatigue Characterization Test Results for Constant Solder Volume

Aspect ratio 0.9 (Control) 1.8 2.2 2.8 3.9

Solder joint shape

Fatigue life

(No. of cycles) 600 1 800 2 700 3 600 8 600

Static shear strength (N)

35 23 17 12 8

Failure location Solder end UBM UBM UBM Midpoint

Solder end

UBMMidpoint

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The results show that an increased aspect ratio improves the reliability of the joint through an increase in joint compliance. For higher aspect ratios, there is a shift of the failure location from the stress concentration at the pad interface to bulk solder at the joint mid-point. Therefore, at these higher aspect ratios, failure is governed by fatigue at the mid-point.

In order to study the fatigue reliabilities of different solder joint shapes, micro-fatigue tests are conducted for solder joints with different shape factors. The aspect ratio is kept constant but the solder volumes are allowed to vary. The results are summarized in Table 3 below. For this series of tests, the fatigue life is defined as the number of cycles required to cause a 5% reduction in the shear load while maintaining constant displacement amplitude.

By controlling the solder volume used in the fabrication process, different solder joint shapes can be achieved for the same aspect ratio as shown by the images attached in Table 3.

Results from tests carried out using a conventional solder bump are also presented as a control case for comparison with the other shapes. The fatigue life data indicates that the solder joints endure larger numbers of mechanical cycling with decreasing shape factor. A smaller shape factor indicates the narrowing of the neck diameter as the shape approaches that of an hourglass. A shape factor of 0.6 can easily achieve almost 200 times improvement in fatigue cycles compared to the control.

The failure location is also observed to shift away from the chip-solder interface to the midpoint of the solder joint as the shape factor approaches 0.5. This proves that the hourglass shape is capable of alleviating the stress concentration at the interface, thus allowing the joint to withstand larger number of fatigue cycles before fracture. The results therefore show that solder joints having hourglass shapes are more reliable compared to column, barrel and ball shapes. This conclusion has been verified using numerical simulations [24] and is in accordance with the findings presented in other studies [16-21].

Table 3: Micro-fatigue Characterization Test Results for Constant Aspect Ratio

Shape factor 1.3 (Control) 1.0 0.6

Solder joint shape

Fatigue life

(No. of cycles) 100 500 20 000

Failure location Solder end UBM Midpoint

5.2 Thermal Cycling Results The results from the thermal cycling tests for stretched

solder joints with aspect ratio of 3 are tabulated in Table 4. The reliability data is compared to that of a conventional spherical solder bump. For the joints being compared, identical solder volume is used. The fatigue life of the joint is considered as the number of cycles the package can withstand before the daisy chain resistance exceeds 300 ohms.

From Table 4, it can be seen that the thermal cycling reliability is notably different for each type of solder joint. The stretched solder joint has a fatigue life which is 4.25 times better than that of a conventional solder bump. SEM images of the joint cross-sections are shown in Table 4, the failure locations for the solder bump and stretched solder joint are at the chip-solder interface and the joint midpoint respectively. This is similar to the results obtained from the micro-fatigue tests. Further testing is being conducted on a wider range of aspect ratios and shape factors in order to understand their influence on the reliability of the stretched solder joints.

Table 4: Thermal Cycling Test Results for Constant Solder Volume

Aspect ratio 0.9 (Control) 3.0

Max Fatigue

life 400 1700

Failure location Solder end Midpoint

Failure location images

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6. Conclusions A new wafer level packaging scheme has been developed

for compliant interconnections. This scheme offers much better thermal cycling and fatigue reliability and excellent joint co-planarity which is critical for the burn-in and test process. It is also more cost-effective than other interconnection schemes. Chip-to-board stretching of solder joints has been successfully demonstrated and mechanical and thermal cycling reliability test results clearly show the superiority of the stretched solder joints over conventional solder bumps.

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