timespot - cern indico

TIMESPOTResults on sensors and electronics developments for future vertex detectors

Adriano Laifor the TIMESPOT teamINFN Sezione di Cagliari – Italy

HSTD12, Hiroshima 14-18 December 2019

3D silicon sensorsproviding time

resolutions below30 ps rms and

relatedelectronics

3D !

LGAD !

TamedTiming (???)

HSTD12, Hiroshima – December 2019 TIMESPOT – Adriano Lai 3

Structure, organization and objectives ofMain target:Develop and realize a demonstrator consisting of a complete yet simplified reduced size tracking system, integrating order 1000 read-out pixel channels, satisfying the following characteristics:

• Pixel pitch: ≤ 55 µm• Radiation hardness: 1016 – 1017 1 MeV neq/ cm2 (sensors) and > 1 Grad (electronics)• Time resolution: ≤ 50 ps per pixel (target = 30 ps or better )• Real time track reconstruction algorithms and fast read-out (data throughput > 1 TB/s)

Activities are organized in 6 work packages:

1. 3D silicon sensors: development and characterization2. 3D diamond sensors: development and characterization3. Design and test of pixel front-end with timing measurement4. Design and implementation of real-time tracking algorithms5. Design and implementation of high-speed readout boards6. System integration and tests

3 years work program + 1 year possible extension (2018-2021)


Places & people:Sezioni: Bologna CagliariGenova Ferrara FirenzeMilanoPadovaPerugiaTorinoTIFPA (Trento)

≈ 60-70 heads, ≈ 20-25 FTE. People from LHCb, ATLAS, CMS + others


3D Trench geometry and Pixel characteristicsThe starting (break-through) point

5

55 µm

150 µm

135 µm

55 µm

• Total charge deposit for MIP ≈ 2 fC• Full depletion @ few Volts, Velocity saturation @ > 30 V• Pixel capacitance (from simulation) ~140 fF

Biasing el. (p+)Collecting el. (n+)

Elec

tric

field

map

Column geometry (e.g. ATLAS IBL) Trench geometry(TIMESPOT)

HR Si (~ 5kΩ cm)(sensitive volume)

LR Si (<Ω cm)

Single-Side production

method


dE/dx deposit(3 pixel volume)

400 psMax

charge collection time

https://github.com/MultithreadCorner/Tcode

Full sensor model and signalsSimulated sensor performance in terms of timing


1st 3D-trench batchDelivered 15 June 2019

Timepix area: 256x256 pixels x 55 µm pitch

See talk #337 S5 by Giulio Forcolin


88

(A) Pixel-strip (10 pixels connected on the same read-out pad); (B) Single and double pixel; (C) Hexagonal (column) pixel device, based on FBK 3D Double Side Technology.

Devices are connected to electronics by wire bonding (Al, 25 µm diameter, ~ 5 mm length)

3D structures under testIn lab & under-beam measurements

For “static“ tests (IV, Vbd, Capacitance) please refer to talk #337 S5 by Giulio Forcolin …


System under test

Tests beam @

p+ Beam

DAQ Power Supplies

pM1


DUT signal (trigger)Exposed Area of DUTs

<< 1 mm2

Each DUT has a different DAQ chain(8 GHz and 4 GHz BW scopes)

Beam RF signal (50 MHz)

2 MCP signals (trigger) (time references st O(10ps))

Exposed area ≈ 5x5 cm2

Tests beam @ PSI pM1Experimental conditions

Cherenkov Time Taggers (MCP)

DUT1 DUT2

Beam E = 270 MeV/c. Beam radius on the spot s ~ 1.5 cm

Original beam: p, e+, µ+, p+ Selectable by TOFUsing a plexiglas degrader and small slitapertures we obtained an almost pure p+

beam (negligible e+ contamination)


Tests beam @ PSI pM1System inside the black box

beam


Noise (gauss) + Signal (Landau) + error (step) function fit

MIP MPV ~ 21 mV

3D Pixel @ -80V

The Max/FWHM ratio iscompatible with a Landau

distribution of a 150 µm thicksilicon

Time resolution per bins of amplitude(Genova F/E)

MIP MPV (21 mV)

Time resolution (1)of TIMESPOT 3D trench pixels


Time resolution (2)of TIMESPOT 3D trench pixels

Trench 3D with «KU» front-end

Leading Edge(Vthr = 10 V)

No ToTcorrection !

st = 46.5 ps

Time resolution becomes 28.9 psafter deconvolving time-tagger jitter

st = 30.7 ps

Trench 3D with

«Genova» front-end

CFD

Tails are the combination of 3 main effects:• Spurious signals (algorithm and in-time EMI noise)• Partial charge deposit (neighbour un-read pixels)• Weak field spots (small contribution)


st vs electronics F/Eof DUT on PSI beam

Test structure Front-end type st

Pixel strip KU* modified prod. 1 – unshielded 40 – 50 ps

Single pixel KU modified prod. 1 – unshielded 35 ps

Hexagonal column(FBK DS process)

KU modified prod. 1 – unshielded ~ 60 ps (preliminary)

Double pixel GE** board SiGe BJT + BB amp – shielded < 30 ps

Single pixel GE board SiGe BJT + GALI – shielded Bad (Oscillations)

ATLAS Phase2 50x50 with poly connection

KU modified prod. 1 – unshielded High values (>100 ps) (preliminary)

Diamond 110 KU modified prod. 2 ~ 320 ps . Worse S/N ratio

Diamond 55 KU modified prod. 2 ~ 230 ps. Worse S/N ratio

• For practical reasons only collective and wire-bonded pixel structures have been tested (x10 increase in Capacitance).

• Comparing different read-out boards is easy to argue that the measurements are limited by front-end performance and extrinsic (EMI) noise. A better/dedicated electronics is needed.

• Final answer will be given using an integrated front-end

*Kansas University


Measurementsin the lab

(more «silent» setup)


Laser setup@INFN Cagliari

• 1030 nm, 100 fs, 40 MHz pulsed laser• Pulse-picker to select pulses from 40 MHz

to single pulse• Monomode fiber to microscope• 5x and 20x optics• Optical filters for light intensity

attenuation• Pin-hole for collimation• Microscope with IR camera

5 µm diameter laser spot on sensor

5x optics cangive a cilinder

inside thesensor volume

(MIP-like deposit)

Abs coeff@1030 nm ≈

30/cmI/I0 ≈ 75% after

100 µm)


0

20

40

60

80

100

120

0.00 0.50 1.00 1.50 2.00 2.5017

st = 20 ps

Std

dev

Tim

e re

solu

tion

(ps)

Charge (fractions of MPV of MIP deposit, MPV ≈ 2 fC), Vbias = – 60 V @ room temperature

• KU Front-end• Digital CFD (on scope)• 10 pixel strip + wire bond

connection (Ctot ≈ 1.5 pF)• Charge deposit estimate

by separate calibrated CSA

Time response vs Charge

st = smeas / sqrt(2)

Dt


Cable loss evaluation and recovery

Impact of cable characteristics on measuredsensor timing performance

(in addition to better EMI setup)


1st prototype in 28-nm CMOSa 1st approach to this technology

• 3 different TDC solutions• 6-bit DAC + SPI I/F• 8-channels CSA+LE

Discriminator • Programmable power

(and speed)• General purpose OPAMP• LVDS Tx/Rx

Integrated cells:

Total area 1.5x1.5 mm2

(mini@sic)

Encapsulated chip prototype. 75 µm bonding pitchBonded at Milano workshop

Ø Main purpose: gain confidence on 28-nm CMOS and test technology withoutpushing in complexity and performance.

Ø All cells are kept independent and directly accessible from external pins(with a few exceptions)

à strongly pad-limited


DCO (dithering)

Tappeddelay

Time Amplifier

Simulated (rms is theoretical*)

TDCSimulation and tests (still preliminary)

Post-layout simulation

characteristics

TDC scheme à

MeasuredTAP TDC config

*calculated as flat channel bin profile: LSB/(12)1/2


DCO (dithering)

Tappeddelay

Time Amplifier

Simulated (rms is theoretical)

TDCSimulation and tests (still preliminary)

Post-layout simulation

characteristics

TDC scheme à

MeasuredTAP TDC config

• ≈ 20% degradation of performance in LSB resolutions

• Higher degradation in rms (but dominated by LVDS driver and readout time jitter –still under study)

à sTDC estimatedbetween 35 and 50 ps

?


Measured performance is x2 worse than expected due to x2 lower gain. Reasons still under investigations (amplifier biasing?)

CSA + DiscriminatorExpected/measured performance

«High» power (7.2 µA)«Low» power (4.1 µA)

Expected performance (from simulations)


Design of 2nd versionTo be submitted Spring 2020

Present, low power

Present, high power

Next version

We are working on the next version of the ASIC:

ü 24x48 55x55 µm2 pixels. Pixel contains: • CSA, LE discriminator, with increased power for

better time resolution (limit is 18 ps @ 22 µW)• New type* TDC (shared among 2 or 4 channels) • TOT real-time correction

ü Other amplifier and TDC test structures (out of the pixelmatrix)

ü Rad-hardening design techniques appliedü Impedance adaptation for diamond sensorü N x1.5Gbps LVDS output links (already designed and

working in 1st version)ü ASIC will be wire-bondable, but TSV ready, with a

Redistribution Layer

*Interpolated–tapped scheme.~ 40 ps LSB, 12 ps rms (theoretical). Size: 22x15 µm2

*Vernier scheme. Conversion time 17 ns~ 30 ps LSB, 8 ps rms (theoretical)

Power vs jitter within our present CSA scheme

• 3D Silicon sensors based on trench geometryhave been produced and characterized

• They show intrinsic time resolution ranging between 20 and 30 ps rms

• Front-end electronics is at the moment thelimiting stage to performance. This is evenmore important when pixel front-end isconsidered, where space and power constraintsenter the game

• A first prototype of pixel electronics has beentested giving best resolutions of 80 ps LSB with40 ps rms (estimated) for TDC and 60 ps rms(estimated) for amplifier (at reduced power consumption of 7µW/channel)

• A second batch of 3D sensor is under design and will be submitted early 2020

• A second prototype of pixel front-end ASIC withmatrix read-out will be submitted is plannedfor Spring 2020

TIMESPOTSummary

HSTD12, Hiroshima 14-18 December 2019

timespot - cern indico

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