switched capacitor circuits -...

Switched Capacitor Circuits (10/11/00)

ECE4430 Analog Integrated Circuit Design

SWITCHED CAPACITOR CIRCUITS INTRODUCTION

Objective

The objective of these notes is to provide an elementary background about switched capacitorcircuits.

Outline

• Introduction

• Resistance emulation

• Switches

• Amplifiers

• Integrators

• First-order circuits

• Summary



RESISTORS RESISTOR EMULATION

Switched Capacitors are Not New

James Clerk Maxwell used switches and a capacitor to measure the equivalent resistance of agalvanometer in the 1860’s.

Parallel Switched Capacitor Equivalent Resistor:

i (t) i (t)2

v (t)1 v (t)2

1 R

(b.)

Figure 9.1-1 (a.) Parallel switched capacitor equivalent resistor.(b.) Continuous time resistor of value R.

(a.)

i (t) i (t)2

Cv (t)1 v (t)2

1 1 2

v (t)C

Two-Phase, Nonoverlapping Clock:

t

t

1

0

1

00 T/2 T 3T/2 2T

2

1

Figure 9.1-2 - Waveforms of a typical two-phase, nonoverlapping clock scheme.



EQUIVALENT RESISTANCE OF A SWITCHED CAPACITOR CIRCUIT

Assume that v1(t) and v2(t) are changing slowly with respect to the clock period.The average current is,

i1(average) = 1T ⌡

⌠0

T

i1(t)dt = 1T ⌡⌠

0

T/2

i1(t)dt

Charge and current are related as,

i1(t) = dq1(t)

dtSubstituting this in the above gives,

i1(average) = 1T ⌡⌠

0

T/2

dq1(t) = q1(T/2)-q1(0)

T = CvC(T/2)-CvC(0)

T

However, vC(T/2) = v1(T/2) and vC(0) = v2(0). Therefore,

i1(average) = C [v1(T/2)-v2(0)]

T ≈ C [V1-V2]

T

For the continuous time circuit:

⇒ i1(average) = V1-V2

R ∴ R ≈ TC

For v1(t) ≈ V1 and v2(t) ≈ V2, the signal frequency must be much less than fc.

i (t) i (t)2

Cv (t)1 v (t)2

1 1 2

v (t)C

i (t) i (t)2

v (t)1 v (t)2

1 R



EXAMPLE 9.1 - DESIGN OF A PARALLEL SWITCHED CAPACITOR RESISTOR EMULATION

If the clock frequency of parallel switched capacitor equivalent resistor is 100kHz, find thevalue of the capacitor C that will emulate a 1MΩ resistor.

Solution

The period of a 100kHz clock waveform is 10µsec. Therefore, using the previousrelationship, we get that

C = TR =

10-5

106 = 10pF

We know from previous considerations that the area required for 10pF capacitor is much less thanfor a 1MΩ resistor when implemented in CMOS technology.



POWER DISSIPATION IN THE RESISTANCE EMULATION

If the switched capacitor circuit is an equivalent resistance, how is the power dissipated?

i (t) i (t)2

v (t)1 v (t)2

1 R

(b.)

Figure 9.1-1 (a.) Parallel switched capacitor equivalent resistor.(b.) Continuous time resistor of value R.

(a.)

i (t) i (t)2

Cv (t)1 v (t)2

1 1 2

v (t)C

Continuous Time Resistor:

Power = (V1 - V2)2

R

Discrete Time Resistor Emulation:

Assume the switches have an ON resistance of Ron. The power dissipated per clock cycle is,

Power = i1(aver.)(V1-V2) where i1 (aver.) = (V1 -V2)

RonT ⌡⌠0

T

e -t/(RonC)dt

∴ Power = (V1-V2)2

TRon ⌡⌠0

T

e -t/(RonC)dt = (V1-V2)2

(T/C) [ ]-e -T /(RonC ) + 1 ≈ (V1-V2)2

(T/C) if T >> RonC

Thus, if R = T/C, then the power dissipation is identical in the continuous time and discrete timerealizations.



OTHER SWITCHED CAPACITOR EQUIVALENT RESISTANCE CIRCUITS

Series

i (t)2

v (t)1 v (t)2

i (t)1 1 2

1S 2SC

v (t)C

Series-Parallel

i (t)2

Cv (t)1 v (t)2

i (t)1 1 2

1S 2S1

C2

v (t)C1 v (t)C2 1

1S i (t)2

v (t) v (t)2

i (t)1

1 2

2SC

121S 2S

Bilinear

v (t)C

Series-Parallel:The current, i1(t), that flows during both the φ1 and φ2 clocks is:

i1(average) = 1T ⌡

⌠0

T

i1(t)dt = 1T

⌡⌠0

T/2

i1(t)dt + ⌡⌠T/2

T

i1(t)dt = q1(T/2)-q1(0)

T + q1(T)-q1(T/2)

T

Therefore, i1(average) can be written as,

i1(average) = C2 [vC2(T/2)-vC2(0)]

T +C1 [vC1(T)-vC1(T/2)]

T

The sequence of switches cause,vC2(0) = V2, vC2(T/2) = V1, vC1(T/2) = 0, and vC1(T) = V1 - V2.Applying these results gives

i1(average) = C2[V1-V2]

T + C1[V1-V2- 0]

T = (C1+C2)(V1-V2)

T

Equating the average current to the continuous time circuit gives: R = T

C 1 + C 2



EXAMPLE 9.1-2 - DESIGN OF A SERIES-PARALLEL SWITCHED CAPACITOR RESISTOR EMULATION

If C1 = C2 = C, find the value of C that will emulate a 1MΩ resistor if the clock frequency is250kHz.

Solution

The period of the clock waveform is 4µsec. Using above relationship we find that C is givenas,

2C = TR =

4x10-6

106 = 4pF

Therefore, C1 = C2 = C = 2pF.



SUMMARY OF THE FOUR SWITCHED CAPACITOR RESISTANCE CIRCUITS

Switched Capacitor ResistorEmulation Circuit

Schematic Equivalent Resistance

Parallel Cv (t)1 v (t)2

1 2

TC

Series v (t)1 v (t)2

1 2

CTC

Series-Parallel

Cv (t)1 v (t)2

1 2

1 C2

TC1Ê+ÊC2

Bilinear

1v (t) v (t)2

1 2

C

2 1

T4C



ACCURACY OF SWITCHED CAPACITOR CIRCUITS

Consider the following continuous time, first-order, low pass circuit:

R1

C21v v2

The transfer function of this simple circuit is,

H(jω) = V2(jω)V1(jω) =

1jωR 1C 2 + 1 =

1jωτ1 + 1

where τ1 = R1C2 is the time constant of the circuit and determines the accuracy.

Continuous Time Accuracy

Let τ1 = τC. The accuracy of τC can be expressed as,dτC

τC =

dR1

R1 +

dC2

C2 ⇒ 5% to 20% depending on the size of the components

Discrete Time Accuracy

Let τ1 = τD =

T

C1 C2 =

1

fcC1 C2. The accuracy of τD can be expressed as,

dτD

τD =

dC2

C2 -

dC1

C1 -

dfc

fc ⇒ 0.1% to 1% depending on the size of components

The above is the primary reason for the success of switched capacitor circuits in CMOS technology.



SWITCHED CAPACITOR CIRCUITS - kT/C NOISE

Switched capacitors generate an inherent thermal noise given by kT/C. This noise is verified asfollows.

An equivalent circuit for a switched capacitor:

C voutvin

+

-

+

-

C voutvin

+

-

+

-

Ron

(a.) (b.)Figure 9.3-11 - (a.) Simple switched capacitor circuit. (b.) Approximation of (a.).

The noise voltage spectral density of Fig. 9.3-11b is given as

e2

Ron = 4kTRon Volts2/Hz =

2kTRon

π Volt2/Rad./sec. (1)

The rms noise voltage is found by integrating this spectral density from 0 to ∞ to give

v2

Ron =

2kTRon

π ⌡⌠

0

∞

ω12dω

ω12+ω2 =

2kTRon

π

πω1

2 = kTC Volts(rms)2 (2)

where ω1 = 1/(RonC). Note that the switch has an effective noise bandwidth of

fsw = 1

4RonC Hz (3)

which is found by dividing Eq. (2) by Eq. (1).



SWITCHES MOS TRANSISTOR AS A SWITCH Symbol

Bulk

A B

(S/D) (D/S)

C (G)

A B

Fig4.1-2

On Characteristics of a MOS Switch

Assume operation in active region (vDS < vGS - VT) and vDS small.

iD = µCoxW

L

(vGS - VT) - vD S

2 vDS ≈ µCoxW

L (vGS - VT)vDS

Thus, RON ≈ vD S

iD =

1µCoxW

L (vGS - VT)

OFF Characteristics of a MOS Switch

If vGS < VT, then iD = IOFF = 0 when vDS ≈ 0V.

If vDS > 0, then

R O N ≈ 1

iDλ = 1

IOFFλ ≈ ∞



MOS SWITCH VOLTAGE RANGES

If a MOS switch is used to connect two circuits that can have analog signal that vary from 0 to5V, what must be the value of the bulk and gate voltages for the switch to work properly?

Circuit1

Circuit2

(0 to 5V)

(S/D)

(0 to 5V)

(D/S)

Bulk

GateFig.4.1-3

• To insure that the bulk-source and bulk-drain pn junctions are reverse biased, the bulk voltagemust be less than the minimum analog signal for a NMOS switch.

• To insure that the switch is on, the gate voltage must be greater than the maximum analog signalplus the threshold for a NMOS switch.

Therefore:

VBulk ≤ 0V

and

VGate > 5V + VT

Also, VGate(off) ≤ 0V

Unfortunately, the large value of reverse bias bulk voltage causes the threshold voltage to increase.



CURRENT-VOLTAGE CHARACTERISTICS OF A NMOS SWITCH

The following simulated output characteristics correspond to triode operation of the MOSFET.100µA

60µA

20µA

-20µA

-60µA

-100µA-1V -0.6V -0.2V 0.2V 0.6V 1V

VGS=2V

VGS=3V

VGS=4V

VGS=5V

VGS=10V

VGS=9V

VGS=8VVGS=7V

VGS=6V

Fig. 4.1-3

SPICE Input File:MOS Switch On CharacteristicsM1 1 2 0 3 MNMOS W=3U L=3U.MODEL MNMOS NMOS VTO=0.75, KP=25U,+LAMBDA=0.01, GAMMA=0.8 PHI=0.6VDS 1 0 DC 0.0

VGS 2 0 DC 0.0VBS 3 0 DC -5.0.DC VDS -1 1 0.1 VGS 2 10 1.PRINT DC ID(M1).PROBE.END



MOS SWITCH ON RESISTANCE AS A FUNCTION OF GATE-SOURCE VOLTAGE 100kΩ

10kΩ

1kΩ

100Ω1.0V 1.5V 2.0V 2.5V 3.0V 3.5V 4.0V 4.5V 5.0V

W/L = 1

W/L = 5

W/L = 10

W/L = 50

MO

S Sw

itch

On

Res

ista

nce

Gate-Source Voltage Fig. 4.1-5

SPICE Input File:MOS Switch On Resistance as a f(W/L)M1 1 2 0 0 MNMOS W=3U L=3UM2 1 2 0 0 MNMOS W=15U L=3UM3 1 2 0 0 MNMOS W=30U L=3UM4 1 2 0 0 MNMOS W=150U L=3U.MODEL MNMOS NMOS VTO=0.75, KP=25U,

+LAMBDA=0.01, GAMMA=0.8, PHI=0.6VDS 1 0 DC 0.001VVGS 2 0 DC 0.0.DC VGS 1 5 0.1.PRINT DC ID(M1) ID(M2) ID(M3) ID(M4).PROBE.END



INFLUENCE OF THE ON RESISTANCE ON MOS SWITCHES

Finite ON Resistance:

vin=2.5VVGateC

vC(0) = 0-+

vin>0C

vC -+

RON

Fig. 4.1-6

Example

Initially assume the capacitor is uncharged. If VGate(ON) is 5V and is high for 0.1µs, find theW/L of the MOSFET switch that will charge a capacitance of 10pF in five time constants(KN’=110µA/V2 and VTN = 0.7V).

Solution

The time constant must be equal to 100ns

5 = 20ns. Therefore RON must be less than 20ns10pF = 2kΩ.

The on resistance of the MOSFET (for small vDS) is

RON = 1

KN’(W/L)(VGS-VT) ⇒ WL =

1RON·KN’(VGS-VT) =

1

2kΩ·110µA/V2·4.3 = 1.06

Comments:

• It is relatively easy to charge on-chip capacitors with minimum size switches.

• Switch resistance is really not constant during switching and the problem is more complex thanabove.



INCLUDING THE INFLUENCE OF THE VARYING ON RESISTANCE

Gate-source Constant

gON(t) = K’W

L (vGS(t)-VT) -vDS(t)

gON(aver.) = 1

rON(aver.) ≈

gON(0) + gON(∞)

2

= K’W2L (VGS-VT) -

K’WVDS(0)

2L + K’W2L (VGS-VT)

= K’W

L (VGS-VT) - K’WVDS(0)

2L

Gate-source Varying

VGS=5V

VGS=5V-vIN

VDS

ID t=0

t=∞

gON(0)

gON(∞)

Fig. 4.1-8vDS(0)vDS(∞)

VGate

C vC(0) = 0-

+

+

-vGS(t)

vIN

gON= K’W2L [VGS(0)-VT] -

K’WVDS(0)

2L + K’W2L [VGS(∞)-vIN-VT]

VGS=5V

VDS

ID t=0

t=∞

gON(0)

gON(∞)

Fig. 4.1-7vDS(0)vDS(∞)



SWITCH ON RESISTANCE EXAMPLE

Assume that at t = 0, the gate of the switch shown is taken to 5V. Design the W/L value of theswitch to discharge the C1 capacitor to within 1% of its initial charge in 10ns. Use the MOSFETparameters of Table 3.1-2.

+-+

5V-

0V

5V

C1 =10pF

C2 = 10pF

+ -0V

Fig.4.1-9

vout(t)

Solution

Note that the source of the NMOS is on the right and is always at ground potential so there isno bulk effect as long as the voltage across C1 is positive. The voltage across C1 can be expressed as

vC1(t) = 5exp

-t

RONC1

At 10ns, vC1 is 5/100 or 0.05V. Therefore,

0.05 = 5exp

-10-8

RON10-11 = 5exp

-103

RON ⇒ exp(GON103) = 100 ⇒ GON =

ln(100)

103 =

0.0046S

∴ 0.0046 = K’W

L (VGS-VT) - K’WVDS

2L =

110x10-6·4.3 - 110x10-6·5

2 WL = 198x10-6 W

L

Thus, WL =

0.0046

198x10-6 = 23.2 ≈ 23



INFLUENCE OF THE OFF STATE ON MOS SWITCHES

The OFF state influence is primarily in any current that flows from the terminals of the switch toground.

An example might be:

vin vout

CH

+

-RBulk+

-vCH

Fig. 4.1-10

Typically, no problems occur unless capacitance voltages are held for a long time. For example,

vout(t) = vCH[1 - e-t/(RBulkCH)]

If RBulk ≈ 109Ω and CH = 10pF, the time constant is 109·10-11 = 0.01seconds



INFLUENCE OF PARASITIC CAPACITANCES

The parasitic capacitors have two influences:

• Parasitics to ground at the switch terminals (CBD and CBS) add to the value of the desiredcapacitors.

This problem is solved by the use of stray-insensitive switched capacitor circuits

• Parasitics from gate to source and drain cause charge injection onto or off the desired capacitors.

This problem can be minimized but not eliminated.

Model for studying charge injection:

1

VS

+

-

CLvCL VS

+

-

CLvCL

Cchannel

CGS0 CGD0

Rchannel

VS

+

-

CLvCL

Cchannel

CGS0 CGD0

Rchannel

2

Cchannel

2

1 1

Fig. 4.1-11

A simple switch circuit usefulfor studying charge injection.

A distributed model ofthe transistor switch.

A lumped model ofthe transistor switch.



CHARGE INJECTION (CLOCK FEEDTHROUGH, CHARGE FEEDTHROUGH)

Charge injection is a complex analysis which is better suited for computer analysis. Here wewill attempt to develop an understanding sufficient to show ways of reducing the effect of chargeinjection.

What is Charge Injection?

1.) When the voltages change across the gate-drain and gate-source

capacitors, a current will flow because i = C dvdt .

2.) When the switch is off, charge injection will appear on the externalcapacitors (CL) connected to the switch terminals causing their voltagesto change.

There are two cases of charge injection depending upon the transition rate when the switch turns off.

1.) Slow transition time.

2.) Fast transition time.

Fig. 4.1-12



SLOW TRANSITION TIME

Consider the following switch circuit:

vin+VT

Switch ONA

B

C

CLvin

Fig. 4.1-13

vin+VTSwitch OFF

A

B

C

CLvin

Chargeinjection

1.) During the on-to-off transition time from A to B, the charge injection is absorbed by the lowimpedance source, vin.

2.) The switch turns off when the gate voltage is vin+VT (point B).

3.) From B to C the switch is off but the gate voltage is changing. As a result charge injectionoccurs to CL.



FAST TRANSITION TIME

For the fast transition time, the rate of transition is faster than the channel time constant so that someof the charge during the region from point A to point B is injected onto CL even though thetransistor switch has not yet turned off.

vin+VT

Switch ONA

B

C

CLvin

Fig. 4.1-14

vin+VTSwitch OFF

A

B

C

CLvin

Chargeinjection

Chargeinjection



APPROXIMATE ANALYSIS OF FEEDTHROUGH

The model for this case is given as:

Fig. 4.1-16

VS +VTSwitch OFF

A

B

C

CLvin ≈VS ≈VD

Chargeinjection

COLCOL

VS +VT

COL

CL

+

-

vCL

VL

VS

VT

VLCircuit at theinstant gate

reaches VS +VT

The switch decrease from B to C is modeled as a negative step of magnitude VS +VT - VL.The output voltage on the capacitor after opening the switch is,

vCL =

CL

COL+CLVS -

COL

COL+CLVT -(VS + VT -VL)

COL

COL+CL ≈ VS - (VS + 2VT -VL)

COL

CL

if COL < CL.

Therefore, the error voltage is

Verror ≈ -(VS + 2VT - VL)

COL

CL = -(vin + 2VT - VL)

COL

CL



SOLUTIONS TO CHARGE INJECTION

1.) Use minimum size switches to reduce the overlap capacitances and/or increaseCL.

2.) Use a dummy compensating transistor.

φ1 φ1

M1 MD

W1L1

WDLD

= W12L1

Fig. 4.1-19

• Requires complementary clocks

• Complete cancellation is difficult and may in fact may make the feedthrough worse

3.) Use complementary switches (transmission gates)

4.) Use differential implementation of switched capacitor circuits (probably the best solution)



INPUT-DEPENDENT CHARGE INJECTION

Examination of the error voltage reveals that,

Error voltage = Component independent of the input + Component dependent on the input

This only occurs for switches that are floating and is due to the fact that the input influences thevoltage at which the transistor switches (vin ≈ VS ≈ VD). Leads to spurious responses and otherundesired results.

Solution:

Use delayed clocks to remove the input-dependence by breaking the current path for injectionfrom the floating switches.

Ci

φ1

φ2φ1d

φ2

CsVin

LC

VoutS1S2 S3

S4

φ1

φ2

φ1d

Clock Delay

t

t

t

Fig. 4.1-20

Assume that Cs is charged to Vin (both φ1 and φ1d are high):1.) φ1 opens, no input-dependent feedthrough because switch terminals (S3) are at ground potential.2.) φ1d opens, no feedthrough occurs because there is no current path (except through smallparasitic capacitors).



CMOS SWITCHES (TRANSMISSION GATE)

VDD

Clock

Clock

A B

Fig. 4.1-21

BAClock

Clock

Advantages:

• Feedthrough somewhat diminished

• Larger dynamic range

• Lower ON resistance

Disadvantages:

• Requires a complementary clock

• Requires more area



DYNAMIC RANGE OF THE CMOS SWITCH

The dynamic range of a switch is the range of voltages at the switch terminals (VA ≈ VB = VA,B)over which the ON resistance stays reasonably small.

VDD

A B

VDD

M1

M21µAVA,B

Fig. 4.1-22

Spice File:Simulation of the resistance of a CMOStransmission switchM1 1 3 2 0 MNMOS L=2U W=50UM2 1 0 2 3 MPMOS L=2U W=50U.MODEL MNMOS NMOS VTO=0.75, KP=25U,LAMBDA=0.01, GAMMA=0.5, PHI=0.5.MODEL MPMOS PMOS VTO=-0.75, KP=10U,LAMBDA=0.01, GAMMA=0.5, PHI=0.5VDD 3 0VAB 1 0IA 2 0 DC 1U.DC VAB 0 5 0.02 VDD 4 5 0.5.PRINT DC V(1,2).END

Result:Low on resistance over a wide voltage range becomes very difficult as the power supply

decreases.

0kΩ

0.5kΩ

1kΩ

1.5kΩ

2kΩ

2.5kΩ

3kΩ

Switc

h O

n R

esis

tanc

e

0V 1V 2V 3V 4V 5V

VDD = 5V

VDD = 4.5V

VDD = 4V

A,B (Common mode voltage)V



CMOS SWITCH WITH TWIN-WELL SWITCHING

VDD

VSS

M1

M2

M3

M4 M5

AnalogSignalInput

Analog Signal Output

VControl

VControl

Circuit when VControl is in its high state. Circuit when VControl is in its low state.

M1

M2

High State

Low State


AnalogSignalInput

M1

M2

High State

Low State


AnalogSignalInput

VDD

VSS



CHARGE PUMPS FOR SWITCHES WITH LOW POWER SUPPLY VOLTAGES

As power supply voltages decrease below 3V, it becomes difficult to keep the switch on at alow value of on-resistance over the range of the power supply. Consequently, charge pumps areused.

Charge pump circuit:

0V

3.3V

C1 C2

VDD = 3.3V

Vsub_hi

CL

0V

0V

Vhi

To a single NMOS switch

M1

(Prevents latchup)

≈ 5V

Vhi = 2VDD·C2

Cgate,NMOS switch + C2 + CL



CHARGE PUMP - CONTINUED

High voltage generator for the well of M1:

C1 C2

VDD = 3.3V

Vsub_hi

CStorage

0V

0V

3.3V

6.6V

Prevents latch-up of M1 by providing a high bulk bias (6.6V).

Use a separate clock driver for each switch to avoid crosstalk through the gate clock lines.Area for layout can be small.



SIMULATION OF THE CHARGE PUMP CIRCUIT

Circuit:VDD

C1

VSS

M1 CLK_out

CLK_in

M2M3

M4

Fig. 4.1-23

CLK_outM5

M6

C1

Simulation:3.0

2.0

1.0

0.0

-1.00.0 1.0 2.0 3.0 4.0 5.0 6.0 7.0 8.0 9.0 10.0

Vol

ts

Time (µs)

Input

Output

Fig. 4.1-24



SUMMARY OF MOS SWITCHES

• Symmetrical switching characteristics

• High OFF resistance

• Moderate ON resistance (OK for most applications)

• Clock feedthrough is proportional to size of switch (W) and inversely proportional to

switching capacitors.

• Output offset due to clock feedthrough has 3 components:

Ideal

Input dependent

Input independent

• Complementary switches help increase dynamic range.

• As power supply reduces, switches become more difficult to fully turn on.



AMPLIFIERS CONTINUOUS TIME AMPLIFIERS

+-

vIN

OUTvR1 R2

+-

vINR1 R2

OUTv

Noninverting Amplifier Inverting AmplifierGain and GB = ∞:

Vout

Vin =

R1+R2

R1

Vout

Vin = -

R2

R1

Gain ≠ ∞, GB = ∞:

Vout

Vin =

Avd(0)

1 + Avd(0)R 1

R1+R2

=

R1+R2

R1

Avd(0) R1

R1+R2

1 + A vd(0)R 1

R1+R2

Vout

Vin =

-R2Avd(0)R1+R2

1 + Avd(0)R 1

R1+R2

= -

R2

R1

R1Avd(0)R1+R2

1 + Avd(0)R 1

R1+R2

Gain ≠ ∞, GB ≠ ∞:

Vout(s)Vin(s) =

R1+R2

R1

GB·R1

R1+R2

s + GB·R 1

R1+R2

=

R1+R2

R1

ωH

s+ωH

Vout(s)Vin(s) =

- R 2

R1

GB·R1

R1+R2

s + GB·R 1

R1+R2

=

- R 2

R1

ωH

s+ωH



EXAMPLE 9.2-1 - ACCURACY LIMITATION OF VOLTAGE AMPLIFIERS DUE TO A FINITE VOLTAGE GAIN

Assume that the noninverting and inverting voltage amplifiers have been designed for avoltage gain of +10 and -10. If Avd(0) is 1000, find the actual voltage gains for each amplifier.Solution

For the noninverting amplifier, the ratio of R2/R1 is 9.

Avd(0)R1/(R1+R2) = 10001+9 = 100.

∴ Vout

V in = 10

100

101 = 9.901 rather than 10.

For the inverting amplifier, the ratio of R2/R1 is 10.Avd(0)R1

R1+R2 =

10001+10 = 90.909

∴ Vout

V in = -(10)

90.909

1+90.909 = - 9.891 rather than -10.



EXAMPLE 9.2-2 - - 3 dB FREQUENCY OF VOLTAGE AMPLIFIERS DUE TO FINITE UNITY-GAINBANDWIDTH

Assume that the noninverting and inverting voltage amplifiers have been designed for avoltage gain of +1 and -1. If the unity-gainbandwidth, GB, of the op amps are 2πMrads/sec, findthe upper -3dB frequency for each amplifier.

Solution

In both cases, the upper -3dB frequency is given by

ωH = GB·R1

R1+R2

For the noninverting amplifier with an ideal gain of +1, the value of R2/R1 is zero.

∴ ωH = GB = 2π Mrads/sec (1MHz)

For the inverting amplifier with an ideal gain of -1, the value of R2/R1 is one.

∴ ωH = GB·11+1 =

GB2 = π Mrads/sec (500kHz)



CHARGE AMPLIFIERS

+-

vIN

OUTvC1 C2

Noninverting Charge Amplifier

+-

vINOUTv

Inverting Charge Amplifier

C1 C2

Gain and GB = ∞:Vout

V in =

C1+C2

C2

Vout

V in = -

C1

C2Gain ≠ ∞, GB = ∞:

Vout

Vin =

C1+C2

C2

Avd(0)C2

C1+C2

1 + Avd(0)C2

C1+C2

Vout

Vin =

-C1

C2

Avd(0)C2

C1+C2

1 + Avd(0)C2

C1+C2Gain ≠ ∞, GB ≠ ∞:

Vout

Vin =

C1+C2

C2

GB·C2

C1+C2

s + GB·C2

C1+C2

Vout

Vin =

-C1

C2

GB·C2

C1+C2

s + GB·C2

C1+C2



SWITCHED CAPACITOR AMPLIFIERS

Parallel Switched Capacitor Amplifier:

1 2

+

-

1 2

voutinv

C1

2C

Inverting Switched Capacitor Amplifier

+

-

vC1

vC2

+

-

1 2

+

-

1

2C

C1

voutinv

Modification to prevent open-loop operation

vC1

vC2

+

-

+-

Analysis:

Assume that the switching frequency (clock frequency, fc = 1/T) is much greater than thesignal bandwidth. Then,

VoutVin

= - “R2”

“R1” ≈ - T/C2T/C1

= - C1C2

If the oversampling assumption is not made, then the transfer function becomes,

VoutVin

= - C1C2

z-1



FREQUENCY RESPONSE OF SWITCHED CAPACITOR AMPLIFIERS

Replace z by e jωT.

H(jω) = Vout(e jωT)

Vin(e jωT) = -

C1

C2 e -jωT/2

and

H(jω) = Vout(e jωT)

Vin(e jωT) = -

C1

C2 e -jωT

If C1/C2 is equal to R2/R1, then the magnitude response is identical to inverting unity gain amplifier.

However, the phase shift of Hoe(e jωT) is

Arg[H (e jωT)] = ±180° - ωT/2

and the phase shift of Hoe(e jωT) is

Arg[H (e jωT)] = ±180° - ωT.

Comments:

• The phase shift of the switched capacitor inverting amplifier has an excess linear phase delay.

• When the frequency is equal to 0.5fc, this delay is 90°.

• One must be careful when using switched capacitor circuits in a feedback loop because of theexcess phase delay.



POSITIVE AND NEGATIVE TRANSRESISTANCE EQUIVALENT CIRCUITS

Transresistance circuits are two-port networks where the voltage across one port controls thecurrent flowing between the ports. Typically, one of the ports is at zero potential (virtual ground).

Circuits:

Positive Transresistance Realization.

1

2 2

1C

vC(t)

v1(t)

i1(t) i2(t)

CP CP

Negative Transresistance Realization.

1

2

2

1C

vC(t)

v1(t)

i1(t) i2(t)

CP CP

Analysis (Negative transresistance realization):

RT = v1(t)i2(t)

= v1

i2(average)

If we assumev1(t) is approximately constant over one period of the clock, then we can write

i2(average) = 1T ⌡⌠

T/2

T

i2(t)dt = q2(T) - q2(T/2)

T = CvC(T) - CvC(T/2)

T = -Cv1

T

Substituting this expression into the one above shows that

R T = -T / C

Similarly, it can be shown that the positive transresistance is T/C.

Comments:

• These results are only valid when fc >> f.

• These circuits are insensitive to the parasitic capacitances shown as dotted capacitors.



INVERTING STRAY INSENSITIVE SWITCHED CAPACITOR AMPLIFIER

Inverting Switched Capacitor Voltage Amplifier.

1

2

+

-

1

2C

voutinv vC2+-

1

2

vC1(t)vC1(t)

1C

vC1(t)

Analysis:


VoutVin

= - “R2”

“R1” ≈ - T/C2T/C1

= - C1C2



NONVERTING STRAY INSENSITIVE SWITCHED CAPACITOR AMPLIFIER

Use the negative transresistor switched capacitor circuit at the input to get,

Noninverting Switched Capacitor Voltage Amplifier.

1 2

+

-

1

2C

voutinv vC2+-

121C

vC1(t)

Analysis:


VoutVin

= - “R2”

“R1” ≈ - T/C2-T/C1

= + C1C2



EXAMPLE 9.2-3 - DESIGN OF A SWITCHED CAPACITOR SUMMING AMPLIFIER

Design a switched capacitor summing amplifier using the circuits in stray insensitivetransresistance circuits which gives the output voltage during the φ2 phase period that is equal to10v1 - 5v2, where v1 and v2 are held constant during a φ2-φ1 period and then resampled for the nextperiod.

Solution

Based on the previous examples, a solution is proposed below.

1 2

+

-

1

vo12

v1

1

2

1

2v2

C

10C

5C

It easy to show that if the oversampling assumption is true that,

Vo ≈ 10V1 - 5V2



NONIDEAL OP AMPS - FINITE GAIN

Consider the inverting switched capacitor amplifier during φ2:

inv

+

-

2CC1

+

-

(n-1)T

vout (n-1/2)Te

ovout (n-1/2)T

e

Avd(0)+- Op amp with finite

value of Avd(0)Fig. 9.2-11

The output during φ2 can be written as,

ve

out(n -1/2)T =

C1

C2 v

oin(n -1)T +

C1+C2

C2 v

eout(n -1/2)T

Avd(0)

Converting this to the z-domain and solving for the Hoe(z) transfer function gives

Hoe(z) = V

eout(z)

Voin(z)

=

C1

C2 z-1/2

1

1 - C1 + C2

Avd(0)C2

.

Comments:• The phase response is unaffected by the finite gain

• A gain of 1000 gives a magnitude of 0.998 rather than 1.0.



NONIDEAL OP AMPS - FINITE BANDWIDTH AND SLEW RATE

Finite GB:

• In general the analysis is complicated. (We will provide more detail for integrators.)

• The clock period, T, should be equal to or less that 10/GB.

• The settling time of the op amp must be less that T/2.

Slew Rate:

• The slew rate of the op amp should be large enough so that the op amp can make a fullswing within T/2.



CONTINUOUS TIME INTEGRATORS

-R1 C2 R R VoutVin

(a.)

+-

+-

Inverter

(b.)

R1 C2Vin Vout

+-

(a.) Noninverting and (b.) inverting continuous time integrators.

Ideal Performance:

Noninverting- Inverting-

Vout(jω)Vin(jω) =

1jω R 1C2

= ωI

jω = -jωI

ω Vout(jω)Vin(jω) =

-1jω R 1C2

= -ωI

jω = jωI

ω

Frequency Response:

90°

0°

Arg[Vout(jω)/Vin(jω)]

ωI log10ω

|Vout(jω)/Vin(jω)|

ωIωIωI100 10

10ωI 100ωI

log10ω

40 dB

20 dB

0 dB

-20 dB

-40 dB

(a.) (b.)



NONINVERTING SWITCHED CAPACITOR INTEGRATOR

Approximate analysis:

Assume that the switching frequency (clock frequency,fc = 1/T) is much greater than the signal bandwidth. Then,

VoutVin

= - 1/sC2 “R1” ≈ -

1/sC2-T/C1

= + C1

sTC2 =

ωIs

where

ωI = CI

TC2

Exact analysis:Vout(z) Vin(z) =

C1

C2

z-1

1-z-1 =

C1

C2

1z-1

Exact frequency response (replace z by ejωT ) to get,

Vout(ejωT)

Vin(ejωT) =

C1

C2

e-jωΤ/2

j2 sin(ωT/2)

ωT

ωT =

C1

jωTC2

ωT/2

sin(ωT/2) ( )e-jωΤ/2

= (Ideal)x(Magnitude error)x(Phase error) where ωI = C1

TC2 ⇒ Ideal =

ωI

jω

Noninverting, stray insensitive integrator.

1 2

2C

voutinv vC2+-

12

1C

vC1(t)

+-

+ -S1

S2 S3

S4



EXAMPLE 9.3-2 - COMPARISON OF A CONTINUOUS TIME AND SWITCHED CAPACITOR INTEGRATOR

Assume that ωI is equal to 0.1ωc and plot the magnitude and phase response of thenoninverting continuous time and switched capacitor integrator from 0 to ωI.

Solution

Letting ωI be 0.1ωc gives

H(jω) = 1

10jω/ωc and Hoo(e jωΤ) =

1

10jω/ωc

πω/ωc

sin(πω/ωc) ( )e-jπω/ωc

Plots:

0

1

2

3

4

5

0 0.2 0.4 0.6 0.8 1

Magnitude

|Hoo(ejωT)|

|H(jω)|ωI

ω/ωc

-300

-250

-200

-150

-100

-50

0

0 0.2 0.4 0.6 0.8 1

Phase Shift (Degrees)

Arg[Hoo(ejωT)]

Arg[H(jω)]

ωI ω/ωc



INVERTING SWITCHED CAPACITOR INTEGRATOR

Analysis:

Approximate analysis:

Assume that the switching frequency (clockfrequency, fc = 1/T) is much greater than the signalbandwidth. Then,

VoutVin

= - 1/sC2 “R1” ≈ -

1/sC2T/C1

= - C1

sTC2 = -

ωIs

where

ωI = CI

TC2

Exact analysis:

H(z) = Vout(z) Vin(z) = -

C1

C2

11-z-1 = -

C1

C2

zz-1

Exact frequency response (replace z by ejωT ) to get,

Vout(ejωT)

Vin(ejωT) =

C1

C2

e-jωΤ/2

j2 sin(ωT/2)

ωT

ωT = -

C1

jωTC2

ωT/2

sin(ωT/2) ( )e jωΤ/2

Same as noninverting integrator except for phase error.

Consequently, the magnitude response is identical but the phase response is given as

Arg[H(e jωΤ)] = π2 + ωΤ

2 .

Inverting, stray insensitive integrator.

1

2

2C

voutinv vC2+-

1

2

1C

vC1(t)

+-

S1

S2 S3

S4



A SIGN MULTIPLEXER

A circuit that changes the φ1 and φ2 of the leftmost switches of the stray insensitive, switchedcapacitor integrator.

1 2

VC

x

y

To switch connectedto the input signal (S1).

To the left most switchconnected to ground (S2).

VC

0

1

x y

1

12

2

Fig. 9.3-8

This circuit steers the φ1 and φ2 clocks to the input switch (S1) and the leftmost switch connected toground (S2) as a function of whether Vc is high or low.



FIRST-ORDER, SWITCHED CAPACITOR CIRCUITS GENERAL, FIRST-ORDER TRANSFER FUNCTIONS

A general first-order transfer function in the s-domain:

H(s) = sa1 ± a0

s + b0

a1 = 0 ⇒ Low pass, a0 = 0 ⇒ High Pass, a0 ≠ 0 and a1 ≠ 0 ⇒ All pass

Note that the zero can be in the RHP or LHP.

The following continuous time circuit is capable of realizing most of the various forms above:

+-

R1 R2

C1 C2

Vin Vout

Fig.9.5-0

VoutVin

= -

R2

R1 sR1C1+1

sR2C2+1



NONINVERTING, FIRST-ORDER, LOW PASS CIRCUIT

+-

vi(t)

φ1

φ1φ2

φ2

φ2

vo(t)

C1

(a.) (b.)Figure 9.5-1 - (a.) Noninverting, first-order low pass circuit. (b.) Equivalent circuit of Fig. 9.5-1a.

φ1 φ1 φ2

+-

vi(t)

φ1

φ1φ2

φ2

φ2

vo(t)

φ2

φ1φ1vo(t)

α1C1

α2C1

α2C1

α1C1

C1

Transfer function:

Noting that C1 of the general circuit is zero gives,

VoutVin

= -

“R2”

”R1” 1

s”R2”C2+1 ≈ -α1α2

1

sT/α2 +1 = -α1

sT + α 2 =

-α1/T

s + α 2/T

Equating the above to the H(s) of the general first-order transfer function gives,

α1 = a0T = a0fc

and α2 = b0T = b0fc



INVERTING, FIRST-ORDER, LOW PASS CIRCUIT

An inverting low pass circuit can be obtained by reversing the phases of the leftmost two switches inFig. 9.5-1a.

+-

vi(t)

φ2

φ1φ1

φ2

φ2

vo(t)

C1

Inverting, first-order low pass circuit. Equivalent circuit.

φ1 φ1 φ2

+-

vi(t)

φ2

φ1φ1

φ2

φ2

vo(t)

φ2

φ1φ1vo(t)

α1C1

α2C1

α2C1

α1C1

C1

It can be shown that,

VoutVin

=

“R2”

”R1” 1

s”R2”C2+1 ≈ α1α2

1

sT/α2 +1 = α1

sT + α 2 =

α1/T

s + α 2/T

Equating the above to the H(s) of a general first order transfer function gives the design equations as

α1 = a0T = a0fc




EXAMPLE 9.5-1 - DESIGN OF A SWITCHED CAPACITOR FIRST-ORDER CIRCUIT

Design a switched capacitor first-order circuit that has a low frequency gain of +10 and a -3dB frequency of 1kHz. Give the value of the capacitor ratios α1 and α2. Use a clock frequency of100kHz.

Solution

Assume that the clock frequency, fc, is much larger than the -3dB frequency. In this example,the clock frequency is 100 times larger so this assumption should be valid. Therefore we can write,

Vout(s)

Vin(s) ≈ α1

α 2 + s T = α1/α2

1 + s(T/α 2)

Setting this equation equal to the specifications gives α1 = 10α2 and α2 = ω-3dB

fc

∴ α 2 = 6283/100,000 = 0.0628 and α 1 = 0.6283

The above represent capacitor ratios and should preferably be close to unity for small area.



FIRST-ORDER, HIGH PASS CIRCUIT

+-

vi(t)

φ2

vo(t)α1C

C

φ1 φ1 φ2α2C

+-

vi(t)

φ2

φ2

vo(t)

C

φ1 φ1 φ2

(a.) (b.)Figure 9.5-3 - (a.) Switched-capacitor, high pass circuit. (b.) Version of Fig. 9.5-3athat constrains the charging of C1 to the φ2 phase.

α1C

α2C

Transfer function:

It can be shown that,

VoutVin

= - s“R2”C1

s”R2”C2+1 ≈ - sTα1C/α2C

sTC/α2C +1 = - sTα1/α2sT/α2 +1 = -

sTα1sT + α 2

= - sα1

s + α 2/T

Equating the above to the general first-order H(s) gives the design equations as

a1 = α1 and α2/T = b0

Solving for α1 and α2 gives

α1 = a1 and α2 =b0T = b0fc



FIRST-ORDER, ALLPASS CIRCUIT

+-

vi(t)

φ1

φ1φ2

φ2

φ2

vo(t)

C

(b.)

φ1 φ1 φ2

φ2

+-

vi(t)

φ1

φ1φ2

φ2

φ2

vo(t)

α1C C

(a.)

φ1 φ1 φ2α3C

Figure 9.5-5 - (a.) High or low frequency boost circuit. (b.) Modification of (a.) to simplifythe z-domain modeling

α2C α3C α2C

α1C

Transfer function:

Summing the currents flowing into the inverting input of the op amp gives

VoutVin

= -

“R2”

“R1” s“R1”C1+1

s“R2”C2+1 = -

α1

α2 sTα3/α1+1

sT/α2+1 = - α 3s + α 1/T

s + α 2/T

Therefore,

α3 = a1, α1/T = a0 and α2/T = b0

or

a1 = α3, α1 = a0T = a0fc




EXAMPLE 9.5-2 - DESIGN OF A SWITCHED CAPACITOR BASS BOOST CIRCUIT

Find the values of the capacitor ratiosα1, α2, and α3 using a 100kHz clock for Fig. 9.5-5 that willrealize the asymptotic frequency response shown in Fig. 9.5-7.

dB

20

01kHz 10kHz10Hz 100Hz

FrequencyFigure 9.5-7 - Bass boost response for Ex. 9.5-2.

Solution

From the previous results, we can write the all-pass transfer function approximately as,

H(s) ≈ -sTα 3 + α 1

sT + α 2 = -

α1

α2

sTα 3/α 1 - 1

sT/α 2 + 1

From Fig. 9.5-7, we see that the desired response has a dc gain of 10, a right-half plane zero at 2πkHz and a pole at -200π Hz. Thus, we see that the following relationships must hold.

α1

α2 = 10 ,

α1

Tα3 = 2000π , and

α2

T = 200π

From these relationships we get the desired values as

α 1 = 2000π

fc, α 2 =

2 0 0 πfc

, a n d α 3 = 1



PRACTICAL IMPLEMENTATIONS OF THE FIRST-ORDER CIRCUITS

Most practical implementations of switched capacitor circuits are fully differential as shown below.

+-

vi(t)

φ1

φ1φ2

φ2

φ2

vo(t)C1

C

(a.) (b.)Figure 9.5-8 - Differential implementations of (a.) Fig. 9.5-1, (b.) Fig. 9.5-3, and (c.) Fig. 9.5-5.

φ1 φ1

φ2α2C

vo(t)

+-

C

φ1 φ1

φ2 φ2

φ1 φ2+

-

+-

vi(t)

φ2

φ2

vo(t)

C

φ1 φ1

φ2

vo(t)

+-

C

φ1 φ1

φ2 φ2

φ2

+-

+-

vi(t)

φ1

φ1φ2

φ2

φ2

vo(t)

C

(c.)

φ1 φ1φ2

vo(t)

+-

C

φ1 φ1

φ2 φ2

φ1 φ2

+-

φ2

φ2α2C

α1C

α1C

α2C

α2C

α1C

α1C

α2C

α2C

α1C

α1C

α3C

α3C

Comments:

• Differential operation reduces clock feedthrough, common mode noise sources and enhances thesignal swing.

• Differential operation requires op amps or OTAs with differential outputs which in turnrequires a means of stabilizing the output common mode voltage.



ANTI-ALIASING IN SWITCHED CAPACITOR FILTERS

A characteristic of circuits that sample the signal (switched capacitor circuits) is that the signalpassbands occur at each harmonic of the clock frequency including the fundamental.

T(jω)

T(j0)T(jωPB)

ωPB

00

ω

Figure 9.7-28 - Spectrum of a discrete-time filter and a continuous-time anti-aliasing filter.

-ωPB ωc 2ωc

ωc+ωPBωc-ωPB 2ωc-ωPB 2ωc+ωPB

Anti-Aliasing Filter

Baseband

The primary problem of aliasing is that there are undesired passbands that contribute to thenoise in the desired baseband.



NOISE ALIASING IN SWITCHED CAPACITOR CIRCUITS

In all switched capacitor circuits, a noise aliasing occurs from the passbands that occur at theclock frequency and each harmonic of the clock frequency.

f0.5fc fcfBfsw-fB

fc-fsw

fc+fBfc-fB

fc+fsw

Magnitude

0

Noise Aliasing

From higher bands

Baseband

Figure 9.7-31 - Illustration of noise aliasing in switched capacitor circuits.

It can be shown that the aliasing enhances the baseband noise voltage spectral density by a factor of2fsw/fc. Therefore, the baseband noise voltage spectral density is

eBN2 =

kT/C

fswx

2fsw

fc =

2kTfcC

volts2/Hz

Multiplying this equation by 2fB gives the baseband noise voltage in volts(rms)2. Therefore, thebaseband noise voltage is

vBN2 =

2kT

fcC ( )2fB =

2kTC

2fB

fc =

2kT /COSR volts(rms)2

where OSR is the oversampling ratio.



SUMMARY• Switched capacitor circuits have reached maturity in CMOS technology.

• The switched capacitor circuit concept was a pivotal step in the implementation of analog signalprocessing circuits in CMOS technology.

• The accuracy of the signal processing is proportional to capacitor ratios.

• Switched capacitor circuits have been developed for:

Amplification

Integration

Differentiation

Summation

Filtering

Comparing

Analog-digital conversion

• Approaches to switched capacitor circuit design:

Oversampled approach - clock frequency is much greater than the signal frequency

z-domain approach - specifications converted to the z-domain and directly realized, can operate to within half of the clock frequency (not covered in the above notes)

• Clock feedthrough and kT/C noise represent the lower limit of the dynamic range of switchedcapacitor circuits.

switched capacitor circuits -...

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