Switched CapacitorConcepts & Circuits

Outline• Why Switched Capacitor circuits?

– Historical Perspective– Basic Building Blocks

• Switched Capacitors as Resistors• Switched Capacitor Integrators

– Discrete time & charge transfer concepts– Parasitic insensitive circuits

• Signal Flow Graphs• Switched Capacitor Filters

– Comparison to Active RC filters– Advantages of Fully Differential filters

• Switched Capacitor Gain Circuits• Reducing the Effects of Charge Injection• Tradeoff between Speed and Charge Injection

Why Switched Capacitor Circuits?

• Historical Perspective– As MOS processes came to the forefront in the late 1970s and

early 1980s, the advantages of integrating analog blocks such asactive filters on the same chip with digital logic became a driving force for inovation.

– Integrating active filters using resistors and capacitors to acturately set time constants has always been difficult, because of large process variations (> +/- 30%) and the fact that resistors and capacitors don’t naturally match each other.

– So, analog engineers turned to the building blocks native to MOSprocesses to build their circuits, switches & capacitors. Since time constants can be set by the ratio of capacitors, very accurate filter responses became possible using switched capacitor techniques

Mixed-Signal Design was born!

Switched Capacitor Building Blocks

• Capacitors: poly-poly, MiM, metal sandwich & finger caps

• Switches: NMOS, PMOS, T-gate

• Op Amps: at first all NMOS designs, now CMOS

Non-Overlapping Clocks

• Non-overlapping clocks are used to insure that one set of switches turns off before the next set turns on, so that charge only flows where intended. (“break before make”)

• Note the notation used to indicate time based on clock periods: ... (n-1)T, (n-½)T, nT, (n+½)T, (n+1)T ...

Switched Capacitors as Resistors

I = dq/dt = ∆q/∆t = C1(V1 – V2)/Twhere T = clock period

compare this to: I = (V1 – V2)/Req

Req = T/C1 or Req = 1/fs C1

Switched Capacitors as Resistors (cont.)

Switched Capacitor Integrator

• The resistor input of a traditional op amp integrator is replaced by a switched capacitor resistor

• This SC integrator operates in discrete time increments, first sampling the input signal onto C1, and then switching C1 to transfer this charge onto C2 :

Q1(n-1) = C1·Vi(n-1) and Q2(n-½) = Q2(n-1) - Q1(n-1)

Vo(n) = Vo(n-½) = Q2(n-½)/C2 = Vo(n-1) - (C1/C2)·Vi(n-1)

Vo(z) = z-1·Vo(z) - (C1/C2) z-1·Vi(z) H(z) = -(C1/C2)/(z-1)

Switched Capacitor Integrator (cont.)

Effect of Parasitic Capacitors

• Cp2 and Cp3 cause no errors because they are in parallel with ground and virtual ground, respectively, and so remain uncharged.

• Cp4 does increase the load capacitance that the op amp must drive, but causes no errors.

• Cp1, the parasitic cap associated with the top plate of C1,appears directly in parallel with C1 and changes the transfer function to :

⎟⎠⎞

⎜⎝⎛

−⎟⎟⎠

⎞⎜⎜⎝

⎛ +−=

1z1

CCC

)z(H2

1p1

Parasitic Insensitive Integrators

• During clock phase 1, C1 is charged to the input voltage

• During clock phase 2, this charge is transferred to C2However, since the + side of C1 is tied to ground, this results in a non-inverting transfer function :

⎟⎠⎞

⎜⎝⎛

−⎟⎟⎠

⎞⎜⎜⎝

⎛=

1z1

CC)z(H2

1

Parasitic Insensitive Integrators (cont.)

• Cp2, Cp3 are in parallel with ground or virtual ground and Cp4 is in parallel with the output, so they cause no errors.

• In this circuit, Cp1 is once again charged to the input voltage on clock phase 1. However, this time Cp1 is discharged to ground on clock phase 2. Since no error charge is transferred to C2, the transfer function is insensitive to this parasitic cap and remains unchanged.

Parasitic Insensitive Integrators (cont.)

• Similar to the previous circuit, just the clock phases changed

( ) ( ) ( )

( ) ( ) ( )

( ) ( ) ( )

( ) ( )( ) ⎟

⎠⎞

⎜⎝⎛

−−=⎟

⎠⎞

⎜⎝⎛−

−==⇒

−=

−−=

−−=

−

−

1zz

CC

z11

CC

zVzVzH

zVCCzVzzV

nVCC1nVnV

nVC1nVCnVC

2

11

2

1

i

O

i2

1O

1O

i2

1OO

i1O2O2

Signal Flow Graphs

• Can be used to show a function symbolically

• Sometimes easier than keeping track of charge movement for a complicated circuit (e.g., SC filters)

• The example shown is just a superposition of our previous 2 cases, plus a non-switched capacitor input

Switched Capacitor Filters

( )1z

CC1

CCz

CCC

zH

A

3

A

1

A

21

−⎟⎟⎠

⎞⎜⎜⎝

⎛+

−⎟⎟⎠

⎞⎜⎜⎝

⎛ +

−=

• Take an active RC filter and replace the R’s with SC equivalents

substituting z = ejωT = cos(ωT) + jsin(ωT)

into H(z) and solving assuming ωT << 1

A

3

A

3

p

C2C1

CC

Tj+

−=ω⇒ eq. 10.42

• For cases where we can’t assume that ωT << 1,we have to “pre-warp”the pole/zero frequencies to convert from thes-domain to z-domain using Ω = tan(ω/2)

• This makes use of the bilinear transform

p = (z – 1)/(z + 1)

where p = σp + jΩ

• Note that this maps the unit circle in the z-domain onto the jω-axis

Switched Capacitor Filters (cont.)

• This circuit is identical to the previous one, except the switches on the left side of C3 are now being shared with the switches on the right side of C2 to reduce area and wiring complexity

Fully Differential SC Filters

Key Advantages offully differential circuits :• Noise appears as a

common-mode signal• Even-order distortion

terms cancel

Switched Capacitor Gain Circuits

( )( ) KzVzV)z(H

in

out −==

SC Gain Circuits with Reset

• Voltage gain = - C1/C2

• Output is reset every clock period during Φ2

• Cancels offset by storingVos on C1 and C2 during reset

But, the op amp must :

• Be able to slew fast

• Be stable for unity gain

SC Gain Circuits with Reset (cont.)

• Very similar to previous circuit, with Vos cancellation and gain = - C1/C2 , except

• Vout is stored on C3, which is used during reset to keep the output voltage from needing to slew down to 0V

• C4 is an optional “deglitching” cap sometimes used to provide feedback during the clock’s non-overlap time

Quazi-Differential SC Circuits

• By including a “replica” of all caps and switches on the op amp’s + input, a single-ended circuit can be made to appear “quazi-differential”, thus making charge injection errors look common-mode (max improvement ~ 20dB)

• Also provides differential to single-ended conversion

Reducing the Effects of Charge Injection

• Charge injection errors can be greatly reduced by the used of “advanced” clocks, which switch just slightly earlier than the main clocks

• Once Q3,4 above turn off, one side of C2,3 is an open circuit the charge injected by the other switches can’t change the charge stored on these caps!

• Still have charge injection from Q3,4 , but since these are tied to a virtual ground this just looks like an offset

Tradeoff between Speed & Charge Injection

• For high speed, we need to use large switches tosettle fast, but this means more charge injection!

2ERR

CLK

ONOXCHERR

ONOX

ON

ONCLKON

L5Vf

ngsubstitutiC2VWLC

C2QV

VLWC

1R

CR101fCR5

2T

µ<

⇒

==

µ=

<⇒>

Tradeoff between Speed & Charge Injection

• Note that this result is independent of cap size and supply voltage, and is proportional to 1/L2

Big improvements as we scale to smaller processes!