Switched capacitor

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<ol><li> 1. 1 Data Converters Switched-Capacitor Circuits Professor Y. Chiu EECT 7327 Fall 2014 Switched-Capacitor Circuits </li><li> 2. Continuous-Time Integrator 2 Data Converters Switched-Capacitor Circuits Professor Y. Chiu EECT 7327 Fall 2014 Goal: C2 Vi Vo R1 C2 Vi Vo SC t o in 1 2 - o i 1 2 1 v t = - v d R C V 1 1 H s = s = - V R C s Approach: emulating resistors with switched capacitors 1 2=R C </li><li> 3. Concept of Switched Capacitor 3 Data Converters Switched-Capacitor Circuits Professor Y. Chiu EECT 7327 Fall 2014 A B q C i = = V - V T T A B 1 i = V - V R 2 1 eq T R = C A switched capacitor is a discrete-time resistor RC time constant set by capacitor ratio C2/C1 (match considerably better than R and C) and clock period T (flexibility) R VA VB i C 22 11 VA VB <i> so, 2 eq,1 2 2 1 1 CT =R C = C = T C C Non-overlapping two-phase clock </i></li><li> 4. Switched Capacitors 4 Data Converters Switched-Capacitor Circuits Professor Y. Chiu EECT 7327 Fall 2014 1 2 1 2 1 2 Shunt- and series-type SCs are simple and cheap to implement Stray-insensitive SC requires 2 more switches, whats the advantage besides being more flexible (i.e., w/ or w/o the T/2 delay)? 2-phase clock 21 VA VB C1 VA VB C 2 Series-typeShunt-type C 22(1) 11(2) VA VB Stray-insensitive </li><li> 5. Discrete-Time Integrator (DTI) 5 Data Converters Switched-Capacitor Circuits Professor Y. Chiu EECT 7327 Fall 2014 2-phase clock C2 Vi Vo 21 C1 Series-typeShunt-type 1 2 1 2 1 2 What are the VTFs (z-domain) of these DTIs, assuming no parasitic capacitance is present? C2 Vi Vo C11 2 </li><li> 6. Shunt-Type DTI 6 Data Converters Switched-Capacitor Circuits Professor Y. Chiu EECT 7327 Fall 2014 1 (sample) Charge conservation law (ideal): Total charge on C1 and C2 during 1 2 transition must remain unchanged! C2 Vi Vo C1 C2 Vo C1 Vi 2 (update) 1 2 1 2 1 2 T vi(t) 0 t vo(t) 0 t (n-1) (n) (n+1) (n-1) (n) (n+1) </li><li> 7. Shunt-Type DTI 7 Data Converters Switched-Capacitor Circuits Professor Y. Chiu EECT 7327 Fall 2014 1 (sample) 2 (update) C2 Vi Vo C1 C2 Vo C1 Vi 1 i 1 o 2Q = V n C - V n C 2 1 o 2Q = 0 C - V n+1 C 1 2 i 1 o 2 1 o 2Q = Q V n C - V n C = 0 C - V n+1 C i 1 o 2 o 2V z C - V z C = -z V z C -1 -1/2 o 1 1 -1 -1 i 2 2 V z C Cz z H z = = - or - V z C 1- z C 1- z </li><li> 8. Series-Type DTI 8 Data Converters Switched-Capacitor Circuits Professor Y. Chiu EECT 7327 Fall 2014 1 (sample/update) 2 (reset C1) C2 Vi Vo C11 2 o 1 -1 i 2 V z C 1 H z = = - V z C 1- z VTF: 1 2 1 2 1 2 T vi(t) 0 t vo(t) 0 t (n-1) (n) (n+1) (n-1) (n) (n+1) </li><li> 9. Stray Capacitance 9 Data Converters Switched-Capacitor Circuits Professor Y. Chiu EECT 7327 Fall 2014 Series-typeShunt-type Cu Cu Cu Cu Cu C1 C2 Strays derive from D/S diodes and wiring capacitance VTF is modified due to strays Strays at the summing node is of no significance (virtual ground) 2 1 C = 4 C C2 Vi Vo C1 1 2 A C2 Vi Vo C1 1 2 A </li><li> 10. Stray-Insensitive SC Integrator 10 Data Converters Switched-Capacitor Circuits Professor Y. Chiu EECT 7327 Fall 2014 1 -1 2 C 1 H z = - C 1- z VTF: -1 1 -1 2 C z H z = + C 1- z Capacitors can be significantly sized down to save power/area Sizes are eventually limited by kT/C noise, mismatch, etc. C1 22(1) 11(2) C2 Vi Vo A B Inverting Non-inverting VTF: </li><li> 11. SC Amplifier 11 Data Converters Switched-Capacitor Circuits Professor Y. Chiu EECT 7327 Fall 2014 -11 2 C H z = + z C Non-integrating, memoryless (less the delay) Used in many applications of parametric amplification VTF: Vi C2 C11 2 1 Vo </li><li> 12. 12 Data Converters Switched-Capacitor Circuits Professor Y. Chiu EECT 7327 Fall 2014 SC Applications </li><li> 13. CT Filter 13 Data Converters Switched-Capacitor Circuits Professor Y. Chiu EECT 7327 Fall 2014 R CVi Vo L R1 CA R R R3 R4 CB R2 Vi Vo RLC prototype Active-RC Tow-Thomas CT biquad </li><li> 14. SC DT Filter 14 Data Converters Switched-Capacitor Circuits Professor Y. Chiu EECT 7327 Fall 2014 SC DT biquad CA CB Vi Vo C1 22 11 C2 C4 2 1 C3 21 12 2 R1 CA R R R3 R4 CB R2 Vi Vo Active-RC Tow-Thomas CT biquad </li><li> 15. Sigma-Delta () Modulator 15 Data Converters Switched-Capacitor Circuits Professor Y. Chiu EECT 7327 Fall 2014 CI 21 12 Vi Do +VR 1-b DAC-VR CS DTI + 1-bit comparator + 1-bit DAC = first-order ADC </li><li> 16. Pipelined ADC 16 Data Converters Switched-Capacitor Circuits Professor Y. Chiu EECT 7327 Fall 2014 SC amplifier + 2 comparators + 3-level DAC = 1.5-bit pipelined ADC Vo Vi 0 -VR VR 1.5-b DAC 1 C1 1 C2 2 1 2 -VR/4 VR/4 </li><li> 17. SC Common-Mode Feedback 17 Data Converters Switched-Capacitor Circuits Professor Y. Chiu EECT 7327 Fall 2014 Vo + Vo - R A R VBias Vcm Vcmc Vo + Vo - R A R Vcmc Vcm-VBias CM sense amp can be replaced by a floating voltage source since the gain through the main op-amp is high enough. </li><li> 18. SC Common-Mode Feedback 18 Data Converters Switched-Capacitor Circuits Professor Y. Chiu EECT 7327 Fall 2014 Vo + Vo - A Vcmc C C 0.2C 0.2C 2 2 2 1 1 1 Vcm Vcm VBias Vo + Vo - A Vcmc Vcm-VBias Vcm-VBias 2 1 </li><li> 19. 19 Data Converters Switched-Capacitor Circuits Professor Y. Chiu EECT 7327 Fall 2014 Noise in SC Circuits </li><li> 20. Noise of CT Integrator 20 Data Converters Switched-Capacitor Circuits Professor Y. Chiu EECT 7327 Fall 2014 Noise in CT circuits can be simulated with SPICE (.noise) R C Vi Vo R C Vo VN1 2 VN2 2 H1(f) H2(f) 2 2 2 22 N1 N2 oN 1 2 V V V = f H f df + f H f df +... f f </li><li> 21. Noise of SC Integrator 21 Data Converters Switched-Capacitor Circuits Professor Y. Chiu EECT 7327 Fall 2014 SC circuits are NOT noise-free! Switches and op-amps introduce noise. 1 2 1 2 1 2 C2 C1 21 12 Vi Vo </li><li> 22. Sampling (1) Ideal Voltage Source 22 Data Converters Switched-Capacitor Circuits Professor Y. Chiu EECT 7327 Fall 2014 Noise is indistinguishable from signal after sampling The noise acquired by C1 will be amplified in 2 just like signal 2 2 22 N1 N2 N 10 2 1 20 1 2 V V V 1 = f + f H f df f f 1 = 4kTR +4kTR df 1+ j2f R +R C kT = C C1 Vi R1 R2 VN1 2 VN2 2 </li><li> 23. Integration (2) 23 Data Converters Switched-Capacitor Circuits Professor Y. Chiu EECT 7327 Fall 2014 No simulator can directly simulate the aggregated output noise! 2 22 2 22 N3 N5N4 N 34 5 V VV V 2 = f + f H f df + f H f df +... f f f 2 2 2 21 oN N N 2 C V = V 1 + V 2 C Vo VN3 2 VN5 2 H34(f) H5(f) C1 C2 R4VN4 2 R3 </li><li> 24. Sampling (1) Noise Cascaded Stages 24 Data Converters Switched-Capacitor Circuits Professor Y. Chiu EECT 7327 Fall 2014 C1'R1 R2 VN3 2 VN5 2 VN1 2 VN2 2 C1 C2 R4VN4 2 R3 Finite op-amp BW limits the noise bandwidth, resulting in less overall kT/C noise (noise filtering). But parasitic loop delay may introduce peaking in freq. response, resulting in more integrated noise (noise peaking). C2 C2' Vi Vo C1 12 21 C1' 21 12 2 </li><li> 25. Sampled Noise Spectrum 25 Data Converters Switched-Capacitor Circuits Professor Y. Chiu EECT 7327 Fall 2014 Total integrated noise power remains constant SNR remains constant CT DT PSD fs/2 fs 3/2fs 0 PSD fs 2fs 0 Alias </li><li> 26. 26 Data Converters Switched-Capacitor Circuits Professor Y. Chiu EECT 7327 Fall 2014 Non-ideal Effects in SC Circuits </li><li> 27. Non-ideal Effects in SC Circuits 27 Data Converters Switched-Capacitor Circuits Professor Y. Chiu EECT 7327 Fall 2014 Capacitors (poly-poly, metal-metal, MIM, MOM, sandwich, gate cap, accumulation-mode gate cap, etc.) PP, MIM, and MOM are linear up to 14-16 bits (nonlinear voltage coefficients negligible for most applications) Gate caps are typically good for up to 8-10 bits Switches (MOS transistors) Nonzero on-resistance (voltage dependent) (Nonlinear) stray capacitance added (Cgs, Cgd, Cgb, Cdb, Csb) Switch-induced sampling errors (charge injection, clock feedthrough, junction leakage, drain-source leakage, and gate leakage) Operational amplifiers Offset Finite-gain effects (voltage dependent) Finite bandwidth and slew rate (measured by settling speed) </li><li> 28. 28 Data Converters Switched-Capacitor Circuits Professor Y. Chiu EECT 7327 Fall 2014 Non-ideal Effects of Switches </li><li> 29. Nonzero On-Resistance 29 Data Converters Switched-Capacitor Circuits Professor Y. Chiu EECT 7327 Fall 2014 FET channel resistance (thus tracking bandwidth) depends on signal level Usually (RonCS)-1 (3-5)-3dB of closed-loop op-amp for settling purpose VGS Vout C CS CS Ron 0 VDDVout VTnVTp PMOS NMOS CMOS -1 on ox DD th out W R = C V - V - V L </li><li> 30. Clock Bootstrapping 30 Data Converters Switched-Capacitor Circuits Professor Y. Chiu EECT 7327 Fall 2014 Small on-resistance leads to large switches large parasitic caps and large clock buffers Clock bootstrapping keeps VGS of the switch constant constant on- resistance (body effect?) and less parasitics w/o the PMOS CS OutIn M1 VDD 1 2 CMOS Bootstrapped NMOS </li><li> 31. Simplified Clock Bootstrapper 31 Data Converters Switched-Capacitor Circuits Professor Y. Chiu EECT 7327 Fall 2014 Pros Linearity Bandwidth Cons Device reliability Complexity Out C In M2 M1 VDD VSS OutIn M1 VDD 1 2 1 1 2 2 2 2 </li><li> 32. Switch-Induced Errors 32 Data Converters Switched-Capacitor Circuits Professor Y. Chiu EECT 7327 Fall 2014 Channel charge injection and clock feedthrough (on drain side) result in charge trapped on CS after switch is turned off. Vout CS Zi Vin CgdCgs Qch Clock feedthrough Charge injection </li><li> 33. Clock Feedthrough and Charge Injection 33 Data Converters Switched-Capacitor Circuits Professor Y. Chiu EECT 7327 Fall 2014 Both phenomena sensitive to Zi, CS, and clock rise/fall time Offset, gain error, and nonlinearity introduced to the sampling Clock feedthrough can be simulated by SPICE, but charge injection cannot be simulated with lumped transistor models VDD 0 Vin+Vth Switch on Switch off Vout CS Zi Vin CgdCgs Qch </li><li> 34. Clock Rise/Fall-Time Dependence 34 Data Converters Switched-Capacitor Circuits Professor Y. Chiu EECT 7327 Fall 2014 VDD 0 Vin+Vth Switch on Switch off Vout CS Zi Vin CgdCgs Qch Clock feedthrough Charge injection Fast turn-off Slow turn-off gs DD gs S C V = - V C +C ox DD th in gs S C WL V - V - V V = - 2 C +C gs in th gs S C V = - V + V C +C V = 0 </li><li> 35. Dummy Switch 35 Data Converters Switched-Capacitor Circuits Professor Y. Chiu EECT 7327 Fall 2014 Difficult to achieve precise cancellation due to the nonlinear dependence of V on Zi, CS, and clock rise/fall time Sensitive to the phase alignment between and _ Vout W L CS W 2L Vin </li><li> 36. CMOS Switch 36 Data Converters Switched-Capacitor Circuits Professor Y. Chiu EECT 7327 Fall 2014 Very sensitive to phase alignment between and _ Subject to threshold mismatch between PMOS and NMOS Exact cancellation occurs only for one specific Vin (which one?) Vout CS Vin Same size for P and N FETs </li><li> 37. Differential Signaling 37 Data Converters Switched-Capacitor Circuits Professor Y. Chiu EECT 7327 Fall 2014 Signal-independent errors (offset) and even-order distortions cancelled Gain error and odd-order nonlinearities remain Balanced diff. input Vop CSp Vip M1 Von CSn Vin M2 </li><li> 38. Switch Performance 38 Data Converters Switched-Capacitor Circuits Professor Y. Chiu EECT 7327 Fall 2014 ch 2 ithDDox 2 ithDDox on Q L VVVWLC L VVV L W C 1 R S ch C Q 2 1 V Charge injection: Bandwidth: S 2 ch Son CL Q CR 1 BW 2 2 ch S S ch Q L CV 1 L = BW 2 C Q 2 Performance FoM: Technology scaling improves switch performance! On-resistance: </li><li> 39. Leakage in SC Circuits 39 Data Converters Switched-Capacitor Circuits Professor Y. Chiu EECT 7327 Fall 2014 I1 diode leakage (existing in the old days too) I2 sub-threshold drain-source leakage of summing-node switch I3 gate leakage (FN tunneling) of amplifier input transistors Leakage currents are highly temperature- and process-dependent; the lower limit of clock frequency is often determined by leakage Vo(t) 0 t 1 12 2 1 = high, 2 = low Vi Vo C2 C1 A0 Vx 2 2 1 1 VB I2 I1 I3 </li><li> 40. DS Leakage 40 Data Converters Switched-Capacitor Circuits Professor Y. Chiu EECT 7327 Fall 2014 M1 + Vi + Vo + Vo - Vi - CS + CS - VDD M1 - VDD 1 1e 1 1e 2 2 CS + CS - 2e 2e 0.13-m CMOS A0 = GmRo = 90dB Ro 2M Rleak 0.6V/3A 0.2M A0 = Gm(Rleak//Ro) 70dB OutIn M1 VDD Out In M3 M4 M2 M1 Ileak VDD = 1.2V VSS = 0V </li><li> 41. Gate Leakage 41 Data Converters Switched-Capacitor Circuits Professor Y. Chiu EECT 7327 Fall 2014 Direct tunneling through the thin gate oxide Short-channel MOSFET behaves increasingly like BJTs Violates the high-impedance assumption of the summing node GS ox GSI WL exp -t exp V </li><li> 42. Switch Size Optimization 42 Data Converters Switched-Capacitor Circuits Professor Y. Chiu EECT 7327 Fall 2014 To minimize switch-induced error voltages, small transistor size, slow turn-off, low source impedance should be used. For fast settling (high-speed design), large W/L should be used, and errors will be inevitably large as well. Guidelines Always use minimum channel length for switches as long as leakage allows. For a given speed, switch sizes can be optimized w/ simulation. Be aware of the limitations of simulators (SPICE etc.) using lumped device models. </li><li> 43. 43 Data Converters Switched-Capacitor Circuits Professor Y. Chiu EECT 7327 Fall 2014 Non-ideal Effects of Op-Amps </li><li> 44. Non-ideal Effects of Op-Amps 44 Data Converters Switched-Capacitor Circuits Professor Y. Chiu EECT 7327 Fall 2014 Offset Finite-gain effects (voltage dependent) Finite bandwidth and slew rate (measured by settling speed) </li><li> 45. Offset Voltage 45 Data Converters Switched-Capacitor Circuits Professor Y. Chiu EECT 7327 Fall 2014 1 i 1 o os 2Q = V n C + V n - V C 2 os 1 o os 2Q = -V C + V n+1 - V C -1 1 o i-1 2 C z V z = V z C 1- z Vi Vo C2 C11 2 2 1 Vos Vo(t) 0 t 1 12 2 Vi = 0 1 i o o os 2 C V = 0 V n+1 - V n = V C </li><li> 46. Autozeroing 46 Data Converters Switched-Capacitor Circuits Professor Y. Chiu EECT 7327 Fall 2014 1 i os 1 os 2Q = V n - V C - V C 2 os 1 o os 2Q = -V C + V n - V C o 1 i 2 V z C H z = = V z C Vi Vo C2 C11 2 2 1 Vos 1 Also eliminates low-frequency noise, e.g., 1/f noise A.k.a. correlated double sampling (CDS) </li><li> 47. Chopper Stabilization 47 Data Converters Switched-Capacitor Circuits Professor Y. Chiu EECT 7327 Fall 2014 Ref: K. C. Hsieh, P. R. Gray, D. Senderowicz, and D. G. Messerschmitt, A low-noise chopper-stabilized differential switched-capacitor filtering technique, IEEE Journal of Solid-State Circuits, vol. 16, issue 6, pp. 708-715, 1981. Vi VoA1 Vn 2 A2 fC 1 -1 A B </li><li> 48. Chopper Stabilization 48 Data Converters Switched-Capacitor Circuits Professor Y. Chiu EECT 7327 Fall 2014 Also eliminates DC offset voltage of A1 Vi VoA1 Vn 2 A2 fC 1 -1 A B |Vi|2 f 0 SN(f) f 0 f 0 |VA|2 |VB|2 f 0 fC fC fC fC </li><li> 49. Chopper-Stabilized Differential Op-Amp 49 Data Converters Switched-Capacitor Circuits Professor Y. Chiu EE...</li></ol>

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