losgcizamst,lwa

e

isitaoenas

tthd

ei

etenc

-ragefac-ere-d ahecesedine andionsnds

gu-

ingle

avesed

dataerehelane

edting

llelheer,ys

d

l

ershatne.byn.r tonts

ingrob- gridel-sign-ndcon-

CHIP-LEVEL AREA ROUTING

Le-Chin Eugene Liu Hsiao-Ping Tseng Carl Sechen

Department of Electrical Engineering, Box 352500University of Washington, Seattle, WA 98195

{lliu,hptseng,sechen}@twolf.ee.washington.edu

ABSTRACT

We present a chip-level area router for modern VLSI technogies. The gridless area router can handle any number of layerwell as rectilinear blockage areas on any layer. A two-stadivide-and-conquer strategy is applied so that the area router handle very large chips. The first stage includes an area-minimtion loop by using an efficient and accurate multi-layer globrouter. The global router minimizes the chip area while perforing the global routing. According to the global routing resultswitchboxes are generated for the whole chip area. Then switchboxes are sent to the second stage for detailed routingwhich a tile-expansion based switchbox router is used. With mulevel rip-up and re-route techniques, the detailed router is shoto be able to complete many difficult switchboxes. The router wtested on the MCNC building block circuits. Our results show bter chip areas than the best previously published results.

1. INTRODUCTION

An area-efficient, multi-layer, and gridless chip-level router presented in this paper. The gridless feature provides the requelements for attacking signal integrity problems, such as cross[4]. A timing optimizer can estimate the performance impact interconnect and convert the performance requirements into gmetric constraints (e.g. increased wire width and larger spacifor our gridless area router. In this paper, we mainly concentron the area routing problem. The previous work in the gridlearea routing domain and in the gridded area routing domainbriefed as follows.

Most of the area routers are maze-based routers. Without guidance of a global routing heuristic to evenly assign nets to routing regions, a pure maze router will usually fail to solve tproblem because some of the routing regions are too congestemaze router is limited to routing nets serially and does not haany sense of the global view. The previous area routing womainly falls into two groups -regional area routersand hybridarea routers. Regional area routers [5]-[22], which do not solvthe net congestion problem, are applicable to single routing regproblems such as the channel routing problem, the switch bproblem and the cell generation problem. Hybrid area rout[23]-[26], which distribute nets evenly into regions and alleviathe routing congestion problem, are applicable to multiple routiregion problems such as chip-level row-based circuits and blobased circuits. The previous work in these two groups are briedescribed below.

1.1. Regional Area RoutingGrid based implementations of maze routing algorithm

[7][17][20][21] have more flexibility to solve a general routing

g aazeivele-

-, aseana-l-,he inti-

ns

t-

redlkfo-g)tesis

hehee. A

verk

onoxrs

gk-fly

s

with obstacles problem than the switchbox routers [5][8][9]. However, the grid based data structure suffers from large data stocomplexity and requires search of a huge solution space when ing large circuits. These maze routers route nets serially and thfore need an extensive rip-up and reroute heuristic (usually callelocal modification) to reorder the nets in congested regions. Trip-up and reroute heuristics contribute further to the performanproblem. Line based approaches [13][14][15] have been propoto alleviate the storage complexity problem by using a simple lbased data structure, which consumes less memory spacereduces the search space. However, the simple path formatbased on lines means that an optimal path with minimum bemay not be found. An even more efficient data structure,cornerstitching, further reduces memory requirements by using rectanlarly shaped tiles to represent layout components and spaces.

Previous approaches [10][16][22] based on the corner stitchdata structure enjoy the most flexibility in design rules - variabwire width and variable wire spacing. The tile based routers hthe potential to handle a larger problem size than the grid-barouters because of the efficient data structure. Margarino,et al. [10]first implemented an area router based on the corner-stitching structure. However, all the routing layers and the contact layer wcombined into a single tile plane, which is highly segmented. Tbreadth first maze router searches for paths on the single tile pfor a restricted wiring style. Tsai,et al. [16] improved the algorithmby using one tile plane per routing layer. An A* algorithm basmaze router was developed to route nets in a restricted roustyle. The routing of a multi-terminal net is done by anet-foresttechnique, which expands the paths from each terminal in paratoward the center of mass. Dion and Monier [22] improved tmaze router by using a bi-directional A* search heuristic. Howevthe path found by their bi-directional search heuristic is not alwaoptimal. An admissible bi-directional A* algorithm certainly coulachieve better solutions.

1.2. Hybrid Area RoutingPrevious routing frameworks [6][23]-[26] that include a globa

routing feature to reduce congestion are calledhybrid area routersand are capable of handling chip-level circuits. Hierarchical rout[6][25] route nets on the grid plane in a hierarchical way such tthe initial routing path is searched for on a very coarse grid plaIn the next iteration, the routers try to refine the routing path using a grid plane with half the grid size of the previous iteratioHierarchical routers have an advantage in using one single routecomplete a large routing problem. However, the path assignmein the early routing iterations are based on very rough routcapacity estimations and often cause subsequent routability plems. A mechanism to backtrace path assignments to a coarserplane is required when routing failure occurs. Lunow [24] devoped a three-stage router - a grid based global router, a track asment detailed router, and a local modification and rip-up areroute stage. However, its global router does not consider the gestion problem. Codar [23] is a grid based maze router featuringlobal router based on a coarse grid map and a grid based mrouter with a fast pattern-based local modification and a recursrip-up and reroute heuristic [27]. However, the grid-based impmentation limits the problem size that it can handle.

sek

tiis

t onoansouoleeT

ii a ste

-

i)

i

on-raphtic.ibeed

re.reaion) oncute a

y vianect

thetheodes. thely beown

eng.hetheare solid in

ateme

ple.ells. andearlace wem of thetan-s of/sink. Toente isg toyerightigh-mn.

We developed an area routing system aiming to solve the chlevel routing problem without the limitations of the previouapproaches. An example of the routing problem for chip-levblock-based circuits is shown in Figure 1. The functional bloc

(building blocks) can have any shape and any size. The rouregions are between blocks and over the blocks. The objective complete the routing of a building-block circuit while minimizingits core size.

To solve the routing problem for block-based circuits, we builrouting system featuring three stages - Steiner tree based glrouting, switchbox generation, and tile expansion area routiThe program flow is shown in Figure 2. Given a placement macro cells (or building blocks), the chip area is divided into smregions by cut lines which are the extension lines of the bouaries of the blockage areas (usually the cells) on all layers (Figure 4 or the dashed lines in Figure 3). If two cut lines are tclose to each other, the two cut lines are merged. The global rofirst finds the rough path for each net based on this meshed glrouting cell plane. Given the information on which nets shoupass through a global routing cell, the switchbox generation hristic generates a single switchbox for each global routing cThe detailed router then processes one switchbox at a time. final routing of an entire chip is obtained by merging the resultsall the switchboxes.

The rest of the paper is organized as follows. Section 2 explaour global routing architecture and how we minimize the charea. Section 3 describes the interface between global routingdetailed routing. A set of Gboxes (switchboxes) are generatedthe detailed router to perform the final routing. Section 4 discusthe detailed routing algorithm. Section 5 shows experimenresults for the benchmark circuits. Section 6 concludes the pap

2. GLOBAL ROUTING/AREA MINIMIZATION

Our area routing algorithm can be divided into two stages global routing and detailed routing. For the global routing, wextended the global router introduced in [1]. The global routerfor multiple routing layers with rectilinear blockage areas. Typcally, the blockage areas are the macro cells (or building blocksthe layout. Other examples are pre-routed areas or reserved aon the higher routing layers.

The routing architecture is constructed by first dividing the ch

blk1

blk4

blk5

blk2

blk3

pad1

pad2pad3

pad4

pin

inter-blockconnection

A

A

Figure 1: Chip level area routing problem

Figure 2: Flow of our routing system

Global routing region definition

Generate Steiner minimum length trees

Congestion removal

Switch-box generation

Detailed switch-box routing

Global Routingor area minimization

or crosspoint assignment

ip-

ls

ng to

abalg.flld-eeoterbaldu-ll.he

of

nspnd

foresalr.

--eis- inreas

p

area into small routing regions. Then, a global routing graph is cstructed. The global route for each net is searched for on the gunder certain criteria by using an improved Steiner tree heurisWe next briefly review the routing architecture, and then descrthe crucial modifications to the global router in [1] that were needfor its use in chip-level area routing.

2.1. Routing architectureA brief review of the routing architecture is presented he

Given a placement of macro cells (or building blocks), the chip ais divided into small regions by cut lines which are the extenslines of the boundaries of the blockage areas (usually the cellsall layers. If two cut lines are too close to each other, the two lines are merged. To construct the global routing graph, we placnode on each layer in every region. The nodes are connected bedges, horizontal edges, and vertical edges. The via edges connodes on different layers. The horizontal/vertical edges connectnodes on the layer used for horizontal/vertical routing. Inside blockage areas, there are no connecting edges between the nIn addition, the connecting edges across the boundary betweenblockage and outside areas are directed. Those edges can onused for the signals to exit the blockage areas. An example is sh

in Figure 3. This example is for two routing layers, in which thfirst one is for horizontal and the second one is for vertical routiThe first layer is not available inside the cells for routing. On tother hand, the second layer (vertical layer) is available inside cells, i.e. it does not have any blockage areas. The cut lines shown as dashed lines in the example. The nodes are the smallsquares. The 3-dimensional global routing graph is also shownthe example.

2.2. Chip size estimateThe global router uses two directed graphs to accurately estim

the chip size. The chip’s height and width are calculated the saway. We use the calculation for the chip’s height as an examFirst, nodes are placed on the top and bottom sides of the cTherefore, a rectangular cell has one node on the top boundaryone node on the bottom boundary. For non-rectangular rectilincells, there may be more than one top or bottom boundary. We pone node on each horizontal boundary segment. In addition,have one source node on the top and one sink node at the bottothe chip. The height graph is directed from the source node tosink node. Since the routing model divides the chip area into recgular regions, we have columns, which may consist of a serieregions, between the cells or between the cells and the sourcenode. In Figure 4(a), the columns are shown by the directed arcssimplify the graph, only one directed edge is needed to represthe columns between any pair of nodes. The weight of the edgdetermined by the highest column of the columns correspondinthe edge. The height of a column is decided by the horizontal lathat requires the most space. Figure 4(b) shows the final hegraph. For illustration purposes, we placed the edges into the hest columns between the nodes, if there is more than one colu

Figure 3. Example routing graph with cut lines

.

. o

r

thba

ios seira

eueen ttit

r

ic

na

iri

tionom-rea.n-

ged.ed.ngefectses iser-m

ti-tionlls tothea-ver,tingnimi-ndtable

thanndi-er-llynt

ver- final this the

Thegirem-

bal ofobaleen ofForthend

ngle

aintthe

uityes,the an

However, they actually represent a set of columns. Inside the ceeach node on the top has an edge to each node at the bottomweight of such an edge is the distance between the boundariesa rectangular cell, it is the height of the cell. The longest path frsource to sink determines the height of the chip.

The width is calculated the same way. The only differencethat the edges go horizontally. The estimated chip area is the puct of the chip height and width.

2.3. Area minimization routingTo minimize the chip area, we try to reduce the height and

width of the chip sequentially. The size of the chip is decided the longest paths in the height and width graph. The longest pcorresponds to the sum of the sizes of a series of routing regand some cells. Since the size of the cells is fixed, the only poble way to change the size of the longest path is to change theof the routing regions. The size of the routing regions is detmined by the number of routes using the regions. Those routregions in the longest path are called “critical regions”, which asimilar to the “dominant tiles” in [30]. We re-route those nets thuse the critical regions during the area minimization routing.

To reduce the height and width of the chip, we re-route the nin the critical regions to see if there is a new route that can redthe size of the critical regions. In particular, we dynamically sthe weights of graph edges in critical regions and reroute the nAn edge’s weight is set to infinity if the use of the edge does reduce the size of the critical region. If such a new route exists,new chip size is calculated according to the route change. If chip size is reduced, the new route is accepted, otherwise rejected. The algorithm is as follows:

1. for (all nets in the critical regions) {2. try to find a new route which reduces the size of

critical regions/* Set the weights of the edges in critical regions to infinity because the use of those edges don’t reduce the size of critical regions */

3. if (no such a new route exists) continue4. if (the new route does not increase the weight

and reduces the chip size)accept the new route and continue

5. if (the new route increases the weight)put the new route in a priority queueaccording to the increase of the weight

6. }7. for (each new route in the priority queue in order)8. if (the new route reduces the chip size)

accept the new route

The re-calculation of the chip size is key to the effectivenessthe algorithm, because a new route which reduces the size of ccal regions may not reduce the chip size. Besides, new critregions can be generated when a new route reduces the origcritical regions. The above algorithm has another feature. It mimizes the wire length increase while minimizing the chip areThe re-routing process can also be repeated many times to achbetter results. A greedy approach is to repeat it until no further sreduction is possible, i.e. no new route is found or accepted duthe iteration.

Figure 4. graphs for the example in Figure 3

(a) column graph (b) height graph

lls, TheForm

isod-

eythnssi-izer-nget

tscetts.othehe is

ofiti-alinali-.

ievezeng

2.4. Area minimization loopThe above area minimization routing is based on the assump

that the macro cells can be pushed away from each other to accmodate more tracks or pushed closer to reduce the required aThis assumption is true for one dimension but not for both dimesions. After the width is reduced, the placement has been chanIt may not be possible to reduce the height as previously assumIn addition, to reduce the chip area, the placement has to chaaccording to the routing results. The placement change may afthe global routing. The original global routing results may losome accuracy. From the above analysis, an iterative procesapparently needed for solving the problem. We used the TimbWolf chip area compactor to work with the global router to perforthe area minimization.

After the area minimization routing, the global router can esmate the required routing area between the cells. This informais passed to the compactor. The compactor moves the macro ceminimize the chip area. We do not allow the compactor to move cells far away from their original positions. The topological reltions between the cells are retained during the process. Howethe original placement may have changed, and the global rougraph may have changed as well. In such a case, a new area mization routing is performed. The area minimization routing acompaction process is repeated until the chip area reaches a spoint. The whole algorithm can be demonstrated as follows:

1. The global router performs area minimization routing.2. The compactor moves the cells.3. If the area does not converge, go to step 1.4. The global router performs congestion removal routing.

When the chip area change between the iterations is smaller a certain percentage of the whole chip area, the convergence cotion is satisfied. According to the experimental results, the convgence usually occurs within five iterations. Placement is usuadone under the minimum-wire-length condition. If the placemewere done under the same minimum-area condition, the congence would happen faster. When the chip area converges, theplacement is fixed. The macro cells can not be moved, becauseis the placement for minimum chip area. Hence, the last step ofalgorithm is to solve any possible congestion problems.

3. GBOX GENERATION

3.1. IntroductionThe global router decides which regions a net goes through.

global routing results provide routing information for each routinregion. For each routing region, there is a list of nets that requtracks in the region. We also know the directions that a net is coing from or going to in a region. Since the three-dimensional glorouting graph mimics the multiple routing layers, the knowledgelayer usage for each net in each region is also included in the glrouting results. Since we know the nets on the boundary betwtwo routing regions, we only need to know the exact positionsthe nets on the boundary in order to construct a switchbox. multi-layer routing, the routing regions are more general than traditional switchboxes. The routing regions can have pins ablockage areas anywhere in the region. We call such a rectawith fixed pins and blockage areas aGbox (global routing box).Each routing region corresponds to a Gbox. There is a constrbetween adjacent Gboxes, namely that the pin locations on common boundary have to be consistent. Otherwise, the continof the signals will be lost. Figure 5(a) shows the notion of Gboxand two of them are shown in the callout. The pin locations on common boundary are exactly matched. Figure 5(b) shows

egeoe

t

hs

nva

e

oriniose

a

hn

thatw

y

theocus

wolgo-le, as the

Theonse 7,

al side

innettotomr-

t Bpinre,ore

toon-eg-ut-

inggatesut- foruen-the

pin theosi-an

line

ulthe

example when the routing is completed inside the two Gboxes.

3.2. Basic conceptsA few terms are defined here. First, we divide a route into s

eral segments. A segment is the maximum continuous routinregion span of a net’s global route on a column or a row. Figurshows an example. The dashed lines are cut lines. The thin slines are part of the routing graph. A global route and the cboundaries are shown as thick solid lines. There is a two-pin nNetA, between two cells. The pins are shown as dots, and nodes that the pins are mapped to are shown as solid squares.NetAis routed through a series of regions. The optimal condition is tNetA has two horizontal tracks, one vertical track, and two viaTherefore, the route consists of three segments. Segments A aspan two regions horizontally. Segment B spans three regions tically. According to the definition of a segment, all the globroutes are decomposed into a set of segments.

A segment that contains one or more pins is called apin seg-ment. For example, in Figure 6, segmentsA and C are pin seg-ments. If a net passes through a routing region, the net is callpass-through net in that routing region. For example, segmentB ofNetA spans three regions: (i,j-1), (i,j), and (i,j+1 ). However, it onlypasses through the middle region, (i,j). Therefore, in region (i,j),NetAis a pass-through net.

The task for generating a Gbox is to assign the exact positifor each net in the routing region. The exact positions are repsented by the pins of a Gbox. A pass-through net of a routregion crosses the opposite boundaries of the routing regTherefore, a pass-through net requires two pins on the oppoboundaries of the corresponding Gbox. A Gbox is complete whall the nets using that routing region have pins completeassigned. The detailed router will decide which actual tracks used inside a Gbox.

Two requirements must be satisfied for constructing tGboxes. The first one is retaining signal continuity. The secoone is making the Gbox feasible for detailed routing,i.e. all netshave to be connected without design rule violations. To satisfy first requirement, we make sure that a signal’s pins have the sposition, including the layer usage, on the shared boundary of adjacent Gboxes. This is also the first constraint for Gbox genetion. The second requirement partially depends on the accurac

Figure 5. Illustrations of Gbox routing

(a) before routing (b) after routing

Figure 6. Example of a route and its segments

NetA

NetA

AB

C

(i,j+1)

(i,j)

(i,j-1)

v-

6lidllet,he

at.d Cer-l

d a

nse-gn.iten

lyre

ed

emeo

ra- of

the global routing. Since the global router is good at estimating routing resources needed, in the Gbox-generating stage, we fon minimizing the required routing resources for every Gbox.

In order to minimize the routing resource usage, we use tessential concepts for assigning the pin positions. First, our arithm keeps the segments as straight as possible. If at all possibsegment is mapped to a single track. It means that a segment hasame pin positions in all the Gboxes that the segment spans.implementation of this concept is to assign the same pin position the opposite boundaries for the pass-through nets. In Figur(a) is the optimal result and (b) is a worse result. The non-optimcases happen when the corresponding position on the oppositeis not available.

Second, our algorithm reduces the number of jogs neededdetailed routing. In Figure 7(c), net A has three fixed pins, and B has two floating pins. If the pin of net B on the right side falls inthe interval between the dashed lines, the pin of net B on the botside will have to be on the right side of net A’s vertical track. Othewise, an extra vertical track (jog) would be needed for routing neas illustrated in Figure 7(d). Our program tries to assign net B’s on the right side to a position that is out of the interval. Therefothe assignment for net B’s pin on the bottom side can have mfreedom.

3.3. Segment-positioning algorithmBased on the above two concepts, we developed the algorithm

generate the Gboxes. Unlike some other Gbox-by-Gbox (regiby-region) algorithms, our algorithm is based on segments. A sment-based algorithm yields better global optimization on the roing resource usage.

The position of a segment is first decided in one of the routregions that the segment spans. The same position then propathroughout the whole segment. From the global routing, every roing region has a list of nets that need to be routed in the regioneach layer. The program assigns the positions for the nets seqtially in a region. The order of the nets is decided according to features of the corresponding segments. Here is the algorithm:

1. for (each net) {2. assign positions for pin segments3. }4. build priority queue for the routing regions5. build segment preference data6. for (each region in the priority queue) {7. assign positions for the pass-through nets with preference8. assign positions for the non-pass-through nets with

preference9. assign positions for the pass-through nets without

preference10. assign positions for the non-pass-through nets without

preference11.}A net’s pins on the macro cells have fixed positions. Since a

segment contains pin(s) of the cells, it is reasonable to assignpin segments first. Assigning a segment means deciding the ptions of the Gboxes’ pins on the Gbox boundaries within the spof the segment. Our algorithm always tries to assign a straight-position for a segment unless there is a conflict.

The next step is to assign the segments in the most difficregion for routing. We have a cost function to determine tsequence in which the regions are processed.

Cost = number_of_potential_jogs + congestion_condition

AB

B

A

A

Figure 7. Connection examples

A

B

B

A

A(c) jog (c) no jog(a) optimal (b) worse

riateh

ning t-esi

hr

tio

id

a feet

t

b. svnee

fnw

s

ee

ai

u

A

angn-lo-

saryas

ts,

rea aelti-ide in

ata

s invale

ori-al

atd V

Hrip)n-e in

s -

ms

etal tod

Ourilesas

It is obvious that a crowded region should be processed befosparse region because the routing resources are more constraThe congestion_condition in the cost function is equal to 2 for over-congested region, and 1 for a full region. An over-congesregion has more tracks than it can accommodate. A full region exactly the same number of tracks as its capacity allows. Tcongestion_condition is 0 for all other regions. Another importafactor is the number of potential jogs. After Line 3, only the psegments are assigned. Many of the segments are still floatinwe can identify where the potential jogs may occur and assignsegments properly to prevent jogs from happening, the overrouting resources needed will be reduced. When the pin segmare assigned, we have fixed pins in the Gboxes that the pin ments span. If two pins belonging to two nets on the opposboundary have conflicting positions, a jog may be needed. Tpotential jogs are counted and included in the cost function.there is a tie for the cost, the number of floating tracks is usedbreak the tie. That is, a region with more floating tracks has higpriority. Line 4 uses the above cost function to decide the ordewhich the regions are to be processed.

In the loop of lines 6-11, the regions are processed one by oProcessing a region is to assign the position for each net in region. The program first assigns a net to a position in a regThen, the program assigns the same position to the whole segmunless there is a conflict. Therefore, the position has to be decby the features of the whole segment and not by the relationsthe nets in a local region.

One important feature of the segments is the preference dThe preference data is used to reduce the total wire length andnumber of potential jogs when assigning segments. The preence of a horizontal segment is decided by the number of the vcal segments connected to the horizontal segment. Similarly, preference of a vertical segment is decided by the number ofhorizontal segments connected to the vertical segment.

Figure 8 shows three examples for a vertical segment. The in the examples is the region that is currently being processed(a), there are two segments connected to the left side and onement to the right side. The preference is therefore to place the tical segment near the left side of the Gbox. In (b), there is preference for the vertical segment. In (c), the vertical segmprefers the right side because there are more horizontal segmconnected on the right side.

Line 5 calculates the preference for the segments. The preence data are used in the loop in Lines 6-11. In the loop, those (segments) with preference are processed before those nets out preference. The nets are divided into two groups accordingthe preference data. Among each group, the pass-through netassigned first. Pass-through nets need two pins on the oppoboundaries. The positions of the two pins have to be the samorder to have a straight line connection. The more restricted nare processed first so that they can have more freedom.

After all regions have been processed, the Gboxes are generaccording to the assigned positions. For a Gbox, the cells’ pand blockage areas are placed first. Then, the cross points (pon all the boundaries are placed to complete the Gbox. TGboxes are then passed to the detailed router. The detailed rodetermines the final routing inside the Gboxes.

Kao [31] developed a switchbox crosspoint assignment (CP

Figure 8. Segment preference

(a) (b) (c)

e aned.nd

ashet

. Ifheallntseg-teheIf toerin

ne.hen.ented

of

ta.ther-

rti-hehe

ox Ineg-

er-ontnts

er-etsith- to aresite ints

tednsins)heter

)

heuristic for two-layer gate-array gridded routing. It features iterative global re-routing during CPA stage when the linear assiment CPA heuristic cannot resolve overcongestion. Since our gbal router accurately estimates routing capacities, it is not necesto apply global re-routing during the CPA stage. Kao’s system wlimited to two-layer routing, was not tested on macro cell circuiand did not address area reduction.

4. DETAILED ROUTING

Gbox detailed routing is accomplished by a robust tile-based arouter which has a multi-level rip-up and reroute strategy androuting window control to improve the routability. We describe thframework of the tile-based router in section 4.1, and the mulevel rip-up and reroute strategy in section 4.2. Heuristics to decthe routing order and the routing window control are presentedsection 4.3 and section 4.4, respectively.

4.1. The Tile-based Area Routing FrameworkOur detailed area router is based on the corner-stitching d

structure. The corner-stitching data structure has advantageretrieving the local geometric information and the space interinformation. It was introduced by Ousterhout [28]. Tiles on thplane are stitched and combined either into strips of maximal hzontal extent called a horizontal (H) tile plane or strips of maximvertical extent called a vertical (V) tile plane.

A special technique to mirror the coordinates of an H tile plane45 degrees can produce a dual V tile plane. The coupled H antile planes are called theDual Tile Plane (see Figure 9(b), (c)). A Vtile plane on coordinate (x, y) is actually an implementation of anplane on the reflected coordinate (y,x). The maximal H (V) sttiles on the H (V) tile plane allow fast tile expansion in the H (Vdirection. It extends the horizontal routing efficiency of the convetional single tile plane to both directions of tile expansion. Wexplain the tile expansion patterns and the searching algorithmthe following paragraphs.

Our tile expansion router essentially takes two routing patterna metal expansion model and a via expansion modelto find a feasi-ble route with minimum cost using an admissible A* algorith[29]. Themetal expansion model is applied when the routing path iexpanded on the current metal layer. Thevia expansion model isapplied when the routing path is expanded to the adjacent mlayer. Our expansion models allow unrestricted layer routing - HV, H to H, V to H and V to V. The cost function weighs expandecomponents, such as a space tile, via, or metal wire, differently. algorithms also extend the search path through existing solid twith different signals. An efficient rip-up and reroute heuristic hbeen developed to clean up overlapped wires.

(b) Horizontal tile plane (c) Vertical tile plane

1

12

21

12

2

Metal 1 Layer by D1H Metal 1 Layer by D1V

Metal 2 Layer by D2H Metal 2 Layer by D2V

1

12

2

(a) a two-layer

xy

xy

yx

yx

layout example

Figure 9: Dual tile plane representation

o

inrp

zhth

s o

h

e

nv

vu

e

en

ivRe

ter

lockwill

en-nalusg

iatevelansithteenet

plen abor-zeriesas

eryere ourn-s aste

g-Fig-

4.2. Multi-level Rip-up and RerouteThe rip-up and reroute (RR) algorithm allows the expansi

path to overlap with anon-equivalent solid tile which has a differ-ent signal than the current net being routed. To form the routpath on the selected non-equivalent solid tile, the center of its oinal shape is used as the alignment to shape the new routing and to meet design rules. By applying thisoverlapped tile expan-sion feature, a feasible optimal route is always found with a minmum of overlapping with non-equivalent solid tiles by the marouter. The router first rips up those two-pin nets which own toverlapped non-equivalent solid tiles, draws the new route for current net, then continues this rip-up and reroute process those ripped up overlapped nets. A multi-level control mechanideveloped to optimize this process is described in subsectionSubsection B shows the difference and the improvement of new rip-up and reroute strategy from previous work.

A. Multi-level Rip-up and RerouteTo prohibit nets from being cyclically thrashed out by eac

other in congested Gboxes, a multi-level control mechanism wimplemented. Thelevel of rip-up and reroute is defined as thnumber of subsequent times that the rip-up and reroute procedwill be executed recursively. A feasible route found at a leveli RRprocess is denoted as atentative route. A tentative route in thelevel 0 RR process is not allowed to overlap with non-equivaletiles, since no subsequent rip-up and reroute executions are aable to remove overlaps. The leveln RR process for nodep isaccomplished by the following procedures - (1) find a tentatiroute, (2) remove nets which own the overlapped tiles on the ro(3) draw the route, (4) run a leveln-1 RR process for the removednets, (5) if any net in step 4 fails, collect thefailed solid tilesowned by the failed nets, and (6) call procedure 1 withn = n-1 andwith the failed solid tiles not being allowed to be expanded.

A multi-level rip-up and reroute tree (MRRT) is constructed toshow the hierarchical relation of nodes in different RR levels (sFigure 10). Netp is processed in the leveln RR process and is per-mitted to findRtpossible (overlapped or non-overlapped) tentativroutes. Tentative routert of net p hasNrt overlapped nets. Themthoverlapped net (m [1, Nrt]) on the routert of nodep is denotedas net(rt, m) in the leveln-1 RR process. If neti is prior to netjand neti is on the path to netj in theMRRT, neti is anancestor tonet j and netj is adescendent to neti in the RR process. A tenta-tive route with a largeNrt tends to be more costly due to the moroverlapping with existing nets and usually has a longer path thatentative route with a smallNrt. In order to control the computa-tion time and to obtain better results, a limited number of tentatroutes (Rt=4) are considered for each net at each level of the process. In our experiments, most of the Gboxes need only a l0-2 RR process.

B. Comparison with Other Recursive Strategies

The recursive rip-up and reroute strategy has been implemenby Poirier [27] for the cell generator EXCELLERATOR (EXCEL

∈

netp

Leveln RR Leveln-1 RR

net (0,0)

net (0,N0-1)

Leveln-2 RR Level 0 RR

net (i,0)

Rip-up andreroute nets

Route (0)

Route (Rt-1)

R(0)

R(0)net (0,1)

net (i,1)

net(i,Ni-1)

Possible

Route (1)

R(Rt0,0-1)

n(0,0)n(0,1)

n(0,N1-1)R(i)

reroute only routes

Figure 10: Multi-level Rip-up and Reroute Tree

n

gig-ath

i-eee

formA.ur

as

ure

tail-

ete,

e

e

a

eRvel

ted

in short). Instead of resolving the conflicts (overlapping wires) afcompleting the current route of netu, EXCEL tries to resolve theconflict on gridk on the expansion tree whenever gridk is owned byan existing net (sayv). The rip-up and reroute process for gridk isrecursive and the traversed nodes of the top-level netu are frozenand treated as obstacles. The frozen nodes unnecessarily bpotentially better routes, since not all the traversed nodes appear on the final optimal path of netu. The attempt to immedi-ately resolve the conflict of every overlapping node is very expsive, since not every overlapping node will appear on the fioptimal path of the top-level net. His implementation is analogoto our MRRT at Rt=1 and only searches a subset of our routinsolution space (see Figure 11). Another drawback of the immedconflict resolution is that each conflicting node at the topmost leis resolved independently of other resolving attempts. That methe new path found for each conflicting net may be overlapped wthe new path of some other conflicting net. There is no guaranthat those conflicting nets on the optimal path of the topmost can be all successfully rerouted.

4.3. Net Ordering and Routing EnhancementsIn a chip-level circuit, most nets are long and go across multi

Gboxes. We observe that most wires go straight without jogs. Icongested region, a jog may cause a ripple effect to push neighing wires away and therefore degrade routability. To maximistraightened wires, nets with their two pins at opposite boundaand at the samex or y position are routed first using zero bends shown in Figure 12(i).

In some of the tested benchmark circuits, we encountered vlarge switchboxes. Several pruning and trimming techniques wdeveloped to route Gboxes as large as 2000x2000 tracks. Sinceswitchbox generation algorithm creates very few vertical costraints, most nets are connected using small numbers of bendshown in Figure 12(i)-(iii). The maximum number of bends to rounet n is denoted asmax_bend(n). If existing wire overlappingsblock the minimum bend solution, a minimum bend plus one-doleg solution may be feasible for most of the cases as shown in

Net i

n0

n1

nN

•••

•••

•••

Conflictinggrids Rip-up

Reroute

•••

Conflictinggrids Conflictinggrids

•••

•• •

Rip-upReroute

Figure 11: Call graph of Poirier’s recursive approach

Figure 12: Nets are routed using minimum bends andan additional jog (numbers shown are the bend counts)

(iii) 2 (vi) 4(ii) 1 (iv) 3(i) 0 bend (v) 4

1)Route net n with max_bend(n)=0, branch_max (n)=L2)Route net n with max_bend (n)=1, branch_max (n)=L3)Route net n with max_bend(n)=2. branch_max (n)=L

Should it fail, route n with branch_max (n)=4)Route the failed nets in (2) with max_bend(n)=3, branch_max(n)=L5)Route the failed nets in (1) with max_bend(n)=4, branch_max(n)=L6)Route the failed nets in (3) with max_bend(n)=4, branch_max(n)=L7)Route all the failed nets with max_bend(n)=4, branch_max (n)=L8)Route all the failed nets with max_bend( n)= , branch_max (n)=

Figure 13: Net routing ordering

∞

∞ ∞

yyensi

dinu

wil4

s

d

o

i

hou

r3 ga

i[a

a t

l

s

Foriledxitym-itsoretime

igh, itlo-c-

ng atiledete of

or ofgiesnd

owsrea to

ay-i33,

vely

ure 12(iv)-(vi).In a tile plane ofNxN tracks (representing a Gbox), a tile ma

generate as many asN nodes to the adjacent layers. Essentiallmost of these nodes can be pruned in finding the minimum bsolution and the minimum bend plus one-jog solution. The becontrol limit provides an upper bound of the tile expansion coAny routing solution using the required number of bends accepted. For each via expansion, only at most theL(branch_max(n), e.g. 10) least cost nodes are selected amongthe possible generated nodes and the rest of the generated nodthis expansion are deleted. The net routing order is describeFigure 13. Note that from step 1 to step 7 only non-overlapproutes are allowed and overlapping routes using rip-up and reroare allowed only in step 8.

4.4. Routing Window ControlWhenever a net fails to be routed inside a routing region,

increase the size of the routing window to accommodate the fanet in the neighboring routing regions. As shown in Figure 1

there is a routing window increasing pattern for each one of routing failures. Assume in regionR, the failed nets are {n1, n2,...}and their window-increasing patterns are {WIn1, WIn2,...}. Thewindow-increasing control for regionR is then to increase thewindow size by one Gbox for each of the directions representeWIR = (WIn1 WIn2 ...). Our router then routes the failednets inside the increased regionWIR. If the window-increasingeffort WIR doesn’t completely route all the failed nets, the window-increasing control is applied recursively (by one more Gbin each of the relevant directions) until all nets are completerouted. To control computation time, the recursion is limited tolevels. Our observation is that any resulting failed nets requfloorplan modification and cannot be resolved manually.

5. RESULTS

We tested our area router on the MCNC building-block bencmark circuits. We used five benchmark circuits: hp, apte, xerami33, and ami49, since those circuits have been used previo[2][3]. In [2], it was shown that TimberWolfMC (the placer andglobal router) and TimberWolfDR (the detailed router) outpeformed all other placement and routing tools at that time. [showed that the Branch-and-Bound placement algorithm couldeven better results than TimberWolfMC. A commercial router wused to finish the routing. In our tests, the placement was doneTimberWolfMC Version 3.1. It is basically the same placer used[2]. So we got about the same quality placement as those in However, our new area router is able to minimize the chip area very effectively finished the tight space routing. Although ouplacement may not be as good as those done by the Branch-Bound algorithm, the final chip areas are better. Table 1 showschip area comparison results. Our results are better than Branch-and-Bound results for every benchmark circuit. Especiafor the largest circuit, ami49, which has 49 blocks and 408 nethe area is reduced by 6.8%. The CPU time for global routing a

Figure 14: Increase the size of the routing windowby one additional Gbox in the directions shown for each of the

types of failed nets

(i)

(ii)

(iii)

(iv)

(v)

(vi)

∪ ∪

,nddt.s

alles of ingte

eed,

ix

in

-xly2re

-x,sly

-]ets byn2].ndrnd-hethelyts,nd

ix

detailed routing is collected from a PentiumPro 200 machine. ami33, our global router takes longer time to finish than the detarouter because the number of cut lines is large (the time compleof global routing is increased) and Gboxes are small (the time coplexity of detailed routing is decreased). On the contrary, circuxerox and ami49 have a small number of cut lines and therefGboxes are comparably large. Our detailed router takes longer in these two cases than the global router.

Table 2 shows the completion rate for the routing. The very hcompletion rate for the initial routing has three meanings. Firstindicates that the global routing is very accurate. An inaccurate gbal routing would cause great difficulties for detailed routing. Seond, our Gbox-generation algorithm is able to minimize the routiresources required. Third, our detailed router is very effectivehandling crowded routing regions. The effectiveness of our detarouter can be further shown in the final results. After the incomplrouting regions were merged with their adjacent regions, 100%the nets were completely routed.

Figure 15(a) shows the routing result of circuit ami49 using twmetal layers. Our area router is capable of handling any numbelayers. To demonstrate this capability, we changed the technoloused for the benchmark circuits from two layers to four layers, awe applied our router to the same circuits again. Figure 15(b) shthe four-layer routing result of circuit ami49. Table 3 shows the areduction results by changing the technologies from two layersfour layers.

The area reductions are limited by the fact that, even for two lers, the chip areas are dominated by active cell area. Circuit amhowever, had a large 21% area reduction since it had a relatilarge amount of routing space for two layers.

Circuit

TWMCTWDR

B.B. +comm. D.R.

TWMC + new area router

area area area CPU (secs)global rout.

CPU (secs)detailed rout.

hp - 12.15 12.12 32.6 240apte - 54.05 53.71 23.6 73

xerox - 26.17 26.16 8.5 5454ami33 2.57 2.24 2.23 1246.2 244ami49 - 51.49 47.97 459.6 3426

Table 1. Chip area comparison

Circuit# of

Gboxes

# of 2-pin nets

inGboxes

before merging, in terms ofafter

merge# of Gboxes # of two pin nets

hp 204 > 1,460 100% 100% 100%apte 152 > 2,170 100% 100% 100%

xerox 217 > 920 97.24%(6 failed) 99.72%(6 failed) 100%ami33 681 > 2,570 97.06%(20 failed) 99.07%(24failed) 100%ami49 2,856 > 13,150 99.47%(15 failed) 99.86%(18failed) 100%

Table 2. Completion rate of Gbox routing

Figure 15: AMI49(a) two-layer (b) four-layer

osotima

ms

t

uiu

e-v

n

n

”

,

n

n

r-

als ofn

-d-

ek-

H-

e-

a

an

I.p.

drch

tedal3,

-p.

ths

ln

g

6. CONCLUSION

We presented a chip-level area router for modern VLSI technogies. The gridless area router can handle any number of layerwell as rectilinear blockage areas on any layer. A divide-and-cquer strategy is applied so that the area router can perform rouon a very large chip area. The first stage includes an area-minzation loop by using an efficient and accurate multi-layer globrouter. The global router minimizes the chip area while perforing the global routing. According to the global routing resultGboxes are generated for the whole chip area. Then the Gboare sent to the second stage for detailed routing by means of aexpansion based router. With multi-level rip-up and re-route tecniques, the detailed router is able to complete many difficGboxes. The router was tested on the MCNC building block ccuits. Our results show better chip areas than the best previopublished results.

REFERENCES

[1] L. E. Liu, “Global Routing and Pin Assignment for Multi-layer Chip-level Layout,”Ph.D. Thesis, University of Wash-ington, Seattle, Nov. 1997.

[2] W. Swartz and C. Sechen, “New Algorithms for the Placment and Routing of Macro Cells,” IEEE International Conference on Computer Aided Design, pp. 336-339, No1990.

[3] H. Onodera, Y. Taniguchi, and K. Tamaru, “Branch-andBound Placement for Building Block Layout,” 28th ACM/IEEE Design Automation Conference, pp. 433-439, Ju1991.

[4] H. P. Tseng, “Detailed Routing Algorithms for VLSI Cir-cuits,” Ph.D. Thesis, University of Washington, Seattle,Nov. 1997.

[5] Lyle R. Smith,et al, “A New Area Router, The LRS Algo-rithm,” Proceedings of IEEE International Conference oCircuits and Computers, pp. 256-259, 1982.

[6] M. Burstein and R. Pelavin, “Hierarchical Wire Routing,IEEE Transactions on Computer-Aided Design, Vol. CAD-2, No. 4, pp. 223-233, October 1983.

[7] Hyunchul Shin and Alberto Sangiovanni-Vincentelli“MIGHTY: A ‘Rip-up and Reroute’ Detailed Router.” Pro-ceedings of IEEE International Conference on ComputeAided Design (ICCAD), pp. 2-5, 1986.

[8] J. M. Jou,et al, “A New Three-Layer Detailed Router forVLSI Layout,” Proceedings of IEEE Int. Conference oComputer-Aided Design (ICCAD), pp. 382-385, 1987.

[9] C. S. Ying,et al, “DRAFT: An Efficient Area Router Basedon Global Analysis,” Proc. of IEEE Int. Conference oComputer-Aided Design (ICCAD), pp. 386-389, 1987.

[10] A. Margarino, A. Romano, A. De Gloria, F. Curatelli and PAntognetti, “A Tile-Expansion Router.”IEEE Transactionson Computer-Aided Design, Vol. CAD-6, No. 4, pp. 507-517, July 1987.

[11] M. H. Arnold and W. S. Scott, “An Interactive Maze Routewith Hints,” Proceedings of ACM/IEEE 25th Design Automation Conference, pp. 672-676, 1988.

2-layer 4-layer reduction

hp 3562 X 3402 3488 X 3228 7.1%apte 7105 X 7560 7032 X 7508 1.7%xerox 4270 X 6127 4078 X 6003 6.3%ami33 1511 X 1478 1317 X 1338 21.1%ami49 6971 X 6882 7029 X 6582 3.6%

Table 3. Area reduction results

l-, asn-ing

i-l-,xesile-h-ltr-sly

-

.

-

e

r-

.

[12] S. H. Gerez and O. E. Herrmann, “CRACKER: A GenerArea Router Bases on Stepwise Reshaping,” ProceedingIEEE International Conference on Computer-Aided Desig(ICCAD), pp. 44-47, 1989.

[13] K. Mikami and K. Tabuchi, “A Computer Program for Optimal Routing of Printed Circuit Connectors,” IFIPS Proceeings, Vol. H47, pp. 1475-1478, 1968.

[14] D. Hightower, “A Solution to Line Routing Problems on thContinous Plane,” Proceedings of Design Automation Worshop, 1-24, 1969.

[15] N. Katoh,et al, “Multi-layer Gridless Routing Method Basedon Line-Expansion Algorithm,” VLSI Logic Synthesis andDesign, pp. 279-285, 1990.

[16] Chia-Chun Tsai, Sao-Jie Chen and Wu-Shiung Feng, “An V Alternating Router,” IEEE Transactions on Computer-Aided Design, Vol. 11, No. 8, pp. 976-991, August 1992.

[17] Robi Dutta,et al, “Multi-layer Area Routing Algorithm as anOptimization Problem,” Proceedings of IEEE Custom Intgrated Circuits Conference, pp. 27.4.1-27.4.4, 1990.

[18] J. M. Cohn,et al, “KOAN/ANAGRAM II: New Tools forDevice-Level Analog Placement and Routing,”IEEE Journalof Solid-State Circuits, Vol. 26, No.3, pp. 330-42. March1991.

[19] Enrico Malavasi and Alberto Sangiovanni-Vincentelli, “AreRouting for Analog Layout,”IEEE Transactions on Com-puter-Aided Design, Vol. 12, No. 8, August 1993.

[20] M. Guruswamy and D. F. Wong, “A General Multi-layer AreRouter,” Proceedings of ACM/IEEE 28th Design AutomatioConference, pp. 335-340, 1991.

[21] N. K. Sehgal,et al, “A Gridless Multi-layer Area Router,”Proceedings of Fourth Great Lakes Symposium on VLSDesign Automation of High Performance VLSI Systems, p158-161, 1994.

[22] Jeremy Dion and Louis M. Monier, “Contour: A Tile-baseGridless Router,” Western Research Laboratory ReseaReport 95/3, Palo Alto, California.

[23] P. S. Tzeng and C. H. Sequin, “Codar: A Congested-DirecGeneral Area Router,” Proceedings of IEEE InternationConference on Computer-Aided Design (ICCAD), pp. 30-31988.

[24] R. E. Lunow, “A Channelless, Multilayer Router,” Proceedings of ACM/IEEE 25th Design Automation Conference, p667-671, 1988.

[25] Y. L. Lin, et al, “Hybrid Routing,” IEEE Transactions onComputer-Aided Design, Vol.9, No.2, pp. 151-157, February1990.

[26] Kenneth M. McDonald and Joseph G. Peters, “Smallest Pain Simple Rectilinear Polygons,”IEEE Transactions on Com-puter-Aided Design, Vol. 11, No. 7, pp. 976-991, July 1992.

[27] Charles J. Poirier, “EXCELLERATOR: Automatic Leaf CelLayout Agent,” Proceedings of IEEE Int. Conference oComputer-Aided Design (ICCAD), pp. 176-179, 1987.

[28] John K. Ousterhout, “Corner Stitching: A Data-StructurinTechnique for VLSI Layout Tools.”IEEE Transactions onComputer-Aided Design, Vol. CAD-3, NO. 1, pp. 87-100,January 1984.

[29] N. J. Nilsson,Principles of Artificial Intelligence, EnglewoodCliffs, NJ: 1980, pp.53-94.

[30] Wei-Ming Dai, et al, A “Dynamic and Efficient Representa-tion of Building-Block Layout,” 24th ACM/IEEE DesignAutomation Conference, pp376-384, 1987.

[31] Wen-Chung Kao,et al, “Cross Point Assignment with GlobalRerouting for General-Architecture Designs,”IEEE Transac-tions on Computer-Aided Design, Vol 14, No 3, Mar. 1995.