08.546 dsd with vhdl lecture notes_module 1

8/3/2019 08.546 DSD With VHDL Lecture Notes_Module 1

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08.546 Digital System Design with VHDL

Lecture 1

Introduction to digital system design

Start the session with an introduction to DIGITAL ELECTRONICS.

Announcement:

Review of Binary system and Boolean algebra

Review of Logic gates, Multiplexer (combinational circuits), Flip Flop,

Registers, Counters (sequential circuits), etc.

Discrete components

Digital ICs

Fab devices

Microprocessor (CPU)

Wrist watch to satellite vehicle

Microcontrollers (SoC)

(Interactive questions related to De Morgan's Law, Universal gates, Digital circuits, Digital ICs

etc.)

Programmable Logic Devices (PLD)

Announcement:

To build reconfigurable digital circuits

Field devices

General purpose chip for implementing logic circuits

Developed by Rone Cline from Signetics (Later Philips, now Xilinx)

Different types (ASIC and Non-ASIC):

ROM

Not as memory

m input lines (address lines), n output lines (data lines)

2m Boolean functions allows 2n logic functions produced at output

Department of ECE, VKCET Page 1


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Notes Basic ROM Structure

The logic array are of mask, fusible wires or special charge-storage

mechanism

Along with flip flops sequential logic can be implemented

Announcement

Programmable Logic Array (PLA)

More flexible than ROM

Internal decoder is replaced with AND array

Notes Basic PLA structure

Announcement



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Programmable Array Logic (PAL)

Economical and easy to program

Same as PLA, but AND array is only programmable

All these PLDs are available with Flip flops

Lattice Semiconductors, Cypress Semiconductors, Atmel , Xilinx, Altera,

Texas Instruments are some vendors of PLDs

Complex PLD (CPLD)

ROM, PLA and PAL are not flexible for sequential and more complicated

combinational digital circuit design

Upto 10,000 logic

Contains many PAL blocks called macro cells

Notes Typical structure of macro cells



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Structure of typical CPLD

Typical CPLD consists 2 to few 100 PAL blocks

Some CPLD vendors and the devices are:

Altera MAX 7000 Family

AMD Mach Family

Lattice Family

Cypress Flash 370 Family

Xilinx XC9500 Family

Announcement

Field Programmable Gate Array (FPGA)

For large number of logic circuits



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More than 10,000 logic

Notes General structure of FPGA

Contains logic blocks (instead of AND and OR plane), IO block and

interconnection switches

Some vendors are:

Xilinx Actel

Atmel Lattice

Altera Quick Logic



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Applications:

Announcement Electronic Design Automation (EDA) Tools:

Software tools for designing electronic system like PCBs, ICs,

PLDs, CPLDs, FPGAs, etc.

Simulation, analysis and verification, manufacturing

Some vendors of EDA softwares are:



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Cadence Design System

Cadsoft

Impulse Accelerated Technologies

Labcenter

Mentor Graphics

National Instruments Electronics Workbench Group

Synopsys

Visionics

Announcement

Hardware Description Language (HDL)

Programming language used to model the intended

operation of a piece of hardware

To describe the architecture and behavior of digital electronic

system

Various softwares:

ABEL (Advanced Boolean Expression Language)

AHDL (Altera HDL)

C to Verilog

Impulse C

JHDL (Java HDL)

RHDL (Ruby HDL)

System C

System Verilog

Verilog

VHDL



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Announcement

Syllabus

Module 1

Design flow of digital system

Introduction to EDA and HDL, Simulation etc

Basics of VHDL

Module 2

VHDL syntax and statements

VHDL models for basic combinational and sequential circuits

Module 3

VHDL model for digital circuits

State machines and its VHDL model

Synthesis

Designing of CPLD and FPGA

Quiz

1. Find the odd one: a) Microcontrollers b) Micrprocessors c) FPGA d) IC 7400

2. PAL stands for ---------------.

3. Sort the followings in ascending order based on its flexibility for complex digital system

design : a) CPLD b) ROM c) PAL d) PLA e) FPGA

4. VHDL is ------- a) PLD b) Language for hardware description c) EDA software d)

Microcontrollers

5. Xilinx is ---------a) Microprocessor b) EDA software c) PLD vendor d) Programming

Language



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Lecture 2Digital system design Process:

Announcement:

Steps to design a digital system:

Notes

Between each steps designer check the result of last transformation and more

information according to the result and passes to the next step

Behavioral definition may be a flow chart, pseudo code etc.. and specify all

function and IO mapping without the details of hardware or the system under

design.

Designer must specify the registers and logic units for the system by the data

path



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Data path:

Path may be unidirectional or bidirectional buses

Logic design involves the use of primitive gates and flip flops of

registers, buses, logic units, control unit etc.

The result of the logic design is net list of gates and flip flops

Net list is transformed into transistor list or layout (by library cells)

Manufacturing is the final step, burn fuses of a field-programmable

device or to generate masks for IC fabrication

Design Automation:

Announcement:

Paper-and-pencil design methodology is replaced with CAD tools, due

to the size and complication of digital system

Designer's idea is transformed int data path description and rest of theroutine can do faster by machine than a talented engineer

The machine is programmed to transform on form of design into

another and the process is called design automation (DA)

DA helps with design entry, hardware generation, test sequence

generation, documentation, verification and design management.

DA helps to generate tests for register transfer fault, can be used to

process system level description and to produce tests that can be used

by test equipment.



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DA tools include synthesizer, that automatically generate net list from

the register and bus structure of the system under design or generate

architectural layout from behavioral description of the system.

Assignment

1. i) List out various EDA software. Give the advantages and

limitations of EDA softwares.

Hardware Modeling

Announcement

Modeling depends on the purpose for which the model is intended

Model may be an abstract behavioral-level model or detailed description

level.

Model should be an imitation of actual hardware component as close as

accurate

Modeling tools include paper-and-pencil, schematic capture program,

bread boarding facilities and hardware description language

Level of modeling vary from one language to other

Computer Aided Design (CAD) tools are used for modeling

Hardware Description Language (HDL)

Announcement

HDLs are used to describe hardware for simulation, modeling, testing,

design and documentation of digital system.

HDL provides hierarchical representation of functional and wiring details

of digital systems.

HDL consists set of symbols, notations etc

HDL program execution is concurrent, so closer to programming

languages for parallel computers

Software for HDLs includes simulators, test and testability applications

and hardware synthesis programs

Simulators are used for design verification, synthesizer are for automatic

hardware generation and test generation provide net list format, test

application test bench and fault injection

Notes



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Three HDLs:

1. Language forbehavioral descriptions:

Instruction Set Processor Specification (ISPS) is an eg. For HDL

using behavioral description

Designed for hardware simulation,design automation and

automatic generation of machine-relative software

Software like programming language, but includes constructs for

data movement between registers and buses

ISPS Script for a simple processor:

mark1 :=

BEGIN** memory.state **m[0:8191],** processor.state **pi\present.instruction'f\function := pi,s := pi,cr\control.register,

acc\accumulator,** instruction.execution ** {tc}MAIN i.cycle :=BEGINpi = m[cr] NEXTDECODE f =>BEGIN0\jmp := cr = m[s],1\jrp := cr = cr + m[s],2\ldn := acc = - m[s],3\sto := m[s] = acc,

4:5\sub := acc = acc - m[s],6\cmp := IF acc LSS 0 => cr = cr + 1,7\stp := STOP(),END NEXTcr = cr + 1 NEXTRESTART i.cycle

This is most appropriate for representing output of the behavioral

design step in a design process.

2. Language fordescribing flow of data:



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A Hardware Programming Language (AHPL) is an example for

this type HDL

Uses set of notations for the representation of hardware

AHPL script for sequential multiplier:

AHPLMODULE: multiplier.

MEMORY: ac1[4]; ac2[4]; count[2]; extra[4]; busy.EXINPUTS: dataready.EXBUSES: inputbus[8].OUTPUTS: result[8]; done.CLUNITS: INC[2](count); ADD[5](extra; ac2);1 ac1


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Verilog description :

`timescale 1 ns / 1 ns

// A 6-gate full adder; this is a commentmodule fulladder (s, co, a, b, c);

// Port declarationsoutput s, co;input a, b, c;

// Intermediate wireswire w1, w2, w3, w4;

// Net list description

xor #(16, 12) g1 (w1, a, b);xor #(16, 12) g5 (s, w1, c);and #(12, 10) g2 (w2, c, b);and #(12, 10) g3 (w3, c, a);and #(12, 10) g4 (w4, b, a);or #(12, 10) g6 (co, w2, w3, w4);endmodule

Comparing three descriptions:

Behavioral description

Well suited for modeling overall functionality of a final

product

Data flow descriptions

Well suited for describing a circuit for design and construction

Net list descriptions

Well suited for detailed analysis or manufacturing of a circuit

Quiz



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1. What is the second step to design a digital system using HDL?

a) Manufacturing b) Logic design c) Behavioral design d) Physical design

2. What is the advantage of HDL over normal programming language?

3. HDL is a --------- a) Net list description language b) Behavioral description

language c) EDA tool d) data flow description language e) all of the above

Lecture 3Announcement Hardware Simulation:

HDLs are modeling tools to create hardware model

Simulation is an act of exercising a model of an actual component in

order to analyze under a given set of conditions and/or stimuli

HDL uses component model and definitions from simulation libraryto form a hardware model.

Notes

Hardware simulation model:

The results obtained from the simulator depends on the level of detail of a

model

Simulation engine may be capable of producing detailed timing, analog

voltages, high level function information

Simulation engine will produce results based on the complete details of

the input model



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Simulator based on HDL can process hardware details supported by its

input HDL

Test bench provides stimuli an relative time of data application to a

simulation engine, simulator applies these data at the specified times andgenerates responses of the circuit

Results of the simulator may be waveforms, timing diagram or time-value

tabular listing

Designer can determine the results are satisfactory, otherwise repeat the

simulation

Verification of each stage of design:



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Announcement:

Classification of digital system simulators:

1. Oblivious simulators

2. Event-driven simulators

Notes

Oblivious Simulators:

Each circuit component is evaluated at fixed time points

Illustration:

EX-OR gate using primitive gates and is simulate with the data

provided the signal shown

In first phase of this simulation program converts the inputcircuit description to a machine-readable tabular form



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Simulator read input values at fixed time intervals and apply

them to internal tabular representation of the circuit

At time tp input values of a and b are read from an input file,

and replaces the old values and output values of all circuit

components will be reevaluated

A change in any value column indicates the circuit has not

stabilized, and more reevaluation of table necessary

Event-driven Simulation:

A component is evaluated only when one of its input changes

More complex, but more efficient simulation

Data structure suitable for EX-OR gate using primitive gates:

In first phase simulator converts the circuit description to a linked list

of data structure

In second phase, a change on an input triggers only those nodes of the

linked list for which an input changes

For a complex circuit, speed of this simulation is more



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Announcement Hardware Synthesis

Design aid that automatically transform a design description from one

form to another.

Move the level of design to one step higher toward its final

implementation

HDL is a useful media for input and output of hardware synthesizers

First step to hardware designer's

Notes Categories of synthesis tools in a design process:

Typical synthesis process:

Hardware description and directives are tool inputs



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Three synthesis stages

Result is layout or netlist

Resource sharing:

Input description affects results

Explicit specification of resource sharing

Sharing without and with extra overhead

Announcement Levels of Abstraction:

Three levels of abstraction for HDL in digital design technique:

Dataflow

Structural

Behavioral



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Behavioral description

Behavioral description is functional

Most appropriate for fast simulation

Present an input-output mapping for the design

Accessible to non-engineers as well as end users of hardware

component

Dataflow description

Concurrent representation of flow of control and movement of data

Cannot serve as a end-user or non-technical document

Technically oriented and describe the components to be synthesized

Slower than input-output mapping of behavioral description

Structural description

Lowest and most detailed level

Simplest to synthesize

Have the list of concurrent active components and their

interconnections

Gate level description with detailed timing simulation

Quiz

1. Compare oblivious and event-driven simulation

2. Logic optimization is ------------

a) Type of Hardware simulation b) Level of abstraction for HDL c) A step in

digital system design process d) Hardware Synthesizer tool



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Lecture 4Announcement VHDL Background

Very high speed integrated ciruits (VHSIC) Hardware Description

Language

Design and documentation tool for VHSIC program

Initiation of State Department of Defense (DoD) in 1981 at Woods

Hole, Massachusetts as a part workshop on HDLs

1983: DoD: Requirements were established Contract was awarded to

IBM, TI, Intermetrics ITAR restrictions removed from language

1984 : IBM, TI, Intermetrics : VHDL 2.0 was defined

December 1984: VHDL 6.0 was released Software development

started

1985: VHDL 7.2 was released to IEEE ITAR removed from software

May 1985: Standard VHDL 1076/A

December 1987 : VHDL 1076-1987 became IEEE standard

1993 : VHDL 1076-1993 was approved

HD Languages:

AHPL : A Hardware Programming Language

Datafow level of abstraction

Uses implicit clock for synchronized registers and flip

flops

Consists concurrent models

Fixed data types

Restriction on functions

Design hierarchy not supported

CDL : Computer Design Language

Datafow level of abstraction

Design hierarchy not supported

Uses microstatement for data transfer between registers

CONLAN : CONsensus LANguage



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Various level of abstraction

Hierarchical description of hardware, but some

limitation

IDL : Interactive Design Language

Internal IBM language

Automatic generation of PLA structures

Hierarchical description of hardware

ISPS : Instruction Set Processor Specification

High level behavioral language

To create an enviornment for designing software basedon a given hardware

Limited timing control

TEGAS : TEst Generation And Simulation

For test generation and simulation of digital circuits

Strctural and Behavioral features

TI-HDL : TI Hardware Description Language

Multilevel language

Supports sequential as well as combinational circuits

Fixed data types

ZEUS : An HDL by GE corpration

Nonprocedural language

Clock level timing

Timing is limited, so asynchronous circuits cannot be

described

Announcement Design Methodology Based on VHDL:

Elements of VHDL:

Describing hardware components

Packaging parts and utilities

Libraries and binding



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Notes

Describing components:

To describe hardware components and systems

Consists an interface specification and an architectural

specification

ENTITY contains input-output ports, external characteristics

like time and temperature dependencies

ARCHITECTURE describes the functionality of of thecomponent

Functionality depends on input-output signals and other

specified interface description

Several architectural specifications with different identifiers

can exist for one component

Multiple architectural specifications:



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Packages:

Group components and utilities for description of components

Type of definitions and subprogram

Package decleration contains components and utilities to become visible

by ENTITIES and ARCHITECTURES

Package body contains subprogram definitions and utilities used by

subprograms

Libraries and binding:

Use of libraries and binding of subcomponents of a design to elements of

various libraries

Include a library statement and configurations

Announcement: Top-Down Design:

Divide-and-conquer strategy

Recursive partitioning of a system into its subcomponents unti all

subcomponents become manageble design parts (available as a part of

library)



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Notes

Recursive partition procedure

Mapping to hardware depends on target technology (eg. CMOS VLSIlayout), available libraries and available tools (eg. Good synthesis

tool, routing etc)

After partition a partition tree and hardware implementation of

terminals of the tree become available

Top-down design and bottom-up implementation:

Verification:

Each and every step of a top-down design process multilevel

simulation tool perform verification and is an important role in

system designe



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Behavioral description of SUD is simulated to verify the

understanding of the problem

After first level of partitioning, behavioral description of SSCs

is wired to form a structural hardware model of the SUD andsimulated, the result is compared with the original CUD for

verification

Verifying first level of partitioning

Verifying hardware implementation.

Verifying the final design.



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For large design such verification is too low

Verifying hardware implementation of SSC3.

This behavioral model of SSC3 can be used in all simulation runs for

verification

An alternate verification of the final design

SSC3 behavioral and hardware model may be functionally equivalent,

but timing and other physical parameters may be different.Such cases

behavioral model of subcomponent can be adjusted to mimic such

properties.

Quiz

1. Name some HD Languages.

2. In VHDL, ENTITY and ARCHITECTURE are to ..................



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a) describe hardware components b) to packaging parts and utilities c) to

libraries and binding

3. After recursive partition procedure in top down design approach results ...

a) behavioral model b) libraries c) partition tree and hardware

implementation of terminals of the tree d) packages

4. Why verification is essential in top down design?

Lecture 5Announcement Top down design with VHDL:

How to describe hardware at various level of abstraction using VHDL

How to form a top-level, mixed level model

How various simulation model can be simulated

Finally how a synthesize tool can help a hardware designer.

Example choosed for designing should be complex to show the real power of VHDL

and VHDL based tools and should be small enough to be able to illustrate the design

steps.

Notes Design to perform:

Consider serial adder

Operation:

Two data inputs (For eg: 8 bits) a and b, a start input and clock

signal for synchronization, since the circuit is a sychronoussequential circuit.

Serial data inputs are synchronized with clock and it will appear

on a and b after the sychronous pulsestart.

The order of the bits is from least to most

After 8 clock pulses the resultoutput will have the add result of

the serial data input and the ready output becomes 1 indicates the

data output is ready. This status remains 1 until another

sychronous start pulse is observed.



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Announcement Setting the stage:

Design partition process continues until a design is partitioned

into a manageable parts

Generally available tools for a designer are: Synthesis tools,

complex library elements and a set of configurable parts, usually

previous designs

Notes Available synthesis tools:

Capable to translate high-level discription language into

interconnection of logic cell or FPGA layouts

To synthesize logic expressions to generate nonfeedback,

memoryless combinational circuits

Available libraries:

Libraries consists predesigned and tested commonly used

functional units

At board level 74XX series libraries are very common, because

many designers are familiar with these parts, IC and in particular

ASIC

Our case: Library contains a multiplexer and a D type flipflop.

Generic symbols:



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VHDL model of 2:1 multiplexer library element is shown below:

Library element terminal node of partition tree

Indicates the multiplexer library element with hardware-level characteristics

Interface description:

At top level, input and ouput ports as well as physical

parameters of the system are specified

ENTITY is the interface description and is mux2_1 in the

upper part and is the name of components

GENERIC is the keyword indicate the model timing

parameters, where dz_delay parameter of type TIME and has a

default value 6ns

PORT is the keyword indicate the names of ports, where sel,

data1 and data0 are three inputs ot type BIT andzis the output

of type BIT for the component mux2_1

The keywords IN and OUT specify the mode of the port signal

and a signal declared as IN cannot be assigned a value from

within the component and an OUT signal cannot be used on

the right hand side of a signal assignment.

Architecture description:

Functionality of the component

Functionality of mux2_1 is specified by flow of data from

input to output

Begins with ARCHITECTURE keyword followed by an

identifier dataflow of the entity mux2_1 to which the

architecture belongs

BEGIN keyword starts the body of description in which the

conditional signal assignment selects data1 ordata0based on



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the value ofsel

The mux2_1 architecture dataflow also specifies the delay

value for assigning input signals to the output

Conditional signal assignment is concurrent statement

Discription of the hardware components shows the data flow through busses, logic

units and registers. For an eg. The data flow between a logic unit, two registers and a register file

connected by two busses is shown below;

VHDL model of flipflop library element is shown below:

flop is the ENTITY has two timing parameters td_resetand td_in



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reset, din and clkare input of type BIT and qout is BUFFER output of

type BIT assigned with 0

Description offlop begins with PROCESS keyword, which is for bodying

sequential statement

Assigning appropriate values, neither the structure nor the details of

hardware (so behavioral)

Graphical behavioral description:

Parts from previous designs:

Hardware designer have his/her own library of parts

A pre-design VHDL model for counter used for stage setting:



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Design stage setting

Announcement: Design Scenario:

Steps to top down design for serial adder:

Analyszing the requirements

Notes VHDL model of serial adder



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VHDL simulation results:

Recursive partitioning

First circle : counter (divide by 8)

Second circle: full adder

Inside second circle: flipflop to hold carry

Third circle: serial shifter

General layout of the design



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First level of partitioning

We have flipflop and counter models

VHDL descriptions forfulladderandshifterare:

Fulladder maybe described at behavioral or dataflow level of

abstraction, since it is combinational circuit and its synthesis tool is

available in stage setting

Shift registershifter is described at data flow level, it cannot be

synthesized with the synthesize tool in stage setting, so furtherpatitioning is required



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Completed parts of first patitioning

Shaded areas have models of libraries or completed parts and bold

boxes indicate that behavioral description is available.

Verification is done by forming a model by wiring fulladder, flop,

shifter and counterand comparing the simulation of this model withthe behavioral description ofserial_adder

Structural description ofserial_adder

Consists interconnection of its four components

Structural description has declarative part and statement part

Four components are instantiated

Signals a, b, clock, ready and result appears in the interface

description of the serial adder, other signals are used for

interconnections



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Signal mapping forfulladderinstantiation

carry_in signal connects to the cin input offulladder, at the

same time this signal is used in the port map offlop

Partial code with intercoonections

Complete code ofserial_adderis simulatable.

Second level of partitioning (shifter)



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To eight flipflop with synchronous resetand clock

Behavioral model ofder_flop

Not as the libraries, to serve i) as a description for verifying the

partitioning and ii) for studying it for purpose of designing it

Structural description of shifter

After simulation and verification, der_flop must be designed

Hardware of flipflop (deduced form of behavioral description)



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Partitioning ofder_flop

The units are available in libraries

Structural description ofder_flop

Satisfies the behavioral description requirements

Complete design of serial-adder

All terminals have hardware corresponding set in stage setting

Design implementation:



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Bottom up implementation consists of wiring mux2_1 andflop to

build der_flops to buildshifterand wiringfulladder, flop, shifter and

counterto buildserial_adder

Final circuit description

Can be simulated along with original behavioral description

Two models have same function, but different timing properties

To develop test bench model for describing any functional differences

Announcement: Final act:

Final design results 19 hardware components from libraries or

generated by syhthesis tools

For large design size and complexity of libraries, toolss and VHDL

descriptions may different



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Real world:

With a commercial synthesis tool, the VHDL description for

serial_adder(with a sligth modification) is:

Partial layout of theserial_addersysnthesized to an FPGA target



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Assignment

1. ii) Assuming that the only available part is a two-input NAND gate, show the

partition tree for a two-bit magnitude comparator. (Hint: Form the Karnaugh

maps and generate the complete gate list using the output maps.)

iii) Assuming that the only available parts are a D-type flip-flop and a two-

input NAND gate, show the partition tree for a Moore 1011 sequence

detector. (Hint: From the state diagram and all design steps must be carried

out.)

iv) Write a dataflow description for a 1-bit comparator. The output of the

comparator becomes 1 when its 2-input bits are equal.

Lecture 6

Review

What is partition tree?

Steps to design a model using top down design approach.

Announcement Subprograms:

Similar to any other high-level languages, VHDL allows functions an

procedures (subprograms)

They can be declared, defined and invoked same as any other languages

Procedure can be useful for type conversions

Notes byte_to_integerprocedure for converting 8-bit binary data to integer:



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faddfunction for full adder operation:

fulladderusingfadd:

Announcement Controller description:

For a complete design data unit and a controller is must

Questions Define state machine.

Differentiate Moore machine and Mealy machine

Notes General outline of a controller

State machine

State transition decisions are based on the values of control



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inputs and are synchronized with a system clock

Simple form of a controller is sequence detector

VHDL description for a simple sequence detector (Moore machine):

The state machine for the above sequence detector:

VHDL behavioral description for the state machine:

Interface includesx and clk inputs andzoutput



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In architecture description, type state is declared to include the

elements in the state machine

There is a case statement and is responsible for state transitions based

on the input values and setting output

Partial code of this transition and its state diagram:

Announcement VHDL operators:

Common type to describe hardware are logical operators

Others are: relational, shifting, adding, sign, multiplying etc.

Notes

Operators operates on BIT or BOLEAN are used describe logic

gates or for general logic operations



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Relational operators are for comparing scalar and arrays

Shift operations are for shifting BIT and BOOLEAN vectors and

the specified numbers of positions

Adding operators consists add, subtract and concantenation

operators

In addition to multiplying operators, MOD and REM operators

return the reminder of their left operand and the difference in the

operators is in handling of negative numbers

Announcement Conventions and syntax:

VHDL keywords are not case sensitive, except some

characters

Syntax of VHDL code (typical):

Quiz

1. Procedure is a _______________________

a) State machine b) data flow description c) subprogram d) VHDL operator

2. Name two VHDL operators.3. The controllers can be implemented by _________________

5. a) combinational circuits b) state machines c) entities



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Lecture 7Review

1. What are the VHDL operators?

2. VHDL is a case sensitive language?

Announcement Basic concepts in VHDL:

Different features from those in software languages

Features to represent special characteristics of hardware components

Characterizing hardware languages

Two characteristics of HDL:

Timing

Concurrency

They are instrumental in correct description of hardware components

at various level of abstraction

Notes Timing:

Wires or busses are used for transfering values between hardware

components or within the components

Signals inVHDL represents real wires

Value transfer through wires:

Gate outputs are connected to two gate inputs through long

capacitive wires

Wiring capacitance and pull-up or pull-down resistances cause

propogation delay through wires



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Simple VHDL assignment statement for the above hardwre:

Here timing is not considered

More accurate VHDL assignment statement:

Concurrency:

Essential feature in HDLs

Software task is in sequential manner, but a hardware is not always

like that, so hardware description is achived by concurrently active

components through their input and output ports

VHDL is a language for which simulators have been developed on

single processor platforms and true concurrency in execution of

thousands of components cannot exist

VHDL simulator makes the users the execution is being done

concurrentlyDescribing subcomponents:

Cocurrent body consists three concurrent structures, each

component may be described by concurrent construct or by

sequential program



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Interconnection of subsystem A (structural) , B (data flow) and

C (sequential) is specified as concurrent body

The architecture of components is concurrent body, and

component instantiation and wiring, concurrent processes, andconcurrent signal assignments can appear this part

The block representation of a VHDL concurrent body:

VHDL simulator simulates this body concurrently, by executing

each statement only when an event occurs on a signal that

statement is sensitive to it

The block representation of VHDL sequential body:



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Similar to other programming languages

Modeling hardware:

Illustration of concepts of concurrency and timing in hardware

modeling of actual circuits

A gate circuit to illustrate timing and concurrency

All components in the circuit are always active and there is a

timing assosiated with every event in the circuit

Assume all gates has a delay of 12ns and all inputs are initially

high

Gates reaction to change in input:

Timing diagram:



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For gates with unequal delay values or the circuit is not stable,

these type analysis become more complicated

Announcement Objects and classes:

Entity has a value of a given type is a VHDL object

Objects may be explicitly declared or implicitly created in the

language

Port signals, loop index variables, signals for interconnecting

components, temporary variables and files are some objects

Notes

Object may be of one of the four classes:

Signals

Variables

Constants

Files

Objects and classes in sequential and concurrent bodies:

Objects of the signal class represent wires and timing

assosiated with them

Objects of the variable class are for storage of temporary

values and have no hardware significance



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Objects of constant class are for constant values of a given

type

Files are used in concurrent and sequential bodies

Summary of objects in VHDL bodies:

Quiz

1. Providing delay between wires and busses in VHDL components is by

__________

a) objects b) cuncurrency c) timing d) classes

2. Consider the following circuit

If all gates have 10ns delay, all inputs are initially '0', then draw the reaction

and timing diagram to change in the input c from '0' to '1'

6. The VHDL object variable can declare in a concurrent body, this statement

is true or false.



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Lecture 8Announcement Signal assignments:

Consists target signal on the left hand side of a left arrow and

an expression for defining a waveform on the right hand side,such assignment specifies that the rigth hand side be assigned

to the left hand side after a delta time

Signal assingnment can include an AFTER clause specifying a

physical time delay

Can have inertial or transport delays

Inertial delay have an additional reject specification and

transport delay must be explicitly specified

Notes Demonstration of delay mechanism:

Includes signal assignments with inertial, inertial with reject

and transport mechanism

Comparing three delay mechanisms and creating a reference

signal

INERTIAL keyword is optional

For inertial with reject, both REJECT and INERTIAL

keywords are mandatory



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Announcement Inertial delay mechanism:

Used to model capacitive networks

Notes RC delay model representing an inertial delay mechanism:

If a pulse width is less than 5ns occurs on waveform, it will be

rejected and does not appear on target1

Delays are acurately modeled with an inertialdelay mechanism

and the pulse rejection value that is less than the value of the

inertial delay

Announcement Transport delay mechanism:

To model the delays through transmission lines and networks

with virtually infinite frequency response

Notes Comparing inertial and transport:

Illustration



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Illustrating differences between delay mechanism in VHDL

Positive and negative pulses appear on the LHS

Quiz

1. The symbol


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Execution of concurrent signal assignment, a value will be scheduled

for the left hand side signal, and is said that the value is placed on the

drive of the left hand side

Multiple concurrent assignments to a signal produce multiple drivers

for that signal

Representation of multiple driving values of a signal to single resolved signal:

Multiple assignments to a signal produce a single driver for that

signal and affect the same driver

Assignments to a signal in multiple sequential bodies are considered

concurrent and each produces a driver for that signal and a resolutionfunction is required

Announcement Events and transactions:

When a waveform causes the value of the target signal change, an

eventis said to have occured on the target signal.

When a value is scheduled to be assigned to a target signal after a

given time, a transaction is said to be placed on the driver of the

target signal

Transaction is represented by a value-time pair in parentheses



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Notes A transaction from creation to expiration:

Execution of a signal assignment causes a value v calculated from

right hand side and delay d to be placed on the driver as (v,d)

transaction (tri) at tduring simulation time now

Initial time component d

At (t+to) time component of transaction tribecomes (d-to)

As simulation progresses, the time component of the transaction

approaches 0 and nowbecomes (t+d) and then transaction is expired

Illustration of events and trasactions:

Transactions are scheduled on the 3 LHS signals

Order is not significant

Initial transaction are placed on all 3 signals

Declaration of signals a, b and c causes creation of these signals with

initial values



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Creation of signals is referred as elaboration and assigning initial

values is called initialization

Events and transactions that ocuur on signals:

Figure a: Timing diagram

hollow rectangles shows transactions

black rectangles shows initial values

Figure b: Transactions

Figure c: Transactions as the time values approach zero to current value



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Transaction represent circle

Size of the circle signifies that the time element of transaction

Figure d: Transactions from creation to expiration

Announcement Delta delay:

In addition to real time delay, VHDL has an internal delay to define

simulation cycle, referred as delta delay ()

To model hardware concurrency

Notes VHDL description to demonstrate need of delta delay:

When an event occur in a orb , a AND b is evaluated and scheduled

to occur on the output zafter 10ns, then the complement ofzis then

placed on thhe driver ofz_barwith zero delay

By concurrency, it is expected a AND b and its complement appearonzandz_barexactly at the same time

But NOTz cannot be evaluated untilzreceives its new value

z signal receives its new value 10ns after an event on a or b, and

z_bar receeives its new value a delta time afterz receives its value

(10ns + ), where delta time is only in internal simulation cycle and

does not contribute to real time values

VHDL description for demonstrating delta delay:

Zero delay assignments

Accumulative worst-case delay of 36ns forzoutput



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Timing diagram:

Another example of delta time, transactions and concurrency:

Timing diagram:

All transaction occurs at time zero between (0 + 1) and (0 + 3)



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Another example for demonstration of delta delay:

With zero delay values of inverter and buffer, the circuit should

oscillate in zero time forever

Quiz

1. HDL has ______________ signal assignments

a) Concurrent b) Sequential c) Concurrent and sequential

d) None of the above

2. When a waveform causes the value of the taget signal to change, an __________

is said to have occured on the target signal

3. Differentiate event and transaction.

4. Delta delay limits _________

a) events b) transactions c) concurrency d) unwanted oscillation



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Lecture 10Announcement Sequential Placement of Transactions:

Body of process statements are done sequentially, so signal

assignment statements order is importment

Multiple signal assignments cause new transactions to be placed on

the driver of the signal

Notes Sequential placement of transactions in a sequential body:

First assugnment to x places the (v1, t1) transaction on the driver of

x, immediately following this assignment a new transaction (v2,t2) is

placed on the driver ofx.

The new transaction is overwrite or append to the driver.

WAIT statement at the end of the process causes the process tosuspend forever, allowing enough time for all pending transactions to

expire

Sequential placement of transactions on the driver of signals can also

be done in concurrent VHDL bodies

Sequential placement of transaction in concurrent body:

Similar to process

Signal drivers:

Has a driving value and several pending transactions on the signal

waiting to become current

Driver for a scalar signal is represented by a projected output

waveform (queue of transactions)



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Projected output waveform:

Transactions are queued according to their time components

Process or concurrent signal assignment statements creates only one

driver for a signal

Multiple concurrent assignment creates multiple drivers

Multiple projected output drivers:

Announcement Transaction appending values:

New transaction is characterized by its value, time and delay

mechanism

Transactions on the driver of a signal is characterized by their value

and time only



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New transaction value is already in the signal is referred as existing

New transaction scheduled before an existing transaction overwrites

the existing one

New transaction scheduled after an existing transaction appended to

the existing one, if the delay is of transport type

For inertial delays, new transaction scheduled after the existing

transaction appends to the existing one unless the values of transaction

are different and the difference between the time of new transaction

and existing transactionis less than or equal to the inertial reject value.

Notes Summary of resulting transaction on the driver of a signal:



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Examples:

Discarding previous transactions

The new transaction is scheduled before the existing one

Appending transactions

Delay type is transport

The new transaction is after the existing one



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Discarding previous transactions

The new transaction is scheduled before the existing one

Appending the new transaction of different value

Time difference of new and existing is greater than reject value



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Discarding previous transactions of different value

The new transaction is scheduled after the existing, and has a

different value

Pulse rejection:

An example:



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Timing diagram:

Pulse rejection in inertial, reject, and transport delay mechanism

This is a result of sequential placement of transactions

New, pending and expired transactions on the above example:



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Another example:

Timing diagram:

Sequential placement of transactions by executing concurrent

signal assignments

Events on a cause placement of transactions on b

In a waveform, all but the first are TRANSPORT

Quiz

1. The statements in the body of process are done ________________

a) sequentially b) concurrently c) both

2. A new transaction on the driver of a signal scheduled __________ an already

existing transaction.

08.546 dsd with vhdl lecture notes_module 1

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