vhdl lecture slides

OutlineOutline■ VHDL Background/History

■ VHDL Design Example

■ VHDL Model Components

–Entity Declarations

–Architecture Descriptions

■ Basic Syntax and LexicographicalConventions

Reasons for Using VHDLReasons for Using VHDL■ VHDL Is an International IEEE Standard

Specification Language (IEEE 1076-1993) forDescribing Digital Hardware Used by IndustryWorldwide

–VHDL is an acronym for VHSIC (Very High

Speed Integrated Circuit) Hardware Description

Language

Reasons for Using VHDLReasons for Using VHDL■ VHDL enables hardware modeling from the

gate to system level

■ VHDL provides a mechanism for digitaldesign and reusable design documentation

■ VHDL Provides a Common CommunicationsMedium

A Brief History of VHDLA Brief History of VHDL■ Very High Speed Integrated Circuit

(VHSIC) Program–Launched in 1980

–Object was to achieve significant gains inVLSI technology by shortening the time fromconcept to implementation (18 months to 6months)

–Need for common descriptive language

A Brief History of VHDLA Brief History of VHDL

■ Woods Hole Workshop– Held in June 1981 in Massachusetts

– Discussion of VHSIC goals

– Comprised of members of industry,government, and academia

A Brief History of VHDLA Brief History of VHDL

■ July 1983: contract awarded to developVHDL–Intermetrics

–IBM

–Texas Instruments

■ August 1985: VHDL Version 7.2 released

A Brief History of VHDLA Brief History of VHDL■ December 1987: VHDL became IEEE

Standard 1076-1987 and in 1988 an ANSIstandard

■ September 1993: VHDL was restandardized toclarify and enhance the language

■ VHDL has been accepted as a DraftInternational Standard by the IEC

GajskiGajski and Kuhn’s Y Chart and Kuhn’s Y ChartArchitecturalArchitecturalArchitecturalArchitectural

Physical/GeometryPhysical/GeometryPhysical/GeometryPhysical/Geometry

StructuralStructuralStructuralStructuralBehavioralBehavioralBehavioralBehavioral

ProcessorProcessorProcessorProcessor

Hardware ModulesHardware ModulesHardware ModulesHardware Modules

ALUsALUsALUsALUs, Registers, Registers, Registers, Registers

Gates,Gates,Gates,Gates, FFs FFs FFs FFs

TransistorsTransistorsTransistorsTransistors

SystemsSystemsSystemsSystems

AlgorithmsAlgorithmsAlgorithmsAlgorithms

Register TransferRegister TransferRegister TransferRegister Transfer

LogicLogicLogicLogic

Transfer FunctionsTransfer FunctionsTransfer FunctionsTransfer Functions

AlgorithmicAlgorithmicAlgorithmicAlgorithmic

Functional BlockFunctional BlockFunctional BlockFunctional Block

LogicLogicLogicLogic

CircuitCircuitCircuitCircuit

RectanglesRectanglesRectanglesRectangles

Cell, Module PlansCell, Module PlansCell, Module PlansCell, Module Plans

Floor PlansFloor PlansFloor PlansFloor Plans

ClustersClustersClustersClusters

Physical PartitionsPhysical PartitionsPhysical PartitionsPhysical Partitions

Copyright 1995, 1996 RASSP E&F

VHDL ModelVHDL Model

Behavioral

Architecture

Dataflow

Architecture

Structural

Architecture

Package

Entity

Generic Ports

Functional

Architecture

VHDLVHDL Combinational CombinationalTemplateTemplate

• Every VHDL model is composed of an entity andat least one architecture .

• Entity describes the interface to the model (inputs,outputs)

• Architecture describes the behavior of the model

• Can have multiple architectures for one entity (wewill only use one in this class).

A VHDL Template forA VHDL Template forCombinational Combinational LogicLogic

entity model_name is port ( list of inputs and outputs ); end model_name; architecture arch_name of model_name is begin concurrent statement 1 concurrent statement 2 ... concurrent statement N;

end arch_name ;

•All of the text not in italics are VHDL keywords. •VHDL is NOT case sensitive.

•(ENTITY is same as entity is same as EnTiTy).

Order ofthesestatementsis notimportant

VHDL Design ExampleVHDL Design Example■ Problem: Design a single bit half adder with carry and

enable

■ Specifications

– Inputs and outputs are each one bit

– When enable is high, result gets x plus y

– When enable is high, carry gets any carry of x plus y

– Outputs are zero when enable input is lowxxxxyyyy

enableenableenableenable

carrycarrycarrycarry

resultresultresultresultHalf AdderHalf AdderHalf AdderHalf Adder


VHDL Design ExampleVHDL Design ExampleEntity DeclarationEntity Declaration

■ As a first step, the entity declarationdescribes the interface of the component– input and output ports are declared

xxxx

yyyy


carrycarrycarrycarry

resultresultresultresultHalfHalfHalfHalf

AdderAdderAdderAdder

ENTITY half_adder IS

PORT( x, y, enable: IN BIT; carry, result: OUT BIT);

END half_adder;


We will, at least at first, useWe will, at least at first, usecapitals and colors to denotecapitals and colors to denoteVHDL language componentsVHDL language components

VHDL Design ExampleVHDL Design ExampleFunctional Functional SpecificationSpecification

■ A high level description can be used todescribe the function of the adder

■ The model can then be simulated to verifycorrect functionality of the component

ARCHITECTURE half_adder_a OF half_adder IS

BEGIN

PROCESS (x, y, enable)

BEGIN

IF enable = ‘1’ THEN

result <= x XOR y;

carry <= x AND y;

ELSE

carry <= ‘0’;

result <= ‘0’;

END IF;

END PROCESS;

END half_adder_a;


VHDL Design ExampleVHDL Design ExampleBehavioral Behavioral SpecificationSpecification

■ A high level description can be used todescribe the function of the adder

■ The model can then be simulated to verifycorrect timing of the entity

ARCHITECTURE half_adder_b OF half_adder IS

BEGIN

PROCESS (x, y, enable)

BEGIN

IF enable = ‘1’ THEN

result <= x XOR y after 10ns;

carry <= x AND y after 12 ns;

ELSE

carry <= ‘0’ after 10ns;

result <= ‘0’ after 12ns;

END IF;

END PROCESS;

END half_adder_b;


timing

VHDL Design ExampleVHDL Design ExampleData FlowData Flow Specification Specification

■ A Third Method Is to Use Logic Equationsto Develop a Data Flow Description

● Again, the model can be simulated at this level toconfirm the logic equations

ARCHITECTURE half_adder_c OF half_adderIS

BEGIN

carry <= enable AND (x AND y);

result <= enable AND (x XOR y);

END half_adder_c;


VHDL Design ExampleVHDL Design ExampleStructuralStructural Specification Specification

■ As a Fourth Method, a StructuralDescription Can Be Created FromPreviously Described Components

■ These gates can be taken from a library ofparts

xxxxyyyy

enableenableenableenablecarrycarrycarrycarry

resultresultresultresult


VHDL Design ExampleVHDL Design ExampleStructural Specification (Structural Specification (ContCont.).)

ARCHITECTURE half_adder_d OF half_adder IS

COMPONENT and2PORT (in0, in1 : IN BIT;

out0 : OUT BIT);END COMPONENT;

COMPONENT and3PORT (in0, in1, in2 : IN BIT;


COMPONENT xor2PORT (in0, in1 : IN BIT;


FOR ALL : and2 USE ENTITY gate_lib.and2_Nty(and2_a);FOR ALL : and3 USE ENTITY gate_lib.and3_Nty(and3_a);FOR ALL : xor2 USE ENTITY gate_lib.xor2_Nty(xor2_a);

-- description is continued on next slide


VHDL Design ExampleVHDL Design ExampleStructural Specification (Structural Specification (ContCont.).)

-- continuing half_adder_d description

SIGNAL xor_res : BIT; -- internal signal

-- Note that other signals are already declared in entity

BEGIN

A0 : and2 PORT MAP (enable, xor_res, result);

A1 : and3 PORT MAP (x, y, enable, carry);

X0 : xor2 PORT MAP (x, y, xor_res);

END half_adder_d;


VHDL Model ComponentsVHDL Model Components■ A Complete VHDL Component Description

Requires a VHDL Entity and a VHDLArchitecture–The entity defines a component’s interface

–The architecture defines a component’sfunction

■ Several Alternative Architectures May BeDeveloped for Use With the Same Entity

VHDL Model ComponentsVHDL Model Components

■ Three Areas of Description for a VHDLComponent:– Structural descriptions

– Functional descriptions

– Timing and delay descriptions (Behavioral)

Majority Gate ExampleMajority Gate ExampleThe following is an example of a three input XOR gate (majority gate)implemented in VHDL

library ieee;use ieee.std_logic_1164.all;

entity majority is port ( A, B, C : in std_logic; -- two dashes is a COMMENT in VHDL Y: out std_logic );end majority;-- this is the architecture declaration, uses only one concurrent statement.

ARCHITECTURE concurrent of majority is

begin

Y <= (A and B) or (A and C) or (B and C);end concurrent;

This is a style ofThis is a style ofone bigone bigexpressionexpression

Majority Gate with Temporary SignalsMajority Gate with Temporary SignalsThe following version of the majority gate uses sometemporary signals (entity has been left out, is same).

-- the architecture now uses 4 concurrent statements

ARCHITECTURE newconc of majority is signal t1, t2, t3 : std_logic ;

begin t1 <= A and B; t2 <= A and C; t3 <= B and C; Y <= t1 or t2 or t3;end newconc;

Note that temporary signals are declared between architecturestatement and begin statement.

Explain why this style isoften more convenient touse

Majority gate:Majority gate:Variant 2Variant 2

Concurrent statement, no process

Majority Gate with when-elseMajority Gate with when-elsestatementstatement

The following version of the majority gate uses a 'when-else' statement:

-- the architecture now uses a when-else statement.

ARCHITECTURE whenelse of majority is

begin Y <= '1' when ( (A and B) or (A and C) or (B and C)) else '0';end whenelse;

•You will find that there are many different ways to accomplishthe same result in VHDL. •There is usually no best way; just use one that you feel mostcomfortable with.


Concurrent statement, no process

Concurrent Versus SequentialConcurrent Versus SequentialStatementsStatements

• The statements we have looked at so far are calledconcurrent statements.– Each concurrent statement will synthesize to a block of logic.

• Another class of VHDL statements are called sequentialstatements.– Sequential statements can ONLY appear inside of a process block.

– A process block is considered to be a single concurrent statement.

– Can have multiple process blocks in an architecture.

– Usually use process blocks to describe complex combinational orsequential logic.

ProcessProcess■ Fundamental Unit for Component

Behavior Description Is the Process– Processes may be explicitly or implicitly

defined

– They are packaged in architectures

VHDL Model ComponentsVHDL Model Components■ Primary Communication Mechanism Is

the Signal (distinct from a variable)– Process executions result in new values being

assigned to signals which are then accessibleto other processes

– Similarly, a signal may be accessed by aprocess in another architecture by connectingthe signal to ports in the the entitiesassociated with the two architectures

Output <= My_id + 10;Output <= My_id + 10;

Note symbolused for signals

VHDL EntityVHDL Entity■ The Primary Purpose of an Entity Is to Declare

the Input and Output Signals WhichCommunicate With It.– Interface signals are listed in the PORT clause

which has 3 parts:

»Name

»Mode

»Data type

VHDL Entity ExampleVHDL Entity ExampleENTITY OR3 IS

PORT ( A, B, C : IN BIT;

D : OUT BIT );

END OR3;

Entity DeclarationsEntity Declarations■ The Primary Purpose of the Entity Is to

Declare the Signals in theComponent’s Interface–The interface signals are listed in thePORT clause

»In this respect, the entity is akin to theschematic symbol for the component


Entity versus Schematic SymbolEntity versus Schematic Symbol

Entity Examplexxxx

yyyy


carrycarrycarrycarryresultresultresultresult

HalfHalfHalfHalfAdderAdderAdderAdder

ENTITY half_adder IS

GENERIC(prop_delay : TIME := 10 ns);

PORT( x, y, enable : IN BIT; carry, result : OUT BIT);

END half_adder;

Entity DeclarationsEntity DeclarationsPort ClausePort Clause

■ PORT clause declares the interface signals of the object to the outsideworld

■ Three parts of the PORT clause– Name

– Mode

– Data type

– Note port signals (i.e. ‘ports’) of the same mode and type or subtype may bedeclared on the same line

PORT (signal_name : mode data_type);PORT (signal_name : mode data_type);

PORT ( input : IN BIT_VECTOR(3 DOWNTO 0); ready, output : OUT BIT );

PORT ( input : IN BIT_VECTOR(3 DOWNTO 0); ready, output : OUT BIT );


name mode Data type

Entity DeclarationsEntity DeclarationsPort Clause (Port Clause (ContCont.).)

■ The Port Mode of the Interface Describesthe Direction in Which Data Travels WithRespect to the Component

■ Five Port Modes1. IN: data comes in this port and can only be

read

2. OUT: data travels out this port

Entity DeclarationsEntity DeclarationsPort Clause (Port Clause (ContCont.).)

3. BUFFER: bidirectional data, but only onesignal driver may be enabled at any one time

4. INOUT: bidirectional data with any numberof active drivers allowed but requires a BusResolution Function

5. LINKAGE: direction of data is unknown

Entity DeclarationsEntity DeclarationsGeneric ClauseGeneric Clause

■ Generics May Be Used for:– Readability,

– Maintenance,

– Configuration.

■ Generic Clause Syntax :

– If optional default_value is missing in genericclause declaration, it must be present whencomponent is to be used (i.e. instantiated)

GENERIC (generic_name : type [:= default_value]);GENERIC (generic_name : type [:= default_value]);


Behavioral DescriptionsBehavioral Descriptions■ VHDL Provides Two Styles of Describing

Component Behavior–Data Flow: concurrent signal assignment

statements

–Behavioral: processes used to describe complexbehavior by means of high-level languageconstructs

» variables, loops, if-then-else statements, etc.


Majority Gate using Majority Gate using process process block and block and ifif statement statement

The entity declaration has been left out (same as before).

ARCHITECTURE ifstate of majority is

begin main: process (A, B, C) begin Y <= '0'; -- default output assignment. if ((A = '1') and (B = '1')) then Y <= '1'; end if; if ((A = '1') and (C = '1') ) then Y <= '1'; end if; if ((B = '1') and (C = '1') ) then Y <= '1'; end if; end process main;end ifstate;

name of aprocess

name of aprocess


process

Comments on process blockComments on process blockmodelmodel

• The first line in the process "main: process (A, B, C)" has the name ofthe process (main) and the sensitivity list of the process.– The process name is user defined, can also be left out (unnamed process).

– The sensitivity list should contain any signals that appear on the right hand sideof an assignment (inputs) or in any boolean for a sequential control statement.

• The if statement condition must return a boolean value (TRUE orFALSE) so that is why the conditional is written as: ( (A='1') and (B= '1') )

• Cannot writeCannot write it as: ( A and B)because this will return a 'std_logic' type (more on types later).

Use of Use of if-elseif-elseARCHITECTURE ifelse of majority is

begin process (A, B, C) begin if (((A = '1') and (B = '1')) or ((A = '1') and (C = '1')) or ((B = '1') and (C = '1')) ) then Y <= '1'; else Y <= '0'; end if;

end process;end ifelse;

Comments:Process is anonymous (noname)Used an 'else' clause to specifywhat the output should be ifthe if condition test was nottrue.

CAREFUL!CAREFUL! use parenthesis to defineprecedence order


process

Generic ClauseGeneric Clause■ Generic Clause Example :

– The generic My_ID, with a default value of 37, can bereferenced by any architecture of the entity with thisgeneric clause

– The default can be overridden at component instantiation

GENERIC (My_ID : INTEGER := 37);GENERIC (My_ID : INTEGER := 37);

GENERIC can betime, current,

voltage, signal…..

Architecture BodiesArchitecture Bodies

■ Describes the Operation of theComponent, Not Just Its Interface

■ More Than One Architecture Can (andUsually Is) Associated With EachEntity

Architecture BodiesArchitecture Bodies

■ Architecture Body consists of Two Parts:1. Declarative part -- includes necessary

declarations, e.g. :»type declarations

»signal declarations

»component declarations

»subprogram declarations

Architecture BodiesArchitecture Bodies2. Statement part -- includes statements that

describe organization and/or functionaloperation of component, e.g. :

»» concurrent signal assignment concurrent signal assignmentstatementsstatements

»» process statements process statements

»» component instantiation statements component instantiation statements

Architecture Body ExampleArchitecture Body Example

ARCHITECTURE half_adder_d OF half_adderIS

-- architecture declarative part

SIGNAL xor_res : BIT ;

-- architecture statement part

BEGIN

carry <= enable AND (x AND y) ;

result <= enable AND xor_res ;

xor_res <= x XOR y ;

END half_adder_d ;

Lexical Elements of VHDLLexical Elements of VHDL

■ Comments– two dashes to end of line is a comment, e.g.,

--this is a comment

Copyright 1997, KJH

Lexical Elements of VHDLLexical Elements of VHDL■ Basic Identifiers

– Can Only Use» alphabetic letters ( A-Z, a-z ), or

» Decimal digits ( 0-9 ), or

» Underline character ( _ )

– Must Start With Alphabetic Letter ( MyVal )

Copyright 1997, KJH

Lexical Elements of VHDLLexical Elements of VHDL■ Basic Identifiers

– Not case sensitive( LastValue = = lAsTvALue)

– May NOT end with underline ( MyVal_ )

– May NOT contain sequential underlines (My__Val)

Copyright 1997, KJH

Not case sensitive, but recommended to usealways the same way. It is also

recommended to use capitals for languagecomponents

Lexical Elements of VHDLLexical Elements of VHDL■ Extended Identifiers

– Any character(s) enclosed by \ \

– Case IS significant in Extended Identifiers

– Extended identifiers are distinct from basic identifiers

– If “ \ ” is needed in extended identifier, use

“ \\ “

Copyright 1997, KJH

Lexical Elements of VHDLLexical Elements of VHDL■ Reserved Words

– Do not use as identifiers

■ Special Symbols– Single characters

& ‘ ( ) * + , - . / : ; < = > |

– Double characters (no intervening space)

=> ** := /= >= <= <>

Lexical Elements of VHDLLexical Elements of VHDL■ Numbers

– Underlines are NOT significant

( 10#8_192 )

– Exponential notation allowed

( 46e5 , 98.6E+12 )

– Integer Literals ( 12 )» Only positive numbers; negative numbers are

preceded by unary negation operator

» No radix pointCopyright 1997, KJH

Lexical Elements of VHDLLexical Elements of VHDL– Real Literals ( 23.1 )

»Always include decimal point

»Radix point must be preceded and followed byat least one digit.

– Radix ( radix # number expressed in radix)»Any radix from binary ( 2 ) to hexadecimal (16 )

»Numbers in radices > 10 use letters a-f for10-15.

Lexical Elements of VHDLLexical Elements of VHDL

■ Characters– Any printable character including space enclosed

in single quotes ( ‘x‘ )

■ Bit Strings– B for binary ( b”0100_1001” )

– O for Octal ( o”76443” )

– X for hexadecimal ( x”FFFE_F138” )

Characters, bits strings and strings are not thesame thing!

VHDL SyntaxVHDL Syntax■ Extended Backus-Naur Form (EBNF)

– Language divided into syntactic categories

– Each category has a rule describing how to build arule of that category

– Syntactic category <= pattern– “<=“ is read as “...is defined to be...”

Copyright 1997, KJH

VHDL SyntaxVHDL Syntax– e.g.,

variable_assignment <= target :=expression;

– Above, a clause of the categoryvariable_assignment is defined to be a clausefrom the category target followed by the symbol “:= “ followed by a clause from the expressioncategory followed by a terminating “ ; ”

VHDL SyntaxVHDL Syntax– A preceding lexical element can be repeated an

arbitrary number of times if ellipses are present,e.g.,

case-statement <=

CASE expression IS

case_statement_alternative

{ . . . }

END CASE ;

Copyright 1997, KJH

repeated

VHDL SyntaxVHDL Syntax■ “OR” operator, “ | | | ”, in a list of alternatives,

e.g.,mode <= IN | OUT | INOUT

■ When grouping is ambiguous, parenthesisare used, e.g.,

term <=

factor { ( * | / | MOD | REM ) FACTOR }

Copyright 1997, KJH

Do not bother to remember operatorprecedence rules, just use parentheses

NEW EXAMPLENEW EXAMPLE: 4-to-1: 4-to-1 mux mux with 8 with 8bitbit Datapaths Datapaths

library ieee;use ieee.std_logic_1164.all;entity mux4to1_8 is port ( a,b,c,d : in std_logic_vector(7 downto 0); sel: in std_logic_vector (1 downto 0); dout: out std_logic_vector(7 downto 0) );end mux4to1_8;architecture whenelse of mux4to1_8 isbegindout <= b when (sel = "01") else c when (sel = "10") else d when (sel = "11") else a; -- default

end process;end whenelse;

8

sel

We do not use with

dout82

a b c d

Comments on Comments on Mux Mux exampleexample• This is one way to write a mux,

but is not the best way.

• The when-else structure hereis actually a priority structure.

– A mux has no prioritybetween inputs, just asimple selection.

– The synthesis tool has towork harder than necessaryto understand that allpossible choices for sel arespecified and that nopriority is necessary.

• Just want a simple selectionmechanism.

library ieee;use ieee.std_logic_1164.all;entity mux4to1_8 is port ( a,b,c,d : in std_logic_vector(7 downto 0); sel: in std_logic_vector (1 downto 0); dout: out std_logic_vector(7 downto 0) );end mux4to1_8;architecture whenelse of mux4to1_8 isbegindout <= b when (sel = "01") else c when (sel = "10") else d when (sel = "11") else a; -- default

end process;end whenelse;

A better way uses “A better way uses “with”with”

repeated

4-to-14-to-1 Mux Mux using Select Concurrent using Select ConcurrentStatementStatement

architecture select_statement of mux4to1_8 isbeginwith sel select dout <= b when "01", c when "10", d when "11", a when others;end select_statementselect_statement;

• Some synthesis tools will automatically recognize this structure (usingwith) as a muxmux•They will find a more efficient implementation than using a when-elseor if statement structure• Remember in general that when-else and if structures define priorityprioritystructures for compilationstructures for compilation.

4-to-14-to-1 Mux Mux using using SelectSelect Concurrent ConcurrentStatementStatement

architecture select_statement of mux4to1_8 isbeginwith sel select dout <= b when "01", c when "10", d when "11", a when othersothers;end select_statement;

• The others case must be specified.• This is a concurrent statement, no process.• The sequential version of the select statementis the case statement.

continued

4-to-14-to-1 Mux Mux using using CaseCase Sequential SequentialStatementStatement

architecture select_statement of mux4to1_8 isbegin

process (a, b, c, d, sel) begin case sel is when "01" => dout <= b ; when "10" => dout <= c; when "11" => dout <= d; when others => dout <= a; end case; end process;end select_statement;

•There can be multiplestatements for each case;• only one statement isneeded for each case in thisexample.

Uses process, it is sequential

Concurrent => use select

Sequential => use case

Pay attention to this arrow, how itis directed

Logical Shift Left by 1Logical Shift Left by 1library ieee;use ieee.std_logic_1164.all;entity lshift is port ( din : in std_logic_vector(7 downto 0); shift_en: in std_logic; dout: out std_logic_vector(7 downto 0) );end lshift;architecture brute_force of lshift isbegin

process (din, shift_en)begin dout <= din; -- default case if (shift_en = '1') then dout(0) <= '0'; -- shift a zero into LSB dout (1) <= din(0); dout (2) <= din(1); dout (3) <= din(2); dout (4) <= din(3); dout (5) <= din(4); dout (6) <= din(5); dout (7) <= din(6); end if; end process;end brute_force;end lshift;

This is one way to do it; surely there is a better way?

Din(7:0)

Dout(7:0)

7 6 5 4 3 2 1 0

Logical Shift Left by 1 (better way)Logical Shift Left by 1 (better way)

architecture better of lshift isbeginprocess (din, shift_en)begin dout <= din; -- default case if (shift_en = '1') then dout(0) <= '0'; -- shift a zero into LSB dout (7 downto 1) <= din(6 downto 0); end if; end process;end better;end lshift;

• This illustrates the assignment of a segment of one bus to another bussegment.• The bus ranges on each side of the assignment statement must be thename number of bits (each 6 bits in this case).

4 Bit Ripple Carry Adder4 Bit Ripple Carry Adder

A B

S

CiCo

A B

S

CiCo

A B

S

CiCo

A B

S

CiCo Cin

A(0)

Cout

B(0)A(1) B(1)A(2) B(2)A(3) B(3)

C(0)C(1)C(2)C(3)C(4)

Sum(0)Sum(1)Sum(2)Sum(3)

Want to write a VHDL model for a 4 bit ripple carry adder. Logic equation for each full adder is: sum <= a xor b xor ci; co <= (a and b) or (ci and (a or b));

4 Bit Ripple Carry Model4 Bit Ripple Carry Modellibrary ieee;use ieee.std_logic_1164.all;entity adder4bit is port ( a,b: in std_logic_vector(3 downto 0); cin : in std_logic; cout: out std_logic; sum: out std_logic_vector(3 downto 0) );end adder4bit;architecture bruteforce of adder4bit is -- temporary signals for internal carries signal c : std_logic_vector(4 downto 0); .begin process (a, b, cin, c) begin c(0) <= cin; -- full adder 0 sum(0) <= a(0) xor b(0) xor c(0); c(1) <= (a(0) and b(0)) or (c(0) and (a(0) or b(0))); -- full adder 1 sum(1) <= a(1) xor b(1) xor c(1); c(2) <= (a(1) and b(1)) or (c(1) and (a(1) or b(1)));

-- full adder 2 sum(2) <= a(2) xor b(2) xor c(2); c(3) <= (a(2) and b(2)) or (c(2) and (a(2) or b(2))); -- full adder 3 sum(3) <= a(3) xor b(3) xor c(3); c(4) <= (a(3) and b(3)) or (c(3) and (a(3) or b(3))); cout <= c(4);end process;end bruteforce;

••Straight forwardStraight forwardimplementation.implementation.••Nothing wrong with this.Nothing wrong with this.••However, is there an However, is there an easiereasierway?way?

Not very elegant for longwords, not scalable

4 Bit Ripple Carry Model4 Bit Ripple Carry Modelusing using For For StatementStatement

architecture forloop of adder4bit is

signal c : std_logic_vector(4 downto 0); -- temporary signals for internal carries.begin process (a, b, cin, c) begin c(0) <= cin; for i in 0 to 3 loop -- all four full adders sum(i) <= a(i) xor b(i) xor c(i); c(i+1) <= (a(i) and b(i)) or (c(i) and (a(i) or b(i))); end loop; cout <= c(4); end process;end forloop;

Index “i” is not a signal , not avariable.

Comments on Comments on for-loop for-loop statementstatement• To visualize what logic is created, 'unroll' the loop by

writing down each loop iteration with loop indicesreplaced hard numbers.

architecture forloop of adder4bit is

signal c : std_logic_vector(4 downto 0); -- temporary signals for internal carries.begin process (a, b, cin, c) begin c(0) <= cin; for i in 0 to 3 loop -- all four full adders sum(i) <= a(i) xor b(i) xor c(i); c(i+1) <= (a(i) and b(i)) or (c(i) and (a(i) or b(i))); end loop; cout <= c(4); end process;end forloop;

The for-loop can be used to repeat blocks of logic

The loop variable i is implicity declared for this loop; does not have tobe declared anywhere else.

VHDL-IIStructuralModeling

VariablesVariables■ Variables Exist Only Within an

Architecture– Values of variables cannot be passed to other

entities except through signals

■ Variables Change Value When They AreEvaluated.– Signals change at a “later” time

SignalsSignals■ Entities are Interconnected by Signals

– Process executions result in new values being assigned tosignals which are then accessible to other processes

– A signal may be accessed by a process in anotherby a process in anotherarchitecturearchitecture by connecting the signal to ports in theentities associated with the two architectures

SignalsSignals■ Signals Can Be Declared Internal to an

Architecture to Connect Internal Entities

■ Variables Are Not Appropriate Since They Do NotHave the Temporal Characteristics of Hardware

■ Signals Declared Within an Entity Are NotAvailable to Other Entities Unless Specified in thePort Clause of the Entity Declaration.

Entity SyntaxEntity SyntaxENTITY identifier IS

[ PORT ( port_interface_list ); ]

{ entity_declarative_item }

END [ ENTITY ] [ identifier ] ;

Entity SyntaxEntity Syntaxport_interface_list <=

( identifier { , . . . } :

[ mode ] subtype_indication

[ := expression ] )

{ ; . . . }

mode <= IN | OUT | INOUT

Entity ExampleEntity ExampleENTITY NiCadCharger IS

PORT (

Voltage, Current : IN REAL := 0.0 ;

AC : IN BIT := ‘1’ ;

Charged, Recharge: OUT BIT );

END ENTITY NiCadCharger ;

mode

Architecture SyntaxArchitecture SyntaxARCHITECTURE identifier OF

entity_name IS

{ block_declarative_item }

BEGIN

{ concurrent_statement }

END [ARCHITECTURE][ identifier ];

Structural ModelStructural Model■ A Representation of a System in

Terms of the Interconnections of a Setof Defined Components.– Components can be described either

structurally or behaviorally

– Smallest components are behavioralentities

– Components usually stored in libraries

Structural ModelsStructural Models■ Components Can Be Instantiated As

Concurrent Statements in Architectures– If architecture not specified in statement

»Must be specified later, or

»Most recently analyzed architecture used

– Ports can be specified two ways»Positional association

»Named association

Internal Signals in aInternal Signals in aStructural ModelStructural Model

■ Entity Ports Which are Declared withinan Architecture Body Are Local Signals– These signals are not available outside the

architecture unless connected to one of thearchitecture’s ports

Odd Parity GeneratorOdd Parity GeneratorExampleExample

ParityParityEntityEntity

ENTITY Odd_Parity IS

PORT(

IN_1, IN_2, IN_3 : IN BIT ;

Out_1 : OUT BIT );

END ENTITY Odd_Parity ;

Odd Parity Behavior ArchitectureOdd Parity Behavior ArchitectureARCHITECTURE Odd_Parity_B OF

Odd_Parity IS

BEGIN

Out_1 <= ( IN_1 AND NOT IN_2 AND IN_3 )

OR ( NOT IN_1 AND NOT IN_2 AND NOT IN_3 )

OR ( NOT IN_1 AND IN_2 AND IN_3 )

OR ( IN_1 AND IN_2 AND NOT IN_3 )

END ARCHITECTURE Odd_Parity_B ;

( )f A B C ABC ABC ABC ABCodd , , = + + +

INVERTER Entity andINVERTER Entity andArchitectureArchitecture

ENTITY INV IS

PORT(

In_1 : IN BIT ;

In_1_Bar : OUT BIT );

END ENTITY INV ;

ARCHITECTURE INV_B OF INV IS

BEGIN

In_1_Bar <= NOT IN_1 ;

END ARCHITECTURE INV_B ;

AND_3 Entity/ArchitectureAND_3 Entity/ArchitectureENTITY AND_3 IS

PORT(

IN_1, IN_2, IN_3 : IN BIT ;

Out_1 : OUT BIT );

END ENTITY AND_3 ;

ARCHITECTURE AND_3_B OF AND_3 IS

BEGIN

Out_1 <= IN_1 AND IN_2 AND IN_3 ;

END ARCHITECTURE AND_3_B ;

OR_4 Entity/ArchitectureOR_4 Entity/ArchitectureENTITY OR_4 IS

PORT(

IN_1, IN_2, IN_3, IN_4 : IN BIT ;

Out_1 : OUT BIT );

END ENTITY OR_4 ;

ARCHITECTURE OR_4_B OF OR_4 IS

BEGIN

Out_1 <= IN_1 OR IN_2 OR IN_3 OR IN_4 ;

END ARCHITECTURE OR_4_B ;

Odd Parity Structural ArchitectureOdd Parity Structural Architecture

ARCHITECTURE Odd_Parity_S OF

Odd_Parity IS

--block_declarative_items

--components

COMPONENT INV IS

PORT(

In_1 : IN BIT ;

In_1_Bar : OUT BIT );

END COMPONENT INV ;


COMPONENT AND_3 IS

PORT( IN_1, IN_2, IN_3 : IN BIT ;

Out_1 : OUT BIT );

END COMPONENT AND_3 ;

COMPONENT OR_4 IS

PORT( IN_1, IN_2, IN_3, IN_4 : IN BIT ;

Out_1 : OUT BIT );

END COMPONENT OR_4 ;

Structural MappingStructural Mapping

inv_1

MT_5

inv_2

inv_3

in_2

in_1

in_3

MT_0

MT_3

MT_6

Out_1

For single-output gates the name ofthe signal is the same as the name of

the gate These namesare necessary

to connectcomponents


--block_declarative_items

--internal signals

SIGNAL MT_0, MT_3, MT_5, MT_6 : BIT ;

SIGNAL INV_1, INV_2, INV_3 : BIT ;

BEGIN --parity structural architecture

--connect gates

G1: INV PORT MAP ( In_1, INV_1 );




G4: AND_3 PORT MAP

( IN_1, INV_2, IN_3, MT_5 );

G5: AND_3 PORT MAP

( INV_1, INV_2, INV_3, MT_0 );

G6: AND_3 PORT MAP

( INV_1, IN_2, IN_3, MT_3 );

G7: AND_3 PORT MAP

( IN_1, IN_2, INV_3, MT_6 );


G8: OR_4 PORT MAP

( MT_0, MT_3, MT_5, MT_6, Out_1 );

END ARCHITECTURE Odd_Parity_S ;

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