vhdl lecture notes - navabi

CHAPTER 1 1 1999, Z. Navabi and McGraw-Hill Inc.

Chapter 1Hardware design environments

1.1 DIGITAL SYSTEM DESIGN PROCESS1.1.1 Design Automation

1.2 The Art of Modeling1.3 HARDWARE DESCRIPTION LANGUAGES

1.3.1 A Language for Behavioral Descriptions1.3.2 A Language for Describing Flow of Data1.3.3 A Language for Describing Netlists

1.4 HARDWARE SIMULATION1.4.1 Oblivious Simulation1.4.2 Event Driven Simulation

1.5 HARDWARE SYNTHESIS TEST APPLICATIONS1.6 LEVELS OF ABSTRACTION1.7 SUMMARY


A digital system design process

Design Idea

Behavioral Design

Data Path Design

Logic Design

Physical Design

Manufacturing

Chip or Board

Flow Graph, Pseudo Code, ..

Bus & Register Structure.

Gate Wirelist, Netlist.

Transistor List, Layout, ...

• Top-down design process• Starting with a design idea• Generating a chip or board


Result of the data path design phase.

Procedurefor Controlof Movementof Data BetweenRegistersand Buses.

CONTROLDATA

REG1 REG2

REG3

LOGIC

MAINLOGICUNIT

. . . . . .

• Dataflow description• Control Data partitioning

An ISPS example, a simple processor.

mark1 := BEGIN ** memory.state ** m[0:8191]<31:0>, ** processor.state ** pi\present.instruction<15:0>' f\function<0:2> := pi<15:13>, s<0:12> := pi<12:0>, cr\control.register<12:0>, acc\accumulator<31:0>, ** instruction.execution ** tcMAIN i.cycle := BEGIN pi = m[cr]<15:0> NEXT DECODE f => BEGIN 0\jmp := cr = m[s], 1\jrp := cr = cr + m[s], 2\ldn := acc = - m[s], 3\sto := m[s] = acc, 4:5\sub := acc = acc - m[s], 6\cmp := IF acc LSS 0 => cr = cr + 1, 7\stp := STOP(), END NEXT cr = cr + 1 NEXT RESTART i.cycle END

• Behavioral Example• Only describing functionality

An AHPL example, a sequential multiplier.

AHPLMODULE: multiplier. MEMORY: ac1[4]; ac2[4]; count[2]; extra[4]; busy. EXINPUTS: dataready. EXBUSES: inputbus[8]. OUTPUTS: result[8]; done. CLUNITS: INC[2](count); ADD[5](extra; ac2);1 ac1 <= inputbus[0:5]; ac2 <= inputbus[4:7];

extra <= 4$0;=> ( ^dataready, dataready ) / (1, 2).

2 busy <= \1\;=> ( ^ac1[3], ac1[3] ) / (4, 3).

3 extra <= ADD[1:4] (extra; ac2).4 extra, ac1 <= \0\, extra, ac1[0:2];

count <= INC(count);=> ( ^(&/count), (&/count) ) / (2, 5).

5 result = extra, ac1; done = \1\; busy <= \0\;=> (1).

ENDSEQUENCE CONTROLRESET(1).END.

• Dataflow description• Describing clock control timing• AHPL, A Hardware Programming Language


Full-adder, logical diagram and Verilog code.

g1

g2

g3

g4

g5

g6

a

b

cs

co

w1

w2

w3

w4

`timescale 1 ns / 1 ns// A 6-gate full adder; this is a commentmodule fulladder (s, co, a, c, c); // Port declarations output s, co; input a, b, c; // Intermediate wires wire w1, w2, w3, w4; // Netlist description xor #(16, 12) g1 (w1, a, b); xor #(16, 12) g5 (s, w1, c); and #(12, 10) g2 (w2, c, b); and #(12, 10) g3 (w3, c, a); and #(12, 10) g4 (w4, b, a); or #(12, 10) g6 (co, w2, w3, w4);endmodule

• Gate level structural description• Describes gate level timing• Graphical and language based descriptions


Hardware simulation.

• Hardware simulation process• Component models, unit model form hardware model• Testbench may provide test data

SimulationEngine

Test Data(Stimuli)

ComponentLibrary(Models)

HardwareDescription(Model)

SimulationResults(Output)

SimulationHardwareModel


Verifying each design stage.

Design Idea

Behavioral Design

Data Path Design

Logic Design

Physical Design

Manufacturing

Chip or Board

Flow Graph, Pseudo Code, ..

Bus & Register Structure.

Gate Wirelist, Netlist.


SIMULATION TOOLS

Behavioral Simulator

Dataflow Simulator

Gate Level Simulator

Device Simulator

Final Testing

Product Sample.

• Simulate at each step• Simulate to verify translation into lower level• Simulation cost increases at lower levels


Simulating an exclusive-OR

z

a

b

1

2

3

4

5

6

7

0 1 2 3 4 5 6 7 8 9 0t

a

b

• Simulating an XOR• Apply data at given time intervals or• Apply data as events occur


Oblivious simulation.

GATE FUNCTION INPUT 1 INPUT 2 VALUE1 Input a -- 02 Input b -- 03 NOT 2 -- 14 NOT 1 -- 15 AND 1 3 06 AND 4 2 07 OR 5 6 0

• Table representation• Simulate until no changes are made• Record values at table entries


Event driven simulation.

- Inp 0 - NOT 0 AND 0

- Inp 0 - NOT 0 AND 0

OR 0

Legend:

In1 In2 Fnc Out

1 3 5

2 4 6

In1: Input 1; In2: Input2; Fnc: Function; Out: Output Value

a

b

• Linked list representation• Simulate links with input events• Record values at node entries


Categories of synthesis tools.

Behavioral Design

Data Path Design

Logic Design

Physical Design

Manufacturing

Design Idea

Chip or Board

Flow Graph, Pseudo Code, ...

Bus & Register Structure


1

2

3

4

5

6

SYNTHESIS TOOLS

• Synthesis• Transformation from one level to another• Ideal is 6, most commercial tools are 2


Synthesis process.

• Hardware description and directives are tool inputs• Three synthesis stages• Layout or netlist is generated

Synthesis Engine

SynthesisDirectives

SynthesisHardwareDescription

SynthesizedHardware(Netlist)

SynthesizableModel

SchedulingLogic

Optimization Binding

Resource sharing.

• Input description affects synthesis results• Explicit specification of resource sharing• Sharing without and with extra overhead

c <= a + b;d <= a + b;

ADDER

a b

d

ADDER

a

x

b

c <= a + b;c <= x + y;

c

c

y


Chapter 2VHDL Background

2.1 VHDL INITIATION2.2 EXISTING LANGUAGES

2.2.1 AHPL2.2.2 CDL2.2.3 CONLAN2.2.4 IDL2.2.5 ISPS2.2.6 TEGAS2.2.7 TI-HDL2.2.8 ZEUS

2.3 VHDL REQUIREMENTS2.3.1 General Features2.3.2 Support for Design Hierarchy2.3.3 Library Support2.3.4 Sequential Statement2.3.5 Generic Design2.3.6 Type Declaration and Usage2.3.7 Use of Subprograms2.3.8 Timing Control2.3.9 Structural Specification

2.4 THE VHDL LANGUAGE2.5 SUMMARY


VHDL Initiation

• 1981 DoD Woods Hole MA : Workshop on HDLs• Part of VHSIC program


VHDL Initiation

• 1981 DoD Woods Hole MA : Workshop on HDLs ITARrestrictions

• 1983 DoD : Requirements were established Contract wasawarded to IBM, TI, Intermetrics ITAR restrictions removedfrom language

• 1984 IBM, TI, Intermetrics : VHDL 2.0 was defined

• December 1984 : VHDL 6.0 was released Softwaredevelopment started

• 1985 : VHDL 7.2 was released to IEEE ITAR removed fromsoftware

• May 1985 : Standard VHDL 1076/A

• December 1987 : VHDL 1076-1987 became IEEE standard

• 1993 : VHDL 1076-1993 was approved


Languages reviewed

• AHPL : A Hardware Programming Language

• CDL : Computer Design Language

• CONLAN : CONsensus LANguage

• IDL : Interactive Design Language

• ISPS : Instruction Set Processor Specification

• TEGAS : TEst Generation And Simulation

• TI-HDL : TI Hardware Description Language

• ZEUS : An HDL by GE corpration


VHDL Requirements

• General FeaturesDocumentation, High level design, Simulation,Synthesis, Test, Automatic hardware

• Design HierarchyMulti-level descriptionPartitioning

• Library SupportStandard PackagesCell based design

• Sequential StatementsBehavioral software-like constructs


VHDL Requirements

• Generic DesignBinding to specific libraries

• Type DeclarationStrongly typed language

• Subprograms

• TimingDelays, concurrency

• Structural SpecificationWiring components


VHDL Requirements

STACK ALUMUX

COUNTER

CPU

BIT

0BIT BIT

n n-1

ADDER LOGIC

ALU

ALU_BIT

MUX

AND OR NOT

MUX

• Use various levels of abstraction for defining a system• Upper level systems are partitioned into lower


Example for hierarchical partitioning.

STACK ALUMUX

COUNTER

CPU

BIT

0BIT BIT

n n-1

ADDER LOGIC

ALU

AL U_BI T

M UX

AND OR NOT

MUX

• Recursive partitioning• Simple components as terminals


An example VHDL environment.

Design Libraries

Lib. 1

.2

.3

LIBRARY SYSTEM VHDLSimulator

LayoutSynthesizer

NetlistSynthesizer

Other Tools

Analyzer

Library Environment

VHDL Input

LibraryManagement

• VHDL defines library usage• Tools define library management


Chapter 3Design Methodology Based on VHDL

3.1 ELEMENTS OF VHDL3.1.1 Describing Components3.1.2 Packages3.1.3 Libraries and Binding

3.2 TOP-DOWN DESIGN3.2.1 Verification3.3 TOP-DOWN DESIGN WITH VHDL

3.3.1 Design to Perform3.3.2 Setting The Stage3.3.3 Design Scenario3.3.4 Final Act3.3.5 Real World

3.4 SUBPROGRAMS3.5 CONTROLLER DESCRIPTION3.6 VHDL OPERATORS3.7 CONVENTIONS AND SYNTAX3.8 SUMMARY


Interface and architectural specifications.

ENTITY component_name IS input and output ports. physical and other parameters.END component_name;

ARCHITECTURE identifier OF component_name IS declarations.BEGIN specification of the functionality of the component in terms of its input lines and influenced by physical and other parameters.END identifier;


Multiple architectural specifications.

ARCHITECTUREbehavioral

OFcomponent_i

IS. . .

ARCHITECTUREdataflow

OFcomponent_i

IS. . .

ARCHITECTUREstructural

OFcomponent_i

IS. . .

otherARCHITECTURES

OFcomponent_i

. . .

. . .

. .

. .

. .

. .

ENTITY component_i IS PORT (. . )


Packages.

PACKAGE package_name IS component declarations. sub-program declasrations.END package_name;

PACKAGE BODY package_name IS type definitions. sub-programs.END package_name;


Design binding.

LIBRARY library_name;

CONFIGURATION configuration_name OF component_name IS binding of Entities and Architectures. specifying parameters of a design. binding components of a library to subcomponents.END CONFIGURATION;


Recursive partition procedure.

Partition (system)IF HardwareMappingOf (system) IS done THEN SaveHardwareOf (system) ELSE FOR EVERY Functionally-Distinct part_i OF system Partition (part_i); END FOR; END IF;END Partition;


Top-down design, bottom-up implementation.

SUD

SSC1 SSC2 SSC3 SSC4

SSC31 SSC3n SSC41 SSC42

SSC311 SSC312 SSC3n1 SSC3n2

...

SUD: System Under DesignSSC : System Sub-ComponentShaded areas designate sub-componts withhardware implementation.

Des

ign

Impl

emen

tatio

n


Verifying the first level of partitioning.

SUD

SSC1 SSC2 SSC3 SSC4

Interconnection of Behavioral Models

Behavioral Model

Compare


Verifying hardware implementation.

SUD

SSC1 SSC2 SSC3 SSC4

Behavioral Model

Compare

Mixed Level Model


Verifying the final design.

SUD

SSC1 SSC2 SSC3 SSC4

SSC31 SSC3n SSC41 SSC42

SSC311 SSC312

...

Behavioral Model

Compare

Hardware Model


Verifying hardware implementation of SSC3.

SSC31

SSC311 SSC312 . . .

SSC3n

SSC3n1 SSC3n2

. . .

SSC3

Compa

re

Behavioral Model

Hardware Model


Verifying the final design.

SUD

SSC1 SSC2 SSC3 SSC4

SSC41 SSC42

Compare

Mixed Level Model

Verifying the final design, an alternative to the setup of Figure 3.9.


Serial adder.

Synchronously add data on a and bput result on result.

a

b

start

clock

result

ready


Available library elements.

S1

1D

1D

Z_

(a) Multiplexer

1R

1D

C1

Q

(b) Flipflop

Multiplexer library element.

VHDL model of the multiplexer library element.

ENTITY mux2_1 IS GENERIC (dz_delay : TIME := 6 NS); PORT (sel, data1, data0 : IN BIT; z : OUT BIT);END mux2_1;--ARCHITECTURE dataflow OF mux2_1 ISBEGIN z <= data1 AFTER dz_delay WHEN sel = '1' ELSE data0 AFTER dz_delay;END dataflow;


Dataflow descriptions.

Controller

Busb

Alu

Busa

Reg File Reg1

Reg2

Dataflow descriptions.

Flip-flop library element.

VHDL model of the flip-flop library element.

ENTITY flop IS GENERIC (td_reset, td_in : TIME := 8 NS); PORT (reset, din, clk : IN BIT; qout : BUFFER BIT := '0');END flop;--ARCHITECTURE behavioral OF flop ISBEGIN PROCESS (clk) BEGIN IF (clk = '0' AND clk'EVENT) THEN IF reset = '1' THEN qout <= '0' AFTER td_reset; ELSE qout <= din AFTER td_in; END IF; END IF; END PROCESS;END behavioral;


Behavioral descriptions.

Receive

FOR all data :Process data :Queue data :

END FOR;

. . .

Transmit

Valid?

Behavioral descriptions.

Divide by 8, counter.

Divide by 8, counter.

ENTITY counter IS GENERIC (td_cnt : TIME := 8 NS); PORT (reset, clk : IN BIT; counting : OUT BIT := '0'); CONSTANT limit : INTEGER := 8;END counter;--ARCHITECTURE behavioral OF counter ISBEGIN PROCESS (clk) VARIABLE count : INTEGER := limit; BEGIN IF (clk = '0' AND clk'EVENT) THEN IF reset = '1' THEN count := 0; ELSE IF count < limit THEN count := count + 1; END IF; END IF; IF count = limit THEN counting <= '0' AFTER td_cnt; ELSE counting <= '1' AFTER td_cnt; END IF; END IF; END PROCESS;END behavioral;


Design stage setting.

CMOS layout l a y o u t s

flop

mux2-1library

predesigned

CountSynthesize

VHDL Boolean

Serial adder behavioral description.

Serial adder behavioral description.

ENTITY serial_adder IS PORT (a, b, start, clock : IN BIT; ready : OUT BIT; result : BUFFER BIT_VECTOR (7 DOWNTO 0));END serial_adder;--ARCHITECTURE behavioral OF serial_adder ISBEGIN PROCESS (clock) VARIABLE count : INTEGER := 8; VARIABLE sum, carry : BIT; BEGIN IF (clock = '0' AND clock'EVENT) THEN IF start = '1' THEN count := 0; carry := '0'; ELSE IF count < 8 THEN count := count + 1; sum := a XOR b XOR carry; carry := (a AND b) OR (a AND carry) OR (b AND carry); result <= sum & result (7 DOWNTO 1); END IF; END IF; IF count = 8 THEN ready <= '1'; ELSE ready <= '0'; END IF; END IF; END PROCESS;END behavioral;


VHDL simulation results.

Partial code of serail_adder.

ELSE

IF count < 8 THEN

count := count + 1;

sum := a XOR b XOR carry;

carry := (a AND b) OR (a AND carry) OR (b AND carry );

result <= sum & result (7 DOWNTO 1);

END IF;


General layout of serial_adder.

counter

Shift Regiser

Flop

Adder

carry_in

carry_out

ensi

clock

result

counting

a

b

serial_sum


First level of partitioning.

counterfull_adder flip_flop shifter

serial_adder

Full_adder description.

ENTITY fulladder IS PORT (a, b, cin : IN BIT; sum, cout : OUT BIT);END fulladder;--ARCHITECTURE behavioral OF fulladder ISBEGIN sum <= a XOR b XOR cin; cout <= (a AND b) OR (a AND cin) OR (b AND cin);END behavioral;

Shifter VHDL description.

ENTITY shifter IS PORT (sin, reset, enable, clk : IN BIT; parout : BUFFER BIT_VECTOR (7 DOWNTO 0));END shifter;--ARCHITECTURE dataflow OF shifter ISBEGIN sh: BLOCK (clk = '0' AND clk'EVENT) BEGIN parout <= "00000000" WHEN reset = '1' ELSE sin & parout (7 DOWNTO 1) WHEN enable = '1' ELSE UNAFFECTED; END BLOCK;END dataflow;


Completed parts of first partitioning.

flop shifter counter

serial_adder

full_adder

Structural description of serial_adder.

ENTITY serial_adder IS PORT (a, b, start, clock : IN BIT; ready : OUT BIT; result : BUFFER BIT_VECTOR (7 DOWNTO 0));END serial_adder;--ARCHITECTURE structural OF serial_adder IS COMPONENT counter IS GENERIC (td_cnt : TIME := 8 NS); PORT (reset, clk : IN BIT; counting : OUT BIT := '0'); END COMPONENT; COMPONENT shifter IS PORT (sin, reset, enable, clk : IN BIT; parout : BUFFER BIT_VECTOR(7 DOWNTO 0)); END COMPONENT; COMPONENT fulladder IS PORT (a, b, cin : IN BIT; sum, cout : OUT BIT); END COMPONENT; COMPONENT flop IS GENERIC (td_reset, td_in : TIME := 8 NS); PORT (reset, din, clk : IN BIT; qout : BUFFER BIT := '0'); END COMPONENT; -- SIGNAL serial_sum, carry_in, carry_out, counting : BIT;BEGIN u1 : fulladder PORT MAP (a, b, carry_in, serial_sum, carry_out); u2 : flop PORT MAP (start, carry_out, clock, carry_in); u3 : counter PORT MAP (start, clock, counting); u4 : shifter PORT MAP (serial_sum, start, counting, clock, result); u5 : ready <= NOT counting;END structural;


Signal mapping for fulladder instantiation.

Signals in structural architecture of serial_adder

a b carry_in serial_sum carry_out

a b cin sum count

Signals in the interface of fulladder


Interconnecting ports.

COMPONENT fulladder IS

PORT (a, b, cin : IN BIT; sum, cout : OUT BIT);

END COMPONENT;

COMPONENT flop IS

GENERIC (td_reset, td_in : TIME := 8 NS);

PORT (reset, din , clk : IN BIT; qout : BUFFER BIT := '0');

END COMPONENT; -- SIGNAL serial_sum, carry_in, carry_out, counting : BIT;

BEGIN

u1 : fulladder PORT MAP (a, b, carry_in, serial_sum, carry_out );

u2 : flop PORT MAP (start, carry_out , clock, carry_in);


Partitioning shifter.

shifter

der_flop der_flop der_flop der_flop der_flop der_flop der_flop der_flop

..

.

Behavioral model of der_flop.

ENTITY der_flop IS PORT (din, reset, enable, clk : IN BIT; qout : OUT BIT := '0');END der_flop;--ARCHITECTURE behavioral OF der_flop ISBEGIN PROCESS (clk) BEGIN IF (clk = '0' AND clk'EVENT) THEN IF reset = '1' THEN qout <= '0'; ELSE IF enable = '1' THEN qout <= din; END IF; END IF; END IF; END PROCESS;END behavioral;


Structural description of shifter.

ENTITY shifter IS PORT (sin, reset, enable, clk : IN BIT; parout : BUFFER BIT_VECTOR (7 DOWNTO 0));END shifter;--ARCHITECTURE structural OF shifter IS COMPONENT der_flop IS PORT (din, reset, enable, clk : IN BIT; qout : BUFFER BIT := '0'); END COMPONENT;BEGIN b7 : der_flop PORT MAP ( sin, reset, enable, clk, parout(7)); b6 : der_flop PORT MAP (parout(7), reset, enable, clk, parout(6)); b5 : der_flop PORT MAP (parout(6), reset, enable, clk, parout(5)); b4 : der_flop PORT MAP (parout(5), reset, enable, clk, parout(4)); b3 : der_flop PORT MAP (parout(4), reset, enable, clk, parout(3)); b2 : der_flop PORT MAP (parout(3), reset, enable, clk, parout(2)); b1 : der_flop PORT MAP (parout(2), reset, enable, clk, parout(1)); b0 : der_flop PORT MAP (parout(1), reset, enable, clk, parout(0));END structural;


Hardware realization of der_flop.

S11D

1D_

1R

1D

C1

Q

clock

reset

dff_in

qout

enable

din


Partitioning der_flop.

der_flop

mux2_1 flop


Structural description of der_flop.

ENTITY der_flop IS PORT (din, reset, enable, clk : IN BIT; qout : BUFFER BIT := '0');END der_flop;--ARCHITECTURE behavioral OF der_flop IS COMPONENT flop IS GENERIC (td_reset, td_in : TIME := 8 NS); PORT (reset, din, clk : IN BIT; qout : BUFFER BIT); END COMPONENT; COMPONENT mux2_1 IS GENERIC (dz_delay : TIME := 6 NS); PORT (sel, data1, data0 : IN BIT; z : OUT BIT); END COMPONENT; SIGNAL dff_in : BIT;BEGIN mx : mux2_1 PORT MAP (enable, din, qout, dff_in); ff : flop PORT MAP (reset, dff_in, clk, qout);END behavioral;


Complete design of seraial_adder.

serial-adder

fulladder flop shifter counter

der-flop der-flop der-flop

mux2-1 flop

. . .. . .. . .


Final Design.

a

b

Counter

Fulladder

carry_in

counting

1R

1D

C1

1R 1R

1D1D

C1 C1

Q Q Q

clk

serial-sum

1R

1D

C1

. . .

. . .

. . .

. . .

Q

carry_out

reset

1

s11

1

s11

1

s11

Synthesizable serial adder.

ENTITY serial_adder IS PORT (a, b, start, clock : IN BIT; ready : OUT BIT; result : BUFFER BIT_VECTOR (7 DOWNTO 0));END serial_adder;--ARCHITECTURE behavioral OF serial_adder ISBEGIN PROCESS (clock) SUBTYPE CNT8 IS INTEGER RANGE 0 TO 8; VARIABLE count : CNT8 := 8; VARIABLE sum, carry : BIT; BEGIN IF (clock = '0' AND clock'EVENT) THEN IF start = '1' THEN count := 0; carry := '0'; ELSE IF count < 8 THEN count := count + 1; sum := a XOR b XOR carry; carry := (a AND b) OR (a AND carry) OR (b AND carry); result <= sum & result (7 DOWNTO 1); END IF; END IF; IF count = 8 THEN ready <= '1'; ELSE ready <= '0'; END IF; END IF; END PROCESS;END behavioral;


FPGA layout of serial_adder.


Type conversion procedure.

TYPE byte IS ARRAY ( 7 DOWNTO 0 ) OF BIT; ...PROCEDURE byte_to_integer (ib : IN byte; oi : OUT INTEGER) IS VARIABLE result : INTEGER := 0;BEGIN FOR i IN 0 TO 7 LOOP IF ib(i) = '1' THEN result := result + 2**i; END IF; END LOOP; oi := result;END byte_to_integer;


The fadd (full adder) function.

FUNCTION fadd (a, b, c : IN BIT) RETURN BIT_VECTOR IS VARIABLE sc : BIT_VECTOR(1 DOWNTO 0);BEGIN sc(1) := a XOR b XOR c; sc(0) := (a AND b) OR (a AND c) OR (b AND c); RETURN sc;END;

fulladder using fadd.

ENTITY fulladder IS PORT (a, b, cin : IN BIT; sum, cout : OUT BIT);END fulladder;--ARCHITECTURE behavioral OF fulladder IS BEGIN (sum, cout) <= fadd (a, b, cin);END behavioral;

General outline of a controller.

x1

xn

z1

zn

.

.

.

.

.

.

clock

z<= . . .

z<= . . .

z<= . . .

x= ...

x= ...


Moore machine description.

IF 110 sequence is detected on x

THEN z gets '1'

ELSE z gets '0'

END;

clk

x z


Sequence detector state machine.

reset

0got1

0

got11

0

got110

10

0

1

11 0

0 1

VHDL Description of 110 detector.

ENTITY moore_110_detector IS PORT (x, clk : IN BIT ; z : OUT BIT);END moore_110_detector;--ARCHITECTURE behavioral OF moore_110_detector IS TYPE state IS (reset, got1, got11, got110);SIGNAL current : state := reset;BEGIN PROCESS(clk) BEGIN IF clk = ‘1’ AND clk’EVENT THEN CASE current IS WHEN reset => IF x = ‘1’ THEN current <= got1; ELSE current <= reset; END IF; WHEN got1 => IF x = ‘1’ THEN current <= got11; ELSE current <= reset; END IF; WHEN got11 => IF x = ‘1’ THEN current <= got11; ELSE current <= got110; END IF; WHEN got110 => IF x = ‘1’ THEN current <= got1; ELSE current <= reset; END IF; END CASE; END IF; END PROCESS; z <= ‘1’ WHEN current = got110 ELSE ‘0’;END behavioral;

State transition and corresponding VHDL code.

reset

0

got1

0

got11

0

1

0WHEN got1 => IF x='1' THEN current <= got11 ELSE current <= reset; END IF;

......

VHDL operators.

Operators Operand Type Result Type

LOGICALAND ORNAND NORXOR XNOR

BITorBOOLEAN

BITor

BOOLEAN

RELATIONAL= /=< <=> >=

All Types BOOLEAN

SHIFTSLL SRLSLA SRAROL ROR

Left:BIT or BOOLEAN VectorRight: INTEGER

BOOLEAN

ADDING + - &Numeric ArrayorArray Element

Same Type

SIGN + - Numeric Same Type

* / INTEGER, REAL Same TypeMULTIPLYING

MOD REM INTEGER Same Type

ABS Numeric Same TypeMISCELLENEOUS

**Left: NumericRight: Integer Same as Left

Syntax details of the architecture body.

ARCHITECTURE demo OF ezample ISSIGNAL

a, b, c :BIT := '0';

BEGINa <= '1' AFTER 15 NS;b <= NOT a AFTER 5 NS;c <= a AFTER 10 NS;

END demo;

architecturedeclarative_part

architecturestatement_part

architecturebody


Basic Concepts in VHDL

4.1 CHARACTERIZING HARDWARE LANGUAGES4.1.1 Timing4.1.2 Concurrency4.1.3 Modeling Hardware

4.2 OBJECTS AND CLASSES4.3 SIGNAL ASSIGNMENTS

4.3.1 Inertial Delay Mechanism4.3.2 Transport Delay Mechanism4.3.3 Comparing Inertial and Transport

4.4 CONCURRENT AND SEQUENTIAL ASSIGNEMNTS4.4.1 Concurrent Assignments4.4.2 Events and Transactions4.4.3 Delta Delay4.4.4 Sequential Placements of Transactions

4.5 SUMMARY


Value transfer through wires.

• What happens in a real hardware

• Must be able to model properly

Value transfer through wires.

a := x;b := x;

a <= x AFTER 4*unit_delay;b <= x AFTER 3*unit_delay;

• In one case immediate assignemnts are done

• In another case scheduling is done


Describing sub-components.

A

B C

S

• Hardware description requires concurrent constructs

• Concurrent bodies can be described behaviorally or at the dataflow

level


A VHDL concurrent body

• A VHDL concurrent body

• Statements are executed when events occur


A VHDL sequential body

• A VHDL sequential body

• Statements are executed when program flow reaches them

ARCHITECTURE sequential . . . BEGIN . . . PROCESS . . . BEGIN . . . IF THEN ELSE . . . FOR LOOP . . . END PROCESS . . .END ARCHITECTURE


Illustrating timing and concurrency.

a

b

c g1w

x

y

z

g2

g3

g4

• Four concurrent gates

• Each has a delay of 12 ns

• Change in inputs may result in in output hazards


Gates reacting to changes.

0 12 24 36

Reacting

Reacting

g1

g2

g3

g4 Reacting

Reacting

Reacting

Nanosecond

• a changes from ‘1’ to ‘0’

• A change in the a input results in domino changes each 12 ns apart

• No more events occur when output is reached


Nanosecond0 12 24 36

a

b

c

w

x

y

z

• Timing diagram resulting from input a changing from ‘1’ to ‘0’ at

time zero

• A glitch appears on the output

• Must model hardware to imitate this behavior

• Requires timing and concurrency in the language

Objects and Classes

sequential_body_1

a_variable := ...

y_signal <= ...

w_signal <= ...

loop_variable_i

z_signal <= ...

concurrent_body_3

u_signal <= local_constant

v_signal <= ...

concurrent_body_2

x_signal <= ...

y_signal <= ...

. . .

concurrent_body_1

v_signal

w_signal

x_signal

z_signal

y_signal

a_signal

b_signal

del1_constant del2_constant

u_signal

• Objects and classes in sequential and concurrent bodies

• Foundation for modeling timing and concurrency are signals

• Variables are used as software variables


Objects and Classes

B O D YConcurrent Sequential

Using ObjectsIn VHDL

Declare Assign to Use Declare Assign to UseSignal YES YES YES NO YES YES

Variable NO NO YES YES YES YES

Constant YES -- YES YES -- YES

OBJECT File YES -- YES YES -- YES

• Objects in VHDL bodies

• Cannot declare signals in sequential bodies

• Variable assignments are only done in sequential bodies

Delay Mechanisms

ENTITY example IS END ENTITY;--ARCHITECTURE delay OF example IS SIGNAL waveform : BIT; SIGNAL target1, target2, target3 : BIT; SIGNAL diff12, diff13, diff23 : BIT; -- This is a commentBEGIN

-- Illustrating inertial delay target1 <= waveform AFTER 5 NS; target2 <= REJECT 3 NS INERTIAL waveform AFTER 5 NS;

-- Illustrating transport delay target3 <= TRANSPORT waveform AFTER 5 NS;

-- Comparing targets diff12 <= target1 XOR target2; diff13 <= target1 XOR target3; diff23 <= target2 XOR target3;

-- Creating waveform waveform <=‘1’ AFTER 03 NS, ‘0’ AFTER 08 NS, ‘1’ AFTER 14 NS, ‘0’ AFTER 18 NS,‘1’ AFTER 24 NS, ‘0’ AFTER 27 NS, ‘1’ AFTER 33 NS, ‘0’ AFTER 35 NS,‘1’ AFTER 41 NS, ‘0’ AFTER 47 NS, ‘1’ AFTER 52 NS, ‘0’ AFTER 58 NS,‘1’ AFTER 62 NS, ‘0’ AFTER 68 NS, ‘1’ AFTER 71 NS, ‘0’ AFTER 77 NS,‘1’ AFTER 79 NS, ‘0’ AFTER 85 NS;END delay;

• VHDL description for the demonstration of delay mechanisms

• Example shows several concurrent statements

• Inertial, Reject and Transport

• Inertial: rejects anything less than its delay

• Reject: rejects anything less than or equal to its reject

• Transport: does not reject


Delay Mechanisms

• The RC delay is best represented by inertial delay mechanism

• This is a simple version of Inertial

• For more accurate modeling Reject can be used

R

C

Target 1 or Target 2


Delay Mechanisms

• Illustrating differences between delay mechanism in VHDL

• Positive and negative pulses appear on the LHS

5 6 4 6 3 6 2 6 6 5 6 4 6 3 6 2 6

Concurrency

ENTITY figure_5_example IS PORT (a, b, c : IN BIT; z : OUT BIT);END figure_5_example;

ARCHITECTURE concurrent OF figure_5_example IS SIGNAL w, x, y : BIT;BEGIN w <= NOT a AFTER 12 NS; x <= a AND b AFTER 12 NS; y <= c AND w AFTER 12 NS; z <= x OR y AFTER 12 NS;END concurrent;

• VHDL description for the gate level circuit for the demonstration

of timing and concurrency

• Four concurrent statements model gates of the circuit

• Events of the RHS cause evaluation and scheduling

• A scheduled value may or may not appear on the LHS

• A scheduled value is a transaction on the driver of the LHS signal


Concurrency

SignalValue

MultipleDrivingValues

ResolutionFunction

• A signal may have more than one driver

• Resolving a single value from multiple driving values

• Each driver has its own timing

• Independent handling of all drivers

• A driving value that is current contributes to the resolution

function


Events and Transactions

• A transaction, from being created to being expired

• A transaction that expires generates a current driving value

• This value contributes to the resolution function

d

d-t

0t t t d now

tr = (v, 0)

EXPIRED

tr = (v, d)

tr = (v, d-t )

i

i

i

0

0 1

transaction time component

0

ARCHITECTURE demo OF example IS SIGNAL a, b, c : BIT := '0';BEGIN a <= '1' AFTER 15 NS; b <= NOT a AFTER 5 NS; c <= a AFTER 10 NS;END demo;

• A simple description for illustrating events and transactions

• Transactions are scheduled on the 3 LHS signals

• Order is not significant

• Initial transaction are placed on all 3 signals



• Events and transactions( d )

0 5 1 0 1 5 2 52 0N S

0

0

0

a

b

c

( a )

0 5 1 0 1 5 2 52 0N S

T r a n s a c t i o n s W h e n T h e y A r e P l a c e d o n S i g n a l s

( 1 , 1 5 ) o n a( 1 , 0 5 ) o n b( 0 , 1 0 ) o n c

( 1 , 0 5 ) o n b( 0 , 1 0 ) o n c

( b )

0 5 1 0 1 5 2 52 0N S

T r a n s a c t i o n s A t 5 N S I n t e r v a l s

( c )

a

b

ca

a

c cb

c

0 5 1 0 1 5 2 52 0N S

P a t h O f T r a n s a c t i o n s T o E x p i r a t i o n

a

b b

cc

Delta Delay

ENTITY timing IS PORT (a, b : IN BIT; z, zbar : BUFFER BIT);END ENTITY;--ARCHITECTURE delta of timing ISBEGIN z_bar <= NOT z; z <= a AND b AFTER 10 NS;END delta;

• Demonstrating need for delta delay

• A “hidden” delay exists between z and z_bar

• Delta delay makes us believe that they take place at the same real

time

• The hidden delay is Delta which is not real-time

Delta Delay

ARCHITECTURE not_properly_timed OF figure_5_example IS SIGNAL w, x, y : BIT := '0';BEGIN y <= c AND w; w <= NOT a; x <= a AND b; z <= x OR y AFTER 36 NS;END not_properly_timed;

• VHDL description for demonstrating the delta delay

• Sequentiality in execution, same exact real time


Delta Delay

0 δ δδ1 2 3 0 12 24 36 NS

0

0

0

1

1

1

1a

b

c

w

x

y

z

• Timing diagram showing delta delays

• Looking at real times, we do not see Sequentiality

Delta Delay

ARCHITECTURE concurrent OF timing_demo IS SIGNAL a, b, c : BIT := '0';BEGIN a <= '1'; b <= NOT a; c <= NOT b;END concurrent;

• Description for a chain of two inverters

• Demonstrating Delta, transactions and concurrency


Delta Delay

δ0 1 2 3 0δδ NS

a

b

c 0

0

0

• Timing diagram for timing_demo

• Everything happens at real-time 0

Delta Delay

y x

Ideal elements withzero real time delay.

ARCHITECTURE forever OF oscillating IS SIGNAL x: BIT := ‘0’; SIGNAL y: BIT := ‘1’;BEGIN x <= y; y <= NOT x;END forever;

• Oscillation in zero real time

• Don’t try this at home

x

y t

t

1δ 2δ 3δ 4δ 5δ

1δ 2δ 3δ 4δ 5δ

00 6δ

6δ00

0

1

7δ 00

00

Sequential Placement of Transactions

ARCHITECTURE sequential OF sequential_placement IS . . .BEGIN PROCESS x<= v1 AFTER t1; x<= v2 AFTER t2; WAIT; END PROCESS;END sequential;

• Sequential placement of transactions in a sequential body of

VHDL

• A wait; statement suspends a sequential body forever

• Sequentially values are placed on the LHS

ARCHITECTURE concurrent OF sequential_placement IS . . .BEGIN a <= v1, v2 AFTER t2-t1 x <= a AFTER t2;END concurrent;

• Sequential placement of transaction in a concurrent body of VHDL

• Same effect as the above process statement



• Projected output waveform

• A new transaction will be compared with all existing transactions

• It appends, or overrides existing ones



• Multiple drivers of a resolved signal

• Each driver timing is treated independently



• Effective transactions on the driver of a signal

• Multiple transactions are sequentially placed on the signal driver

TRANSPORT INERTIAL

New Transaction is BEFOREAlready Existing

Overwriteexisting transaction


New Transaction is AFTERAlready Existing

Append thenew transaction.

v = vnew existing

Append thenew transaction.

1

2

3

4

v / = vnew existing

v / = vnew existing


Append the newtransaction

5

6

Difference betweentime of new andexisting is less thanor equal to reject value

Difference between time of new and existing is greater than the rejectvalue

ARCHITECTURE sequential OF discarding_old IS SIGNAL x : rit := ‘Z’;BEGIN PROCESS BEGIN x <= ‘1’ AFTER 5 NS; x <= TRANSPORT ‘0’ AFTER 3 NS; WAIT; END PROCESS;END sequential;

0 1 2 3 4 5 6 7 8 9

z

x

0z

• Discarding previous transactions

• The new transaction is scheduled before the existing one.

ARCHITECTURE sequential OF saving_all IS SIGNAL x : rit := ‘Z’;BEGIN PROCESS BEGIN x <= ‘1’ AFTER 5 NS; x <= TRANSPORT ‘0’ AFTER 8 NS; WAIT; END PROCESS;END sequential;

z

0 1 2 3 4 5 6 7 8 9

z

x

0z 1

• Appending transactions

• Delay type is transport

• The new transaction is after the existing one.

ARCHITECTURE sequential OF overwriting_old IS SIGNAL x : rit := ‘Z’;BEGIN PROCESS BEGIN x <= ‘1’ AFTER 5 NS; x <= ‘0’ AFTER 3 NS; WAIT; END PROCESS;END sequential;

0 1 2 3 4 5 6 7 8 9

z

x

0z

• Discarding previous transactions

• The new transaction is scheduled before the existing one

ARCHITECTURE sequential OF saving_all IS SIGNAL x : rit := ‘Z’;BEGIN PROCESS BEGIN x <= ‘0’ AFTER 5 NS; x <= ‘0’ AFTER 8 NS; WAIT; END PROCESS;END sequential;

z

0 1 2 3 4 5 6 7 8 9

z

x

0z

• Saving previous transactions of same value

• Transactions with the same value are both kept on the driver of x

ARCHITECTURE sequential OF appending IS SIGNAL x : rit :=’Z’;BEGIN PROCESS BEGIN x <= ‘1’ AFTER 5 NS; x <= REJECT 2 NS INERTIAL ’0’ AFTER 8 NS; WAIT; END PROCESS;END sequential;

• Appending the new transaction of different value

• Time difference of new and existing is greater than reject value

0 1 2 3 4 5 6 7 8 9

0z 1Z

x

Z

ARCHITECTURE sequential OF discarding_old IS SIGNAL x : rit :=’Z’;BEGIN PROCESS BEGIN x <= ‘1’ AFTER 5 NS; x <= REJECT 4 NS INERTIAL ’0’ AFTER 8 NS; WAIT; END PROCESS;END sequential

0 1 2 3 4 5 6 7 8 9

z

x

0z

• Discarding previous transactions of different value

• The new transaction is scheduled after the existing, and has a

different value

ENTITY example IS END ENTITY;--ARCHITECTURE delay OF example IS SIGNAL waveform : BIT; SIGNAL target1, target2, target3 : BIT;BEGIN

-- Signal assignments target1 <= waveform AFTER 5 NS; target2 <= REJECT 3 NS INERTIAL waveform AFTER 5 NS; target3 <= TRANSPORT waveform AFTER 5 NS;

-- Creating waveform waveform <= '1' AFTER 03 NS, '0' AFTER 08 NS, '1' AFTER 14 NS, '0' AFTER 18 NS, '1' AFTER 24 NS, '0' AFTER 27 NS, '1' AFTER 33 NS, '0' AFTER 35 NS;END delay;

• Pulse rejection in inertial, reject, and transport delay mechanisms

• This is a result of sequential placement of transactions

0 3 5 8 14 18 24 27 29 32 33 35 38 40



• New, pending, and expired transactions on targets of example

(0,5

)(0

,2)

(1,5

)(1

,3)

(1,0

)

(0,5

)

(0,0

)

(1,5

)

(1,1

)

(0,5

)

(0,0

)

(1,5

)

(1,2

)

(0,5

)

(0,0

)(1

,5)

(1,3

)

(0,5

)

(0,0

)

(0,5

)(0

,0)

(0,0

)

(0,5

)

(1,3

)

(1,0

)

(0,5

)

(1,3

)(1

,5)

(1,5

)(0

,0)

(0,0

)

(0,5

)

(1,2

)(1

,5)

(1,0

)

(0,5

)

(1,5

)(1

,2)

(1,5

)

(0,2

)

(1,3

)

(1,3

)(1

,0)

(0,5

)

(0,0

)

(1,5

)

(1,1

)

(0,5

)

(1,0

)(0

,0)

(0,2

)

(1,5

)

(0,0

)

(1,3

)

(1,0

)

(0,5

)

(0,0

)

(1,5

)

(1,1

)

(0,5

)

(1,0

)(0

,0)

03

58

1314

1819

2324

2729

3233

3538

40

targ

et1

targ

et2

targ

et3

ENTITY example IS END ENTITY;--ARCHITECTURE delay OF example IS SIGNAL a, b : BIT;BEGIN

-- Signal assignments a <= '1' AFTER 5 NS, '0' AFTER 10 NS, '1' AFTER 15 NS; b <= '0', a AFTER 3 NS;

END delay;

• Sequential placement of transactions by executing concurrent

signal assignments

• Events on a cause placement of transactions on b

• In a waveform, all but the first are TRANSPORT

CHAPTER 5 1 1999, Zainalabedin Navabi

CHAPTER 5STRUCTURAL SPECIFICATION

OF HARDWARE

5.1 PARTS LIBRARY5.1.1 Inverter Model5.1.2 NAND Gate Models

5.2 WIRING OF PRIMITIVES5.2.1 Logic Design of Comparator5.2.2 VHDL Description of bit_comparator

5.3 WIRING ITERATIVE NETWORKS5.3.1 Design of a 4-Bit Comparator

5.3.2 VHDL Description of a 4-Bit Comparator5.4 MODELING A TEST BENCH

5.4.1 VHDL Description of A Simple Test Bench5.4.2 Simulation

5.6 BINDING ALTERNATIVES5.6 TOP-DOWN WIRING

5.6.1 Sequential Comparator5.6.2 Byte Latch5.6.3 Byte Comparator

5.7 SUMMARY

Parts Library

(a)

ENTITY inv IS PORT (i1 : IN BIT; o1 : OUT BIT);END inv;

(b)

ARCHITECTURE single_delay OF inv ISBEGIN o1 <= NOT i1 AFTER 4 NS;END single_delay;

(c)

• Inverter• Symbol• Entity declaration• Architecture body• Notation.

invi1 o1

(d)


Parts Library

• Details of the entity declaration of inverter• Port clause• Interface signal declaration

;

o1 : OUT BIT

i1 : IN BIT

PORT

ENTITY inv IS

END inv;

interface_signal_declaration


portclause

(

;

)

entitydeclaration


Parts Library

• Elements of aspect notation• Input• Output• Inout• Buffer is output that can be used on RHS

Interface AspectInputPort

OutputPort

BidirectionalPort

entity_name

BufferPort


Parts Library

• Using ports, Inputs, Outputs, Bi-directional ports,Buffers

• Inout implies In and Out (two wires)• Buffer can be used inside an architecture

Parts Library

(a)

ENTITY nand2 IS PORT (i1, i2 : IN BIT; o1 : OUT BIT);END nand2;

(b)

ARCHITECTURE single_delay OF nand2 ISBEGIN o1 <= i1 NAND i2 AFTER 5 NS;END single_delay;

(c)

• Two-input NAND symbol• Entity declaration• Architecture body uses NAND operator

nand2i1

o1i2

(d)


Parts Library

• Port clause details for nand2• Signal declaration includes identifier list• Mode and type are the same as those of the inverter

portclause

(

o1 : OUT BIT

BIT

:

PORT


identifier_list

mode

type

interfacesignaldeclaration interface

list

i1, i2

IN

;

)

Parts Library

ENTITY nand3 IS PORT (i1, i2, i3 : IN BIT; o1 : OUT BIT);END nand3;

(b)

ARCHITECTURE single_delay OF nand3 ISBEGIN o1 <= NOT ( i1 AND i2 AND i3 ) AFTER 6 NS;END single_delay;

(c)

• Three-input NAND symbol• Architecture body and notation are shown• Must use AND and NOT

(a)

nand3i1

o1i2

i3

Wiring Components

• Logical symbol of a single bit comparator• Cascadable comparator• Will design one bit and cascade

Comparator

AB

>=<

A>B

A=B

A<B

Wiring Components

• Karnaugh maps for the outputs of the single bitcomparator

• Each output depends on data inputs and itscorresponding control input

00 01 11 10

0

1

a, b00 01 11 10

0

1

a, b00 01 11 10

0

1

a, b

a > b a = b a = <

1

1 11 1 1 1

1

1 1


Wiring Components

a_gt_b = a . gt + b’ . gt + a . b’

a_eq_b = a . b . eq + a’ . b’ . eq

a_lt_b = a’ . lt + b . lt + a’ . b

a_gt_b = ((a . gt)’.( b’ . gt)’.( a . b’)’)’

a_eq_b = ((a . b . eq)’.(a’ . b’ . eq)’)’

a_lt_b = ((a’ . lt)’.(b . lt)’.( a’ . b)’)’

• Boolean expression for the outputs• Use DeMorgan’s for all-NAND implementation


Wiring Components

• Logic diagram of bit_comparator• Using only our primitive components

a

gt

b

a_gt_b

a_eq_b

a_lt_b

a

b

eq

a

lt

b


Wiring Components

ENTITY bit_comparator IS PORT (a, b, -- data inputs gt, -- previous greater than eq, -- previous equal lt : IN BIT; -- previous less than a_gt_b, -- greater a_eq_b, -- equal a_lt_b : OUT BIT); -- less thanEND bit_comparator;

(b)

• Interface description of bit_comparator• Inputs and outputs of BIT type are declared

bit_comparator

a

a_gt_b

b

gt

eq

lt a_lt_b

a_eq_b

(a)


Wiring Components

• Composition Aspect of bit_comparator.

invi1 o1

nand2i1

o1i2

nand3i1

o1i2i3

nand2i1

o1i2

nand2i1

o1i2

nand3i1

o1i2i3

nand3i1

o1i2

i3

nand2i1

o1i2

nand2i1

o1i2

nand2i1

o1i2

nand2i1

o1i2

nand3i1

o1i2

i3

im3

im4

im5

im6

im7

im8

im9

im10

a_gt_b

a_eq_b

a_lt_binv

i1 o1

bit_comparator (gate_level)

a

b

gt

eq

lt

im2

im1


Wiring Components

ARCHITECTURE gate_level OF bit_comparator IS COMPONENT n1 PORT (i1: IN BIT; o1: OUT BIT); END COMPONENT; COMPONENT n2 PORT (i1, i2: IN BIT; o1: OUT BIT); END COMPONENT; COMPONENT n3 PORT (i1, i2, i3: IN BIT; o1: OUT BIT); END COMPONENT; FOR ALL : n1 USE ENTITY WORK.inv (single_delay); FOR ALL : n2 USE ENTITY WORK.nand2 (single_delay); FOR ALL : n3 USE ENTITY WORK.nand3 (single_delay); -- Intermediate signals SIGNAL im1,im2, im3, im4, im5, im6, im7, im8, im9, im10 : BIT;BEGIN -- a_gt_b output g0 : n1 PORT MAP (a, im1); g1 : n1 PORT MAP (b, im2); g2 : n2 PORT MAP (a, im2, im3); g3 : n2 PORT MAP (a, gt, im4); g4 : n2 PORT MAP (im2, gt, im5); g5 : n3 PORT MAP (im3, im4, im5, a_gt_b); -- a_eq_b output g6 : n3 PORT MAP (im1, im2, eq, im6); g7 : n3 PORT MAP (a, b, eq, im7); g8 : n2 PORT MAP (im6, im7, a_eq_b); -- a_lt_b output g9 : n2 PORT MAP (im1, b, im8); g10 : n2 PORT MAP (im1, lt, im9); g11 : n2 PORT MAP (b, lt, im10); g12 : n3 PORT MAP (im8, im9, im10, a_lt_b);END gate_level;

• Architecture body of bit_comparator identified asgate_level

• Components instantiations constitute the body• Each instantiation has a label, component name, and

PORT MAP• Component declarations are local to the architecture


Wiring Components

• Syntax details of the architecture body ofbit_comparator

• Signals in the entity are visible to the architecture

USE

FOR

END COMPONENT;

OF bit_comparator IS

PORT (i1, i2, i3: IN BIT;

. . .

im5, im6, im7, im8,

BEGIN

g7 :

COMPONENT n3

ARCHITECTURE gate_level

O1: OUT BIT);

. . .

ALL : n3

ENTITY

SIGNAL im1, im2, im3, im4,

im9, im10 : BIT;

. . .

PORT MAP (a, b, eq, im7);

. . .

n3

. . .

END gate_level;

componentdeclaration

configurationspecification

signaldeclaration

componentinstantiationstatement

architecturestatementpart

architecturedeclarativepart

architecturebody


Wiring Components

• Component instantiation statement syntax details• A label is required• It includes an association list

;

a, b, eq, im7

PORT MAP

:

g7

association_list


component_name

portmapaspect

instantiation_label

n3

(

)


Wiring Components

ARCHITECTURE netlist OF bit_comparator IS -- Intermediate signals SIGNAL im1,im2, im3, im4, im5, im6, im7, im8, im9, im10 : BIT;BEGIN -- a_gt_b output g0 : ENTITY WORK.inv(single_delay) PORT MAP (a, im1); g1 : ENTITY WORK.inv(single_delay) PORT MAP (b, im2); g2 : ENTITY WORK.nand2(single_delay) PORT MAP (a, im2, im3); g3 : ENTITY WORK.nand2(single_delay) PORT MAP (a, gt, im4); g4 : ENTITY WORK.nand2(single_delay) PORT MAP (im2, gt, im5); g5 : ENTITY WORK.nand3(single_delay)

PORT MAP (im3, im4, im5, a_gt_b); -- a_eq_b output g6 : ENTITY WORK.nand3(single_delay)

PORT MAP (im1, im2, eq, im6); g7 : ENTITY WORK.nand3(single_delay) PORT MAP (a, b, eq, im7); g8 : ENTITY WORK.nand2(single_delay)

PORT MAP (im6, im7, a_eq_b); -- a_lt_b output g9 : ENTITY WORK.nand2(single_delay) PORT MAP (im1, b, im8); g10 : ENTITY WORK.nand2(single_delay) PORT MAP (im1, lt, im9); g11 : ENTITY WORK.nand2(single_delay) PORT MAP (b, lt, im10); g12 : ENTITY WORK.nand3(single_delay)

PORT MAP (im8, im9, im10, a_lt_b);END netlist;

• Netlist description of bit_comparator• This is direct instantiation• If architecture name is not specified, the most recently

compiled architecture will be used


Wiring Components

• bit_comparator simulation run• keeping control inputs at 010

Wiring Iterative Networks

• Logical symbol of a 4-bit comparator• Same configuration as that of the one-bit comparator• This is similar to the 74LS85 magnitude comparator

Four Bit ComparatorA

B

>=<

A>B

A=B

A<B

Compareoutputs

Datainputs

Control inputs

4

4

• A 4-bit comparator using four single bit comparators• Numbers different in MSB, produce results faster• Worst case delay for equal inputs

Comparator

AB

>=<

A>B

A=B

A=<

A>B

A=B

A=<

A>B

A=B

A=<

A>B

A=B

ABA=B

A

ENTITY nibble_comparator ISPORT (a, b : IN BIT_VECTOR (3 DOWNTO 0);-- a and b data inputs gt, -- previous greater than eq, -- previous equal lt : IN BIT; -- previous less than a_gt_b, -- a > b a_eq_b, -- a = b a_lt_b : OUT BIT); -- a < bEND nibble_comparator;

• Interface description of nibble_comparator, (a)interface aspect, (b) entity declaration

• Inputs of of BIT_VECTOR type• Can use any range

nibble_comparator

a(3:0)a_gt_bb(3:0)

gt

eq

lta_lt_b

a_eq_b

(a)



• Composition aspect of nibble_comparator

nibble_comparator(iterative)

bit_comparator

a

a_gt_b

b

gt

eq

lt a_lt_b

a_eq_b

(gate_level)Bit 3

bit_comparator

a

a_gt_b

b

gt

eq

lt a_lt_b

a_eq_b

(gate_level)Bit 2

bit_comparator

a

a_gt_b

b

gt

eq

lt a_lt_b

a_eq_b

(gate_level)Bit 1

bit_comparator

a

a_gt_b

b

gt

eq

lt a_lt_b

a_eq_b

(gate_level)Bit 0

a_gt_b

a_eq_b

a_lt_b

a(3)

b(3)

a(2)

b(2)

a(1)

b(1)

a(0)

b(0)

c1to2:

im(6)

im(7)

im(8)

im(3)

im(4)

im(5)

im(0)

im(1)

im(2)

gt

eq

lt

a(3:0)

b(3:0)



ARCHITECTURE iterative OF nibble_comparator IS COMPONENT comp1 PORT (a, b, gt, eq, lt : IN BIT; a_gt_b, a_eq_b, a_lt_b : OUT BIT); END COMPONENT; FOR ALL : comp1 USE ENTITY WORK.bit_comparator (gate_level); SIGNAL im : BIT_VECTOR ( 0 TO 8);BEGIN c0: comp1 PORT MAP (a(0), b(0), gt, eq, lt, im(0), im(1), im(2)); c1to2: FOR i IN 1 TO 2 GENERATE c: comp1 PORT MAP (a(i), b(i), im(i*3-3), im(i*3-2), im(i*3-1), im(i*3+0), im(i*3+1), im(i*3+2) ); END GENERATE; c3: comp1 PORT MAP (a(3), b(3), im(6), im(7), im(8), a_gt_b, a_eq_b, a_lt_b);END iterative;

• Iterative architecture of nibble_comparator• Uses nested generate statements• Can easily expand by changing numbers



• Association list of c instance of comp1 within generatestatement

• Bit 1 is configured for i value of 1

i = 1 i = 1 i = 1 i = 1 i = 1 i = 1i = 1 i = 1

PORT MAP (a(i), b(i), im(i*3-3), im(i*3-2), im(i*3-1), im(i*3+0), im(i*3+1), im(i*3+2) )

PORT MAP (a(1), b(1), im(0), im(1), im(2), im(3), im(4), im(5) )



• Generate statement syntax details• This is a concurrent statement• The body of a generate statement is concurrent• Can use FOR or IF generation scheme

:

GENERATE

END GENERATE

im(i*3-1), im(i*3+0),

PORT MAP (a(i), b(i),

generate_label

;

generation_scheme

concurrent_statement

generatestatement

c1to2

FOR i IN 1 TO 2

c: COMP1

im(i*3-3), im(i*3-2),

im(i*3+1), im(i*3+2));

ARCHITECTURE iterative OF nibble_comparator IS COMPONENT comp1 PORT (a, b, gt, eq, lt : IN BIT; a_gt_b, a_eq_b, a_lt_b : OUT BIT); END COMPONENT; FOR ALL : comp1 USE ENTITY WORK.bit_comparator (gate_level); CONSTANT n : INTEGER := 4; SIGNAL im : BIT_VECTOR ( 0 TO (n-1)*3-1);BEGIN c_all: FOR i IN 0 TO n-1 GENERATE l: IF i = 0 GENERATE least: comp1 PORT MAP (a(i), b(i), gt, eq, lt, im(0), im(1), im(2) ); END GENERATE; m: IF i = n-1 GENERATE most: comp1 PORT MAP (a(i), b(i), im(i*3-3), im(i*3-2), im(i*3-1), a_gt_b, a_eq_b, a_lt_b); END GENERATE; r: IF i > 0 AND i < n-1 GENERATE rest: comp1 PORT MAP (a(i), b(i), im(i*3-3), im(i*3-2), im(i*3-1), im(i*3+0), im(i*3+1), im(i*3+2) ); END GENERATE; END GENERATE;END iterative;

• A more flexible iterative architecture ofnibble_comparator

• Constant n sizes the comparator• There is still a better way, use unconstrained arrays;

Chap 7.



l: IF i = 0 GENERATE FOR least : comp1 USE ENTITY WORK.bit_comparator (gate_level);BEGIN least: comp1 PORT MAP (a(i), b(i), gt, eq, lt, im(0), im(1), im(2) );END GENERATE;

• Configuration specifications create some ambiguities• Problem is corrected by Generate Statement

Declarative Part• Binding indication appears here


Modeling a Test Bench

• A test bench for nibble_comparator, the compositionaspect

• A test bench does not use ports• All signals used must be explicitly declared

nibble_comparator

a(3:0)

b(3:0)

gt

eq

lt

a_gt_b

a_eq_b

a_lt_b

(iterative)

test_bench (input_output)

ENTITY nibble_comparator_test_bench ISEND nibble_comparator_test_bench ;--ARCHITECTURE input_output OF nibble_comparator_test_bench IS COMPONENT comp4 PORT (a, b : IN bit_vector (3 DOWNTO 0); a_gt_b, a_eq_b, a_lt_b : IN BIT; a_gt_b_out, a_eq_b_out, a_lt_b_out : OUT BIT); END COMPONENT; FOR a1 : comp4 USE ENTITY WORK.nibble_comparator(iterative); SIGNAL a, b : BIT_VECTOR (3 DOWNTO 0); SIGNAL eql, lss, gtr : BIT; SIGNAL vdd : BIT := '1'; SIGNAL gnd : BIT := '0';BEGIN a1: comp4 PORT MAP (a, b, gnd, vdd, gnd, gtr, eql, lss);a2: a <= "0000", ---- a = b (steady state)

"1111" AFTER 0500 NS, -- a > b (worst case) "1110" AFTER 1500 NS, -- a b (need bit 1 info) "1010" AFTER 3500 NS, -- a < b (need bit 2 info) "0000" AFTER 4000 NS, -- a < b (steady state, prepare for next) "1111" AFTER 4500 NS, -- a = b (worst case) "0000" AFTER 5000 NS, -- a b (need bit 3 only, best case)

a3 : b <= "0000", ---- a = b (steady state) "1110" AFTER 0500 NS, -- a > b (worst case) "1111" AFTER 1500 NS, -- a b (need bit 1 info) "1100" AFTER 3500 NS, -- a < b (need bit 2 info) "1111" AFTER 4000 NS, -- a < b (steady state, prepare for next) "1111" AFTER 4500 NS, -- a = b (worst case) "1111" AFTER 5000 NS, -- a b (need bit 3 only, best case)

END input_output;

• Test bench for iterative architecture ofnibble_comparator.



SIGNALSTIME(NS) a(3:0) b(3:0) gtr eql lss

0 "0000" "0000" '0' '0' '0'5 ...... ...... ... '1' ...

500 "1111" "1110" ... ... ...544 ...... ...... '1' ... ...548 ...... ...... ... '0' ...

1500 "1110" "1111" ... ... ...1544 ...... ...... '0' ... ...1548 ...... ...... ... ... '1'2500 ...... "1100" ... ... ...2533 ...... ...... ... ... '0'2537 ...... ...... '1' ... ...3500 "1010" ...... ... ... ...3522 ...... ...... '0' ... ...3526 ...... ...... ... ... '1'4000 "0000" "1111" ... ... ...4500 "1111" ...... ... ... ...4544 ...... ...... ... '1' ...4548 ...... ...... ... ... '0'5000 "0000" ...... ... ... ...5011 ...... ...... ... '0' ...5015 ...... ...... ... ... '1'5500 ...... "0000" ... ... ...5544 ...... ...... ... ... '0'5548 ...... ...... ... '1' ...6000 "1111" ...... ... ... ...6011 ...... ...... '1' ... ...6015 ...... ...... ... '0' ...

• Simulation report for simulating iterative comparatortest bench

• All events are observed


Binding Alternatives

• Logical diagram of a simple latch• With equal timing this will not work• Will use this example for showing binding alternatives• Correct the oscillation problem by binding to NAND

gates of different delay values

C

S

R

1

2

3

4

Q

ENTITY sr_latch IS PORT (s, r, c : IN BIT; q : OUT BIT);END sr_latch;--ARCHITECTURE gate_level OF sr_latch IS COMPONENT n2 PORT (i1, i2: IN BIT; o1: OUT BIT); ENDCOMPONENT; FOR ALL : n2 USE ENTITY WORK.nand2 (single_delay); SIGNAL im1, im2, im3, im4 : BIT;BEGIN g1 : n2 PORT MAP (s, c, im1); g2 : n2 PORT MAP (r, c, im2); g3 : n2 PORT MAP (im1, im4, im3); g4 : n2 PORT MAP (im3, im2, im4); q <= im3;END gate_level;

• VHDL description of set-reset latch• This is using the 2-input NAND for all four instances• Signal assignment avoids use of Buffer• The single_delay architecture is used



ARCHITECTURE gate_level OF sr_latch IS COMPONENT n2 PORT (i1, i2: IN BIT; o1: BUFFER BIT); ENDCOMPONENT; FOR ALL : n2 USE ENTITY WORK.nand2 (single_delay); SIGNAL im1, im2, im4 : BIT;BEGIN g1 : n2 PORT MAP (s, c, im1); g2 : n2 PORT MAP (r, c, im2); g3 : n2 PORT MAP (im1, im4, q); g4 : n2 PORT MAP (q, im2, im4);END gate_level;

• sr_latch (gate_level) architecture using BUFFER• componet declaration and the actual entity must match

is PORT MAP is not used with the configurationspecification

• The 2-input NAND must change to use BUFFERinstead of OUT

ARCHITECTURE fast_single_delay OF nand2 ISBEGIN o1 <= i1 NAND i2 AFTER 3 NS;END fast_single_delay;

• A faster NAND gate• The gate delay is 3 NS• Uses the same entity as the single_delay NAND• Using this NAND corrects the oscillation problem



• SR-latch, using gates with different delays, compositionaspect

• Same wiring as the latch that oscillates

nand2i1

o1i2 g1:

(fast_single_delay)

nand2i1

o1i2 g2:

(single_delay)

nand2i1

o1i2 g3:

(fast_single_delay)

nand2i1

o1i2 g4:

(single_delay)

sr_latch (gate_level)

im1

im2

im3

im4

q

c

s

r

(a)

ARCHITECTURE gate_level OF sr_latch IS COMPONENT n2 PORT (i1, i2: IN BIT; o1: OUT BIT); ENDCOMPONENT; FOR g1, g3 : n2 USE ENTITY WORK.nand2 (fast_single_delay); FOR g2, g4 : n2 USE ENTITY WORK.nand2 (single_delay); SIGNAL im1, im2, im3, im4 : BIT;BEGIN g1 : n2 PORT MAP (s, c, im1); g2 : n2 PORT MAP (r, c, im2); g3 : n2 PORT MAP (im1, im4, im3); g4 : n2 PORT MAP (im3, im2, im4); q <= im3;END gate_level;

• SR-latch, using gates with different delays,architecture body

• Same wiring, different binding• Fast_single_delay architecture is used for g1 and g3



• SR-latch, using nand2 and nand3 gates, compositionaspect

• This solution uses 3-input NAND gates• The 3-input gates have different delay values than the

2-input NAND gates

nand2i1

o1i2 g1:

(single_delay) nand2i1

o1i2 g3:

(single_delay)

sr_latch (gate_level)

im1im3 q

c

s

rnand3i1

o1i2

i3

nand3i1

o1i2

i3

(single_delay) (single_delay)

g2: g4:

im2 im4

(a)

ARCHITECTURE gate_level OF sr_latch IS COMPONENT n2 PORT (x, y: IN BIT; z: OUT BIT); END COMPONENT; FOR g1, g3 : n2 USE ENTITY WORK.nand2 (single_delay) PORT MAP (x, y, z); FOR g2, g4 : n2 USE ENTITY WORK.nand3 (single_delay) PORT MAP (x, x, y, z); SIGNAL im1, im2, im3, im4 : BIT;BEGIN g1 : n2 PORT MAP (s, c, im1); g2 : n2 PORT MAP (r, c, im2); g3 : n2 PORT MAP (im1, im4, im3); g4 : n2 PORT MAP (im3, im2, im4); q <= im3;END gate_level;

ALTERNATIVELY:

FOR g1, g3 : n2 USE ENTITY WORK.nand2 (single_delay) PORT MAP (x, y, z);FOR OTHERS : n2 USE ENTITY WORK.nand3 (single_delay) PORT MAP (x, x, y, z);

• SR-latch, using nand2 and nand3 gates, architecture• Configuration specification takes caring of wiring the

3-input NAND into a 2-input NAND• PORT MAP in binding, overrides the default• Could use OTHERS



• Two-step association• Declaration is local• Names in declaration are used only when not specified

in a configuration specification

r c im2

x y z

Signals ofgate_level ofsr_latch

in1 in2 in3 o1

Local portsof g2 instanceof n2

Formalports of nand3

Port map associationof instantiationstatement

Port map associationof configurationspecification



• Configuration specification syntax details• Binding indication contains entity aspect, port map

aspect, and generic map aspect• If not specified, those of the declaration will be used• Declarations are still needed unless direct

instantiations are used

(x, y, z)

PORT

(single_delay)

ENTITY

n2

g1, g3 instantiation_listcomponentspecification

FOR

component_name

entityaspect

port mapaspect

bindingindication

configurationspecification

:

USE

WORK.nand2

MAP

;


Top-Down Wiring

• Will develop a complete example, compare old andnew data, keep a count

• Defaults will be used• Most recently compiled architectures are used in the

absence of configuration specifications• Composition aspect of old_new_comparator

byte_comparator

a

b

gt

eq

lt

a_gt_b

a_eq_b

a_lt_b

old_new_comparator

byte_latchdi

clk

i

clk

con1


Top-Down Wiring

ENTITY old_new_comparator IS PORT (i : IN BIT_VECTOR (7 DOWNTO 0); clk : IN BIT; gt_compare, eq_compare : OUT BIT);END old_new_comparator;--ARCHITECTURE wiring OF old_new_comparator IS COMPONENT byte_latch PORT (di : IN BIT_VECTOR (7 DOWNTO 0); clk : IN BIT; qo : OUT BIT_VECTOR (7 DOWNTO 0)); END COMPONENT; COMPONENT byte_comparator PORT(a, b : BIT_VECTOR (7 DOWNTO 0); gt, eq, lt : IN BIT; a_gt_b, a_eq_b, a_lt_b : OUT BIT); END COMPONENT; SIGNAL con1 : BIT_VECTOR (7 DOWNTO 0); SIGNAL vdd : BIT := '1'; SIGNAL gnd : BIT := '0';BEGIN l : byte_latch PORT MAP(i, clk, con1); c : byte_comparatorPORT MAP(con1, i, gnd, vdd, gnd, gt_compare, eq_compare, OPEN);END wiring;

• old_new_comparator VHDL description• Declarations are present• Configuration specifications are missing• Use OPEN for unconnected outputs• OPEN inputs must have a default value


Top-Down Wiring

ENTITY byte_latch IS PORT (di : IN BIT_VECTOR (7 DOWNTO 0); clk : IN BIT; qo : OUT BIT_VECTOR( 7 DOWNTO 0));END byte_latch;--ARCHITECTURE iterative OF byte_latch IS COMPONENT d_latch PORT (d, c : IN BIT; q : OUT BIT); END COMPONENT;BEGIN g : FOR i IN di'RANGE GENERATE l7dt0 : d_latch PORT MAP (di(i), clk, qo(i)); END GENERATE;END iterative;

• An 8-bit latch is required for this design• Use a configurable description based on D-type latch• VHDL description of byte_latch.• Iterative architecture is used


Top-Down Wiring

(a)

• Build a D-latch using our sr_latch and an inverter• Composition aspect is shown

C

S

R

qq

invo1i1

c

d

sr_latch


Top-Down Wiring

ENTITY d_latch IS PORT(d,c : IN BIT;q: OUT BIT); END d_latch;--ARCHITECTURE sr_based OF d_latch IS COMPONENT sr_latch PORT (s, r, c : IN BIT; q : OUT BIT); END COMPONENT; COMPONENT inv PORT (i1 : IN BIT; o1 : OUT BIT); END COMPONENT; SIGNAL dbar: BIT;BEGIN c1 : sr_latch PORT MAP (d, dbar, c, q); c2 : inv PORT MAP (d, dbar);END sr_based;

(b)

• Design of d_latch, VHDL description• Configuration specifications are not used• Local declarations are used for ports and name of the

actual entity

Top-Down Wiring

ARCHITECTURE iterative OF nibble_comparator IS COMPONENT bit_comparator PORT (a, b, gt, eq, lt : IN BIT; a_gt_b, a_eq_b, a_lt_b : OUT BIT); END COMPONENT; CONSTANT n : INTEGER := 8; SIGNAL im : BIT_VECTOR ( 0 TO (n-1)*3-1);BEGIN c_all: FOR i IN 0 TO n-1 GENERATE l: IF i = 0 GENERATE least: bit_comparator PORT MAP (a(i), b(i), gt, eq, lt, im(0), im(1), im(2) ); END GENERATE; m: IF i = n-1 GENERATE most: bit_comparator PORT MAP (a(i), b(i), im(i*3-3), im(i*3-2), im(i*3-1), a_gt_b, a_eq_b, a_lt_b); END GENERATE; r: IF i > 0 AND i < n-1 GENERATE rest: bit_comparator PORT MAP (a(i), b(i), im(i*3-3), im(i*3-2), im(i*3-1), im(i*3+0), im(i*3+1), im(i*3+2) ); END GENERATE; END GENERATE;END iterative;

• Another necessary component for this design is an 8-bit comparator

• Byte comparator VHDL description• Uses 8 instances of bit_comparator• Constant n is changed to 8• Default architectures are used


Top-Down Wiring

A structural description for a design consists of a wiring

specification of its subcomponents. In this chapter, the

definition and usage of components in larger designs was

illustrated. Generate statements also were introduced as a

convenient way to describe repetitive hardware structures

and a notation was defined for graphical representation of

structural descriptions. In addition, various forms and

options in component declarations and configuration

specifications were discussed. The last part of this chapter

presented a top-down design using basic gates and

components presented in the earlier sections. Using simple

gates, the reader should now be able to design larger digital

circuits with many levels of component nesting.

• End Of Chapter 5


CHAPTER 6DESIGN ORGANIZATION AND

PARAMETERIZATION

6.1 DEFINITION AND USAGE OF SUBPROGRAMS6.1.1 A Functional Single Bit Comparator6.1.2 Using Procedures in a Test Bench6.1.3 Language Aspects of Subprograms6.1.4 Utility Procedures

6.2 PACKAGING PARTS AND UTILITIES6.2.1 Packaging Components6.2.2 Packaging Subprograms

6.3 DESIGN PARAMETRIZATION6.3.1 Using Default Values6.3.2 Using Fixed Values6.3.3 Passing Generic Parameters

6.4 DESIGN CONFIGURATION6.4.1 A General Purpose Test Bench6.4.2 Configuring Nested Components6.4.3 Incremental Binding6.4.4 An n-bit Register Example6.4.5 Iterative Parity Checking

6.5 DESIGN LIBRARIES6.5.1 Existing Libraries6.5.2 Library Management

6.6 SUMMARY

Definition and Usage of Subprograms

GT Equation a_gt_b = a . gt + b' . gt + a . b'

EQ Equation a_eq_b = a . b . eq + a' . b' . eq

LT Equation a_lt_b = b . lt + a' . lt + b . a'

ARCHITECTURE functional OF bit_comparator IS FUNCTION fgl (w, x, gl : BIT) RETURN BIT IS BEGIN RETURN (w AND gl) OR (NOT x AND gl) OR (w AND NOT x); END fgl; FUNCTION feq (w, x, eq : BIT) RETURN BIT IS BEGIN RETURN (w AND x AND eq) OR (NOT w AND NOT x AND eq); END feq;BEGIN a_gt_b <= fgl (a, b, gt) AFTER 12 NS; a_eq_b <= feq (a, b, eq) AFTER 12 NS; a_lt_b <= fgl (b, a, lt) AFTER 12 NS;END functional;

• Demonstrating the use of functions• Use functions in place of Bololean expresssions• A functional bit_comparator, using the same function

for two outputs

An architecture fordemonstrating use ofsubprograms



• Function body is sequential• Use functions for utilities and coding style• Syntax details of a subprogram body, a general view

(NOT x AND g1) OR

RETURN

IS

RETURN

fgl

;

designator

expression

formal_parameter_list

type_mark

subprogramspecification

returnstatement

sequentialstatement

subprogramstatementpart

sub-programbody

FUNCTION

( w, x, g1 :BIT)

BIT

BEGIN

(w AND g1) OR

(w AND NOT x)

END;

ARCHITECTURE structural OF nibble_comparator IS COMPONENT comp1 PORT (a, b, gt, eq, lt : IN BIT; a_gt_b, a_eq_b, a_lt_b : OUT BIT); END COMPONENT; FOR ALL : comp1 USE ENTITY WORK.bit_comparator (functional); CONSTANT n : INTEGER := 4; SIGNAL im : BIT_VECTOR ( 0 TO (n-1)*3-1);BEGIN c_all: FOR i IN 0 TO n-1 GENERATE l: IF i = 0 GENERATE least: comp1 PORT MAP (a(i), b(i), gt, eq, lt, im(0), im(1), im(2) ); END GENERATE; m: IF i = n-1 GENERATE most: comp1 PORT MAP (a(i), b(i), im(i*3-3), im(i*3-2), im(i*3-1), a_gt_b, a_eq_b, a_lt_b); END GENERATE; r: IF i > 0 AND i < n-1 GENERATE rest: comp1 PORT MAP (a(i), b(i), im(i*3-3), im(i*3-2), im(i*3-1), im(i*3+0), im(i*3+1), im(i*3+2) ); END GENERATE; END GENERATE;END structural;

• Using the functional bit_comparator• Structural architecture of a nibble_comparator

ARCHITECTURE procedural OF nibble_comparator_test_bench IS TYPE integers IS ARRAY (0 TO 12) OF INTEGER; PROCEDURE apply_data (SIGNAL target : OUT BIT_VECTOR (3 DOWNTO 0); CONSTANT values : IN integers; CONSTANT period : IN TIME) IS VARIABLE j : INTEGER; VARIABLE tmp, pos : INTEGER := 0; VARIABLE buf : BIT_VECTOR (3 DOWNTO 0); BEGIN FOR i IN 0 TO 12 LOOP tmp := values (i); j := 0; WHILE j <= 3 LOOP IF (tmp MOD 2 = 1) THEN buf (j) := '1'; ELSE buf (j) := '0'; END IF; tmp := tmp / 2; j := j + 1; END LOOP; target <= TRANSPORT buf AFTER i * period; END LOOP; END apply_data; COMPONENT comp4 PORT (a, b : IN bit_vector (3 DOWNTO 0); gt, eq, lt : IN BIT; a_gt_b, a_eq_b, a_lt_b : OUT BIT); END COMPONENT; FOR a1 : comp4 USE ENTITY WORK.nibble_comparator(structural); SIGNAL a, b : BIT_VECTOR (3 DOWNTO 0); SIGNAL eql, lss, gtr : BIT; SIGNAL vdd : BIT := '1'; SIGNAL gnd : BIT := '0';BEGIN a1: comp4 PORT MAP (a, b, gnd, vdd, gnd, gtr, eql, lss); apply_data (a, 00&15&15&14&14&14&14&10&00&15&00&00&15, 500 NS); apply_data (b, 00&14&14&15&15&12&12&12&15&15&15&00&00, 500 NS);END procedural;

• Defining and using a procedure• Procedural architecture of nibble_comparator• INTEGERS type is an array of 13 integers



SIGNALSTIME(NS) a(3:0) b(3:0) gtr eql lss

0 "0000" "0000" '0' '0' '0' 48 ...... ...... ... '1' ...

500 "1111" "1110" ... ... ... 548 ...... ...... '1' '0' ... 1500 "1110" "1111" ... ... ... 1548 ...... ...... '0' ... '1' 2500 ...... "1100" ... ... ... 2536 ...... ...... '1' ... '0' 3500 "1010" ...... ... ... ... 3524 ...... ...... '0' ... '1' 4000 "0000" "1111" ... ... ... 4500 "1111" ...... ... ... ... 4548 ...... ...... ... '1' '0' 5000 "0000" ...... ... ... ... 5012 ...... ...... ... '0' '1' 5500 ...... "0000" ... ... ... 5548 ...... ...... ... '1' '0' 6000 "1111" ...... ... ... ... 6012 ...... ...... '1' '0' ...

• Simulation report resulting from the procedural testbench

• All events are observed• Shows increments of 12 NS only



• Details of a subprogram body• Function or procedure subprogram specification• Subprograms are procedural bodies• Nested procedural statements

formalparameterlist

VARIABLE tmp : INTEGER := 0;

IS

CONSTANT period : IN TIME

(

BIT_VECTOR (3 DOWNTO 0);

BIT_VECTOR (3 DOWNTO 0);

FOR i IN 0 TO 12 LOOP

.

END LOOP;

subprogramspecification

subprogramdeclarativepart

loopstatement

sequentialstatement

subprogramstatementpart

sub-programbody

SIGNAL target : OUT

PROCEDURE apply_data

CONSTANT values : IN integers;

)

VARIABLE j : INTEGER;

VARIABLE buf:

BEGIN;

.

.

END apply_data;



• Loops are procedural• Loop statement with FOR iteration scheme• Can nest procedural statements• Sequence_of_statements is the sequential construct

.

12

0

i

.sequence_of_statement

loopparameterspecification

iterationscheme

loop_statement

FOR

IN

TO

LOOP

.

END LOOP;



• Details of the If statement of apply_data procedure• This is a procedural statement• Sequence_of_statements is the sequential construct

sequence_of_statements

condition

buf (j) := ‘0’;

buf (j) := ’1’;

(tmp MOD 2 = 1)

sequence_of_statements

if_statement

IF

THEN

ELSE

END IF;



PROCEDURE bin2int (bin : IN BIT_VECTOR; int : OUT INTEGER) IS VARIABLE result: INTEGER;BEGIN result := 0; FOR i IN bin'RANGE LOOP IF bin(i) = '1' THEN result := result + 2**i; END IF; END LOOP; int := result;END bin2int;

• Can do utility procedures• ‘RANGE attribute makes this a generic procedure• Procedure for binary to integer conversion



PROCEDURE int2bin (int : IN INTEGER; bin : OUT BIT_VECTOR) IS VARIABLE tmp : INTEGER;BEGIN tmp := int; FOR i IN 0 TO (bin'LENGTH - 1) LOOP IF (tmp MOD 2 = 1) THEN bin (i) := '1'; ELSE bin (i) := '0'; END IF; tmp := tmp / 2; END LOOP;END int2bin;

• Another utility procedure• Procedure for integer to binary conversion• ‘LENGTH attribute is used here

PROCEDURE apply_data ( SIGNAL target : OUT BIT_VECTOR (3 DOWNTO 0); CONSTANT values : IN integers; CONSTANT period : IN TIME)IS VARIABLE buf : BIT_VECTOR (3 DOWNTO 0);BEGIN FOR i IN 0 TO 12 LOOP int2bin (values(i), buf); target <= TRANSPORT buf AFTER i * period; END LOOP;END apply_data;

• Can use procedures within procedure• Another version of apply_data procedure• This version takes advantage of the int2bin procedure• TRASPORT delay schedules all transactions at time 0



FUNCTION to_integer (bin : BIT_VECTOR) RETURN INTEGER IS VARIABLE result: INTEGER;BEGIN result := 0; FOR i IN bin'RANGE LOOP IF bin(i) = '1' THEN result := result + 2**i; END IF; END LOOP; RETURN result;END to_integer;

• Functions can serve as utilities• Binary to integer conversion function• Assumes lower bound of 0, otherwise it is a generic

function


Packaging Parts and Utilities

-- Packaging components

PACKAGE simple_gates IS COMPONENT n1 PORT (i1: IN BIT; o1: OUT BIT); END COMPONENT; COMPONENT n2 PORT (i1: i2: IN BIT; o1: OUT BIT); END COMPONENT; COMPONENT n3 PORT (i1, i2, i3: IN BIT; o1: OUT BIT); END COMPONENT;END simple_gates;

• Component declarations as well as utilities can bepackaged

• A package declaration containing componentdeclarations of simple gates

• Eliminates the need for individual declarations

Demonstratingspecification and usage ofpackages



USE WORK.simple_gates.ALL;ARCHITECTURE gate_level OF bit_comparator IS FOR ALL : n1 USE ENTITY WORK.inv (single_delay); FOR ALL : n2 USE ENTITY WORK.nand2 (single_delay); FOR ALL : n3 USE ENTITY WORK.nand3 (single_delay); -- Intermediate signals SIGNAL im1,im2, im3, im4, im5, im6, im7, im8, im9, im10 : BIT;BEGIN -- a_gt_b output g0 : n1 PORT MAP (a, im1); g1 : n1 PORT MAP (b, im2); g2 : n2 PORT MAP (a, im2, im3); g3 : n2 PORT MAP (a, gt, im4); g4 : n2 PORT MAP (im2, gt, im5); g5 : n3 PORT MAP (im3, im4, im5, a_gt_b); -- a_eq_b output g6 : n3 PORT MAP (im1, im2, eq, im6); g7 : n3 PORT MAP (a, b, eq, im7); g8 : n2 PORT MAP (im6, im7, a_eq_b); -- a_lt_b output g9 : n2 PORT MAP (im1, b, im8); g10 : n2 PORT MAP (im1, lt, im9); g11 : n2 PORT MAP (b, lt, im10); g12 : n3 PORT MAP (im8, im9, im10, a_lt_b);END gate_level;

• Using package of simple gates in gate_level ofbit_comparator

• This becomes our local declarations• Same naming rules as before, same configuration



USE WORK.simple_gates.n1, WORK.simple_gates.n2, WORK.simple_gates.n3;.-- n1, n2 and n3 component declarations are visible.

• An alternative application of the use clause• Can select only those needed



PACKAGE basic_utilities IS TYPE integers IS ARRAY (0 TO 12) OF INTEGER; FUNCTION fgl (w, x, gl : BIT) RETURN BIT; FUNCTION feq (w, x, eq : BIT) RETURN BIT; PROCEDURE bin2int (bin : IN BIT_VECTOR; int : OUT INTEGER); PROCEDURE int2bin (int : IN INTEGER; bin : OUT BIT_VECTOR); PROCEDURE apply_data ( SIGNAL target : OUT BIT_VECTOR (3 DOWNTO 0); CONSTANT values : IN integers; CONSTANT period : IN TIME); FUNCTION to_integer (bin : BIT_VECTOR) RETURN INTEGER;END basic_utilities;

• The basic_utilities package declaration• Packaging subprograms replaces their declaration• Types and declarations become visible to architectures



PACKAGE BODY basic_utilities IS FUNCTION fgl (w, x, gl : BIT) RETURN BIT IS BEGIN RETURN (w AND gl) OR (NOT x AND gl) OR (w AND NOT x); END fgl; FUNCTION feq (w, x, eq : BIT) RETURN BIT IS BEGIN RETURN (w AND x AND eq) OR (NOT w AND NOT x AND eq); END feq; PROCEDURE bin2int (bin : IN BIT_VECTOR; int : OUT INTEGER) IS VARIABLE result: INTEGER; BEGIN result := 0; FOR i IN bin'RANGE LOOP IF bin(i) = '1' THEN result := result + 2**i; END IF; END LOOP; int := result; END bin2int; PROCEDURE int2bin (int : IN INTEGER; bin : OUT BIT_VECTOR) IS VARIABLE tmp : INTEGER; VARIABLE buf : BIT_VECTOR (bin'RANGE); BEGIN tmp := int; FOR i IN 0 TO (bin'LENGTH - 1) LOOP IF (tmp MOD 2 = 1) THEN bin (i) := '1'; ELSE bin (i) := '0'; END IF; tmp := tmp / 2; END LOOP; END int2bin;

• Package body includes body of procedures• The basic_utilities package body• Will use this package in all our examples

PROCEDURE apply_data ( SIGNAL target : OUT BIT_VECTOR (3 DOWNTO 0); CONSTANT values : IN integers; CONSTANT period : IN TIME) IS VARIABLE buf : BIT_VECTOR (3 DOWNTO 0); BEGIN FOR i IN 0 TO 12 LOOP int2bin (values(i), buf); target <= TRANSPORT buf AFTER i * period; END LOOP; END apply_data; FUNCTION to_integer (bin : BIT_VECTOR) RETURN INTEGER IS VARIABLE result: INTEGER; BEGIN result := 0; FOR i IN bin'RANGE LOOP IF bin(i) = '1' THEN result := result + 2**i; END IF; END LOOP; RETURN result; END to_integer;END basic_utilities;

• Continuation of the basic_utilities package body• New declarations in this body are visible to this body

only

USE WORK.basic_utilities.ALL;ARCHITECTURE functional OF bit_comparator ISBEGIN a_gt_b <= fgl (a, b, gt) AFTER 12 NS; a_eq_b <= feq (a, b, eq) AFTER 12 NS; a_lt_b <= fgl (b, a, lt) AFTER 12 NS;END functional;

• Using functions of the basic_utilities package• Architecture need not include function body• The USE statement handles visibility



USE WORK.basic_utilities.ALL;ARCHITECTUR procedural OF nibble_comparator_test_bench IS COMPONENT comp4 PORT ( a, b : IN bit_vector (3 DOWNTO 0); gt, eq, lt : IN BIT; a_gt_b, a_eq_b, a_lt_b : OUT BIT); END COMPONENT; FOR a1 : comp4 USE ENTITY WORK.nibble_comparator(structural); SIGNAL a, b : BIT_VECTOR (3 DOWNTO 0); SIGNAL eql, lss, gtr : BIT; SIGNAL vdd : BIT := '1'; SIGNAL gnd : BIT := '0';BEGIN a1: comp4 PORT MAP (a, b, gnd, vdd, gnd, gtr, eql, lss); apply_data (a, 0&15&15&14&14&14&14&10&00&15&00&00&15, 500 NS); apply_data (b, 0&14&14&15&15&12&12&12&15&15&15&00&00, 500 NS);END procedural;

ALTERNATIVELY:

apply_data (a, (00,15,15,14,14,14,14,10,00,15,00,00,15), 500 NS);apply_data (b, (00,14,14,15,15,12,12,12,15,15,15,00,00), 500 NS);

• Using procedures of the basic_utilities package• Concatenate to form 13 integers• Can also use aggregate operation• Aggregate for elements of the array only

Design Parametrization

ENTITY inv_t IS GENERIC (tplh : TIME := 5 NS; tphl : TIME := 3 NS); PORT (i1 : IN BIT; o1 : OUT BIT);END inv_t;--ARCHITECTURE average_delay OF inv_t ISBEGIN o1 <= NOT i1 AFTER (tplh + tphl) / 2;END average_delay;

• Start design parameterization examples with samesimple structures

Architecture fordemonstrating specificationand definition of parameters

ENTITY nand2_t IS GENERIC (tplh : TIME := 6 NS; tphl : TIME := 4 NS); PORT (i1, i2 : IN BIT; o1 : OUT BIT);END nand2_t;--ARCHITECTURE average_delay OF nand2_t ISBEGIN o1 <= i1 NAND i2 AFTER (tplh + tphl) / 2;END average_delay;

ENTITY nand3_t IS GENERIC (tplh : TIME := 7 NS; tphl : TIME := 5 NS); PORT (i1, i2, i3 : IN BIT; o1 : OUT BIT);END nand3_t;--ARCHITECTURE average_delay OF nand3_t ISBEGIN o1 <= NOT ( i1 AND i2 AND i3 ) AFTER (tplh + tphl) / 2;END average_delay;

• Parametrized gate models• GENERIC is used, declares objects of type constant



• Details of the entity declaration of inverter withgenerics

• Using a default value is helpful but not required• Generic clause comes before port clause

GENERIC

entitydeclaration

interfaceconstantdeclaration

3 NS

tphl :

5 NS

tplh :

PORT

o1 : OUT BIT);

interfaceconstantdeclaration

(generic)interfacelist

(formal)portclause

(formal)genericclause

entityheader

ENTITY inv_t IS

(

TIME :=

;

TIME :=

);

(i1 : IN BIT;

END inv_t;



• Interface aspects of inv_t, nand2_t, and nand3_t• Graphical representation with generics• Port association and generic association must be done

when used

nand3_ti1

o1i2

i3

inv_ti1 o1tplh tphl

nand2_ti1

o1i2tplh tphl

tplh tphl



ARCHITECTURE default_delay OF bit_comparator IS COMPONENT n1 PORT (i1: IN BIT; o1: OUT BIT); END COMPONENT; COMPONENT n2 PORT (i1, i2: IN BIT; o1: OUT BIT); END COMPONENT; COMPONENT n3 PORT (i1, i2, i3: IN BIT; o1: OUT BIT); END COMPONENT; FOR ALL : n1 USE ENTITY WORK.inv_t (average_delay); FOR ALL : n2 USE ENTITY WORK.nand2_t (average_delay); FOR ALL : n3 USE ENTITY WORK.nand3_t (average_delay);-- Intermediate signals SIGNAL im1,im2, im3, im4, im5, im6, im7, im8, im9, im10 : BIT;BEGIN-- a_gt_b output g0 : n1 PORT MAP (a, im1); g1 : n1 PORT MAP (b, im2); g2 : n2 PORT MAP (a, im2, im3); g3 : n2 PORT MAP (a, gt, im4); g4 : n2 PORT MAP (im2, gt, im5); g5 : n3 PORT MAP (im3, im4, im5, a_gt_b);-- a_eq_b output g6 : n3 PORT MAP (im1, im2, eq, im6); g7 : n3 PORT MAP (a, b, eq, im7); g8 : n2 PORT MAP (im6, im7, a_eq_b);-- a_lt_b output g9 : n2 PORT MAP (im1, b, im8); g10 : n2 PORT MAP (im1, lt, im9); g11 : n2 PORT MAP (b, lt, im10); g12 : n3 PORT MAP (im8, im9, im10, a_lt_b);END default_delay;

• Many alternatives for specifying generics• Using default values for the generics of logic gates• No need to declare and specify generics if they are to

use default values



ARCHITECTURE fixed_delay OF bit_comparator IS COMPONENT n1 GENERIC (tplh, tphl : TIME); PORT (i1: IN BIT; o1: OUT BIT); END COMPONENT; COMPONENT n2 GENERIC (tplh, tphl : TIME); PORT (i1, i2: IN BIT; o1: OUT BIT); END COMPONENT; COMPONENT n3 GENERIC (tplh, tphl : TIME); PORT (i1, i2, i3: IN BIT; o1: OUT BIT); END COMPONENT; FOR ALL : n1 USE ENTITY WORK.inv_t (average_delay); FOR ALL : n2 USE ENTITY WORK.nand2_t (average_delay); FOR ALL : n3 USE ENTITY WORK.nand3_t (average_delay); SIGNAL im1,im2, im3, im4, im5, im6, im7, im8, im9, im10 : BIT;BEGIN-- a_gt_b output g0 : n1 GENERIC MAP (2 NS, 4 NS) PORT MAP (a, im1); g1 : n1 GENERIC MAP (2 NS, 4 NS) PORT MAP (b, im2); g2 : n2 GENERIC MAP (3 NS, 5 NS) PORT MAP (a, im2, im3); g3 : n2 GENERIC MAP (3 NS, 5 NS) PORT MAP (a, gt, im4); g4 : n2 GENERIC MAP (3 NS, 5 NS) PORT MAP (im2, gt, im5); g5 : n3 GENERIC MAP (4 NS, 6 NS) PORT MAP (im3, im4, im5, a_gt_b);-- a_eq_b output g6 : n3 GENERIC MAP (4 NS, 6 NS) PORT MAP (im1, im2, eq, im6); g7 : n3 GENERIC MAP (4 NS, 6 NS) PORT MAP (a, b, eq, im7); g8 : n2 GENERIC MAP (3 NS, 5 NS) PORT MAP (im6, im7, a_eq_b);-- a_lt_b output g9 : n2 GENERIC MAP (3 NS, 5 NS) PORT MAP (im1, b, im8); g10 : n2 GENERIC MAP (3 NS, 5 NS) PORT MAP (im1, lt, im9); g11 : n2 GENERIC MAP (3 NS, 5 NS) PORT MAP (b, lt, im10); g12 : n3 GENERIC MAP (4 NS, 6 NS) PORT MAP (im8, im9, im10, a_lt_b);END fixed_delay;

• If generics are declared without default values, theyhave to be specified

• Associating fixed values with the generics of logic gates• Generic map is shown here



• Syntax details• Component instantiation statement with generic map

aspect• Generic map aspect comes first

b, im2

PORT MAP

2 NS, 4 NS

GENERIC MAP

:

;

instantiation_label

component_name

association_list

association_list

genericmapaspect

portmapaspect


g1

n1

(

)

(

)



ENTITY bit_comparator_t IS GENERIC (tplh1, tplh2, tplh3, tphl1, tphl2, tphl3 : TIME); PORT (a, b, -- data inputs gt, -- previous greater than eq, -- previous equal lt : IN BIT; -- previous less than a_gt_b, -- greater a_eq_b, -- equal a_lt_b : OUT BIT); -- less thanEND bit_comparator_t;

(a)

ARCHITECTURE passed_delay OF bit_comparator_t IS COMPONENT n1 GENERIC (tplh, tphl : TIME); PORT (i1: IN BIT; o1: OUT BIT); END COMPONENT; COMPONENT n2 GENERIC (tplh, tphl : TIME); PORT (i1, i2: IN BIT; o1: OUT BIT); END COMPONENT; COMPONENT n3 GENERIC (tplh, tphl : TIME); PORT (i1, i2, i3: IN BIT; o1: OUT BIT); END COMPONENT; FOR ALL : n1 USE ENTITY WORK.inv_t (average_delay); FOR ALL : n2 USE ENTITY WORK.nand2_t (average_delay); FOR ALL : n3 USE ENTITY WORK.nand3_t (average_delay);-- Intermediate signals SIGNAL im1,im2, im3, im4, im5, im6, im7, im8, im9, im10 : BIT;BEGIN . . .

• A bit comparator with timing parameters• Passing generics of bit comparator to its components• Bit comparator has generic parameters that must be

passed to it



. . .-- a_gt_b output g0 : n1 GENERIC MAP (tplh1, tphl1) PORT MAP (a, im1); g1 : n1 GENERIC MAP (tplh1, tphl1) PORT MAP (b, im2); g2 : n2 GENERIC MAP (tplh2, tphl2) PORT MAP (a, im2, im3); g3 : n2 GENERIC MAP (tplh2, tphl2) PORT MAP (a, gt, im4); g4 : n2 GENERIC MAP (tplh2, tphl2) PORT MAP (im2, gt, im5); g5 : n3 GENERIC MAP (tplh3, tphl3) PORT MAP (im3, im4, im5,a_gt_b);-- a_eq_b output g6 : n3 GENERIC MAP (tplh3, tphl3) PORT MAP (im1, im2, eq, im6); g7 : n3 GENERIC MAP (tplh3, tphl3) PORT MAP (a, b, eq, im7); g8 : n2 GENERIC MAP (tplh2, tphl2) PORT MAP (im6, im7, a_eq_b);-- a_lt_b output g9 : n2 GENERIC MAP (tplh2, tphl2) PORT MAP (im1, b, im8); g10 : n2 GENERIC MAP (tplh2, tphl2) PORT MAP (im1, lt, im9); g11 : n2 GENERIC MAP (tplh2, tphl2) PORT MAP (b, lt, im10); g12 : n3 GENERIC MAP (tplh3, tphl3) PORT MAP (im8, im9, im10,a_lt_b);END passed_delay;

• A bit comparator with timing parameters• Gates require generic specification• These override the gate generics



• Composition aspect of bit_comparator_t• Dotted lines with arrows indicate generics

inv_ti1 o1

nand2_ti1

o1i2

nand3_ti1

o1i2

i3

nand2_ti1

o1i2

nand2_ti1

o1i2

nand3_ti1

o1i2i3

nand3_ti1

o1i2i3

nand2_ti1

o1i2

nand2_ti1

o1i2

nand2_ti1

o1i2

nand2_ti1

o1i2

nand3_ti1

o1i2

i3

im3

im4

im5

im6

im7

im8

im9

im10

a_gt_b

a_eq_b

a_lt_binv_t

i1 o1

bit_comparator_t (passed_delay)

a

b

gt

eq

lt

im2

im1

(average_delay)

(average_delay)

(average_delay)

(average_delay) (average_delay)

(average_delay)

(average_delay)

(average_delay)

(average_delay)(average_delay)

(average_delay)

(average_delay)

(average_delay)

tplh tphl

tplh

tplhtplh

tplh

tplh

tplh

tplh

tplh

tplhtplh tplh

tplh

tphl

tphl

tphl

tphl

tphl

tphl

tphl

tphl

tphltphl

tphl

tphl

tplh1 tphl1 tplh2 tphl2 tplh3 tphl3



ARCHITECTURE iterative OF nibble_comparator IS

COMPONENT comp1 GENERIC (

tplh1 : TIME := 2 NS; tplh2 :TIME := 3 NS; tplh3 : TIME := 4 ns;tplh1 : TIME := 4 NS; tplh2 :TIME := 5 NS; tplh3 : TIME := 6 ns;

PORT (a, b, gt, eq, lt : IN BIT; a_gt_b, a_eq_b, a_lt_b : OUT BIT); END COMPONENT;

FOR ALL : comp1 USE ENTITY WORK.bit_comparator_t (passed_delay); SIGNAL im : BIT_VECTOR ( 0 TO 8);BEGIN c0: comp1 PORT MAP (a(0), b(0), gt, eq, lt, im(0), im(1), im(2)); c1to2: FOR i IN 1 TO 2 GENERATE c: comp1 PORT MAP (a(i), b(i), im(i*3-3), im(i*3-2), im(i*3-1), im(i*3+0), im(i*3+1), im(i*3+2) ); END GENERATE; c3: comp1 PORT MAP (a(3), b(3), im(6), im(7), im(8), a_gt_b, a_eq_b, a_lt_b);END iterative;

• Comp1 is declared with default values• Passing default values of local generics to the generics

of bit_comparator_t• These values override at the lower levels



ARCHITECTURE iterative OF nibble_comparator IS . . .BEGIN c0: comp1

GENERIC MAP (OPEN, OPEN, 8 NS, OPEN, OPEN, 10 NS)PORT MAP (a(0), b(0), gt, eq, lt, im(0), im(1), im(2));

. . .END iterative;

• Some are associated with OPEN• Associating constants with some of generics of

bit_comparator_t, and using defaults for others• Association by position, correspond in the order they

are listed



ARCHITECTURE iterative OF nibble_comparator IS . . .BEGIN c0: comp1

GENERIC MAP (tplh3 => 8 NS, tphl3 => 10 NS)PORT MAP (a(0), b(0), gt, eq, lt, im(0), im(1), im(2));

. . .END iterative;

SAME FORMAT FOR THE PORTS:

PORT AS DECLARED:PORT (a, b, gt, eq, lt : IN BIT; a_gt_b, a_eq_b, a_lt_b : OUT BIT);

ARCHITECTURE BECOMES:ARCHITECTURE iterative OF nibble_comparator IS . . .BEGIN c0: comp1

GENERIC MAP (tplh3 => 8 NS, tphl3 => 10 NS)PORT MAP

(a => a(0), b => b(0), gt => gt, eq => eq, lt => lt,a_gt_b => im(0), a_eq_b => im(1), a_lt_b => im(2));

. . .END iterative;

• Using named association, same mapping as before• It must be: as_in_declaration => local_value• Order is not significant• Leave open or use a_gt_b => OPEN• Outputs can be left open, inputs only if default


Design Configuration

USE WORK.basic_utilities.ALL;ARCHITECTURE customizable OF nibble_comarator_test_bench IS COMPONENT comp4 PORT ( a, b : IN BIT_VECTOR (3 DOWNTO 0); gt, eq, lt : IN BIT; a_gt_b, a_eq_b, a_lt_b : OUT BIT); END COMPONENT; SIGNAL a, b : BIT_VECTOR (3 DOWNTO 0); SIGNAL eql, lss, gtr : BIT; SIGNAL vdd : BIT := '1'; SIGNAL gnd : BIT := '0';BEGIN a1: comp4 PORT MAP (a, b, gnd, vdd, gnd, gtr, eql, lss); apply_data (a, (0,15,15,14,14,14,14,10,00,15,00,00,15), 500 NS); apply_data (b, (0,14,14,15,15,12,12,12,15,15,15,00,00), 500 NS);END customizable;

• A customizable test bench• Configuration specification is not included• Comp4 is not in our work library

Customizable architecturefor demonstratingconfiguration declarations



• Configuring customizable for testing structuralarchitecture of nibble_comparator

• Hierarchically enter the architecture, perform binding

USE WORK.ALL;CONFIGURATION functional OF nibble_comparator_test_bench IS FOR customizable FOR a1 : comp4 USE ENTITY WORK.nibble_comparator(structural); END FOR; END FOR;END functional;

1 2 3



• Graphical representation• Composition aspect for functional configuration

declaration, configuring customizable test bench• Pass through hierarchies with arrows

a1: comp4

a(3:0)

b(3:0)

gt

eq

lt

a_gt_b

a_eq_b

a_lt_b

nibble_comparator (structural)

nibble_comparator_test_bench (customizable)

functional



USE WORK.ALL;CONFIGURATION average_delay OF nibble_comparator_test_bench IS FOR customizable FOR a1 : comp4 USE ENTITY WORK.nibble_comparator(iterative); END FOR; END FOR;END average_delay;

• Another configuration on top of the test bench• Configuring customizable for testing iterative

architecture of nibble_comparator• No need to recompile the test bench



• Details of configuration declaration• Configuration declaration replaces or adds to a

configuration specification• Includes component configuration and block

configuration

componentconfiguration

USE

FOR customizable

test_bench

average_delay

nibble_

WORK.

(iterative)

END FOR;

END average_delay;

CONFIGURATION

OF

comparator_

IS

FOR al : comp4

ENTITY

nibble_comparator

;

END FOR;

identifier

entity_name

bindingindication

blockconfiguration

configurationdeclaration



ARCHITECTURE flexible OF nibble_comparator IS COMPONENT comp1 PORT (a, b, gt, eq, lt : IN BIT; a_gt_b, a_eq_b, a_lt_b : OUT BIT); END COMPONENT; SIGNAL im : BIT_VECTOR ( 0 TO 8);BEGIN c0: comp1 PORT MAP (a(0), b(0), gt, eq, lt, im(0), im(1), im(2)); c1to2: FOR i IN 1 TO 2 GENERATE c: comp1 PORT MAP (a(i), b(i), im(i*3-3), im(i*3-2), im(i*3-1), im(i*3+0), im(i*3+1), im(i*3+2) ); END GENERATE; c3: comp1 PORT MAP (a(3), b(3), im(6), im(7), im(8), a_gt_b, a_eq_b, a_lt_b);END flexible;

• A general purpose nibble_comparator• This 4-bit comparator does not use a specific bit

comparator• A top-level configuration configures comp1

instantiations



• Composition aspect for configuring customizable testbench for testing default_delay bit_comparator

• Graphical representation of hierarchies


a_gt_bgt

eq

lt a_lt_b

a_eq_b

c3: comp1

a(3:0)

a_gt_b

b(3:0)

gt

eq

lt a_lt_b

a_eq_b

a(3:0)

a_gt_b

b(3:0)

gt

eq

lt a_lt_b

a_eq_b

a(3:0)

a_gt_b

b(3:0)

gt

eq

lt a_lt_b

a_eq_b

a_gt_b

a_eq_b

a_lt_b

a(3)

b(3)

a(2)

b(2)

a(1)

b(1)

a(0)

b(0)

c1to2:

im(6)

im(7)

im(8)

im(3)

im(4)

im(5)

im(0)

im(1)

im(2)

gt

eq

lt

a(3:0)

b(3:0)a(3:0)

b(3:0)

c2: comp1

c1: comp1

c0: comp1

default_bit_level

bit_comparator(default_delay) nibble_comparator(flexible)

a1: c

omp4



USE WORK.ALL;CONFIGURATION default_bit_level OF nibble_comparator_test_bench IS FOR customizable FOR a1 : comp4 USE ENTITY WORK.nibble_comparator(flexible); FOR flexible FOR c0, c3: comp1 USE ENTITY WORK.bit_comparator (default_delay); END FOR; FOR c1to2 FOR c: comp1 USE ENTITY WORK.bit_comparator (default_delay); END FOR; END FOR; END FOR; END FOR; END FOR;END default_bit_level;

• Configuration declaration for configuring customizabletest bench for testing default_delay bit_comparator

• Binding to the default_delay architecture



USE WORK.ALL;CONFIGURATION fixed_bit_level OF nibble_comparator_test_bench IS FOR customizable FOR a1 : comp4 USE ENTITY WORK.nibble_comparator(flexible); FOR flexible FOR c0, c3: comp1 USE ENTITY WORK.bit_comparator (fixed_delay); END FOR; FOR c1to2 FOR c: comp1 USE ENTITY WORK.bit_comparator (fixed_delay); END FOR; END FOR; END FOR; END FOR; END FOR;END fixed_bit_level;

• Configuring customizable test bench for testing thefixed_delay architecture of bit_comparator

• Binding to the fixed_delay architecture• Can use ALL or OTHERS



• Composition aspect of the passed_bit_level• Configuration for test bench for testing passed_delay

architecture of bit_comparator_t


a_gt_bgt

eq

lt a_lt_b

a_eq_b

c3: comp1

a(3:0)

a_gt_b

b(3:0)

gt

eq

lt a_lt_b

a_eq_b

a(3:0)

a_gt_b

b(3:0)

gt

eq

lt a_lt_b

a_eq_b

a(3:0)

a_gt_b

b(3:0)

gt

eq

lt a_lt_b

a_eq_b

a_gt_b

a_eq_b

a_lt_b

a(3)

b(3)

a(2)

b(2)

a(1)

b(1)

a(0)

b(0)

im(6)

im(7)

im(8)

im(3)

im(4)

im(5)

im(0)

im(1)

im(2)

gt

eq

lt

a(3:0)

b(3:0)a(3:0)

b(3:0)

c2: comp1

c1: comp1

c0: comp1

passed_bit_level

bit_comparator_t(passed_delay) nibble_comparator(flexible)

a1: c

omp4

2NS3NS

4NS4NS5NS6NS

tplh1tplh2tplh3tphl1tphl2tphl3

2NS3NS

4NS4NS5NS6NS


2NS3NS

4NS4NS5NS6NS


c1to2:

2NS3NS

4NS4NS5NS6NS




USE WORK.ALL;CONFIGURATION passed_bit_level OF nibble_comparator_test_bench IS FOR customizable FOR a1 : comp4 USE ENTITY WORK.nibble_comparator(flexible); FOR flexible FOR c0, c3: comp1 USE ENTITY WORK.bit_comparator_t (passed_delay) GENERIC MAP (tplh1 => 2 NS, tplh2 => 3 NS, tplh3 => 4 NS, tphl1 => 4 NS, tphl2 => 5 NS, tphl3 => 6 NS); END FOR; FOR c1to2 FOR c: comp1 USE ENTITY WORK.bit_comparator_t (passed_delay) GENERIC MAP (tplh1 => 2 NS, tplh2 => 3 NS, tplh3 => 4 NS, tphl1 => 4 NS, tphl2 => 5 NS, tphl3 => 6 NS); END FOR; END FOR; END FOR; END FOR; END FOR;END passed_bit_level;

• Using configuration declarations for componentbindings, and specification of generic parameters

• Same format for generic map and port map aspects asconfiguration specification

SYNTAX



• Details of a block configuration enclosing componentconfigurations and other block configurations

• Binding indication and generic map aspect

tphl2 => 5 NS, tphl3 => 6 NS);

(tplh1 => 2 NS, tplh2 => 3 NS,

(passed_delay)

FOR c0, c3: comp1

ENTITY

FOR c1to2

USE

WORK.bit_comparator_t

GENERIC MAP

USE

FOR flexible

WORK.bit_comparator_t

GENERIC MAP

tplh3 => 4 NS, tphl1 => 4 NS,

END FOR;

FOR c: comp1

ENTITY

(passed_delay)

tplh3 => 4 NS, tphl1 => 4 NS,

END FOR;

(tphl1 => 2 NS, tplh2 => 3 NS,

tphl2 => 5 NS, tphl3 => 6 NS);

END FOR;


entityaspect

END FOR;

blockconfigurationgeneric

mapaspect


blockconfiguration



ARCHITECTURE partially_flexible OF nibble_comparator IS COMPONENT comp1 PORT (a, b, gt, eq, lt : IN BIT; a_gt_b, a_eq_b, a_lt_b : OUT BIT); END COMPONENT;

FOR ALL :comp1 USE ENTITY WORK.bit_comparator_t (passed_delay);

SIGNAL im : BIT_VECTOR ( 0 TO 8 );BEGIN c0: comp1 PORT MAP ( . . . ); c1to2 : FOR i IN 1 TO 2 GENERATE c: comp1 PORT MAP ( . . . ); END GENERATE; c3: comp1 PORT MAP ( . . . );END partially_flexible;

• Can do incremental binding• Do some with configuration specification, and more

with configuration declaration• This is an illustration for the primary binding

indication



USE WORK.ALL;CONFIGURATION incremental OF nibble_comparator_test_bench IS FOR customizable FOR a1 : comp4 USE ENTITY WORK.nibble_comparator (partially_flexible); FOR flexible FOR c0, c3: comp1 GENERIC MAP (tplh1 => 2 NS, tplh2 => 3 NS, tplh3 => 4 NS, tphl1 => 4 NS, tphl2 => 5 NS, tphl3 => 6 NS); END FOR; FOR c1to2 FOR c: comp1 GENERIC MAP (tplh1 => 2 NS, tplh2 => 3 NS, tplh3 => 4 NS, tphl1 => 4 NS, tphl2 => 5 NS, tphl3 => 6 NS); END FOR; END FOR; END FOR; END FOR; END FOR;END incremental;

• Incremental binding indication illustration• Add generic map aspect to the existing binding• Can use different mappings

ENTITY sr_latch IS PORT (s, r, c : IN BIT; q : OUT BIT);END sr_latch;--ARCHITECTURE gate_level OF sr_latch IS COMPONENT

n2 PORT (i1, i2: IN BIT; o1: OUT BIT); END COMPONENT; SIGNAL im1, im2, im3, im4 : BIT;BEGIN g1 : n2 PORT MAP (s, c, im1); g2 : n2 PORT MAP (r, c, im2); g3 : n2 PORT MAP (im1, im4, im3); g4 : n2 PORT MAP (im3, im2, im4); q <= im3;END gate_level;

• A new example, illustrating configurations at severallevels of depth

• Unbound VHDL description of set-reset latch• Uses the same basic components

Customizable architecture,using a sequential example,several levels of hierarchy



ENTITY d_latch IS PORT (d, c : IN BIT; q : OUT BIT);END d_latch; --ARCHITECTURE sr_based OF d_latch IS COMPONENT

sr PORT (s, r, c : IN BIT; q : OUT BIT); END COMPONENT; COMPONENT

n1 PORT (i1: IN BIT; o1: OUT BIT); END COMPONENT; SIGNAL dbar : BIT;BEGIN c1 : sr PORT MAP (d, dbar, c, q); c2 : n1 PORT MAP (d, dbar);END sr_based;

• Building a D-latch• Add an inverter to the SR-latch• Unbound VHDL description of a D-latch• All gate level components are unbound



ENTITY d_register IS PORT (d : IN BIT_VECTOR; c : IN BIT; q : OUT BIT_VECTOR);END d_register;--ARCHITECTURE latch_based OF d_register IS COMPONENT

dl PORT (d, c : IN BIT; q : OUT BIT); END COMPONENT;BEGIN dr : FOR i IN d'RANGE GENERATE di : dl PORT MAP (d(i), c, q(i)); END GENERATE;END latch_based;

• Generically generate a register• Unbound VHDL description for an n-bit latch• Configuration specification is not included



• Composition aspect for configuring the latch_basedarchitecture of d_register

• Hierarchical configuration

i1i2

o1

i1

i1

i1

i2

i2

i2o1

o1

o1

g1:g3:

g2: g4:i1 o1c2:

c1:di:

i1i2

o1

i1

i1

i1

i2

i2

i2o1

o1

o1

g1:g3:

g2: g4:i1 o1c2:

c1:di:

2 NS

4 NS

5 NS

6 NS

2 NS

4 NS

5 NS

6 NS

i1i2

o1

i1

i1

i1

i2

i2

i2o1

o1

o1

g1:g3:

g2: g4:i1 o1c2:

c1:di:

i1i2

o1

i1

i1

i1

i2

i2

i2o1

o1

o1

g1:g3:

g2: g4:i1 o1c2:

c1:di:

2 NS

4 NS

5 NS

6 NS

2 NS

4 NS

5 NS

6 NS

3 NS

5 NS

3 NS

3 NS

5 NS

5 NS

5 NS3 NS

a v e r a g e _ g a t e _ d e l a y d _ l a t c h ( s r _ b a s e d )

Sr_l

atch

(ga

te_l

evel

)

inv_t

(ave

rage

_del

ay)

nand

2_t(

aver

age_

dela

y)



• Configuring d_register for using average_delay gates

USE WORK.ALL;CONFIGURATION average_gate_delay OF d_register IS FOR latch_based FOR dr FOR di : dl USE ENTITY WORK.d_latch(sr_based); FOR sr_based FOR c1 : sr USE ENTITY WORK.sr_latch(gate_level); FOR gate_level FOR g2, g4 : n2 USE ENTITY WORK.nand2_t(average_delay) GENERIC MAP (5 NS, 6 NS); END FOR; FOR g1, g3 : n2 USE ENTITY WORK.nand2_t(average_delay) GENERIC MAP (2 NS, 4 NS); END FOR; END FOR; END FOR; FOR c2 : n1 USE ENTITY WORK.inv_t(average_delay) GENERIC MAP (3 NS, 5 NS); END FOR; END FOR; END FOR; END FOR; END FOR;END average_gate_delay;

1 2 3 4 5 6 8

9

7

10



BlockNo.

ConfigurationType

PURPOSEVisibility or Binding to:

BecomesVisible by:

1ConfigurationDeclaration Main - -

2Block

Configuration Visibilitylatch_based

ARCHITECTUREFigure 6.46

1

3Block

Configuration Visibilitydr

GENERATE STATEMENTFigure 6.46

1, 2

4Component

Configuration Bindingdi instance of dl

Figure 6.46 1, 2, 3

5Block

Configuration Visibilitysr_based


1, 2, 3, 4

6Component

Configuration Bindingc1 instance of sr

Figure 6.45 1, 2, 3, 4, 5

7Component

Configuration Bindingc2 instance of sr

Figure 6.45 1, 2, 3, 4, 5

8Block

Configuration Visibilitygate_level


1, 2, 3, 4, 5, 6

9Component

Configuration Bindinginstances g2, g4 of n2

Figure 6.44 1, 2, 3, 4, 5, 6, 8

10Component

Configuration Bindinginstances g1, g3 of n2

Figure 6.44 1, 2, 3, 4, 5, 6, 8

• Analyzing configuration constructs of theaverage_gate_delay configuration of d_register

• Configuration declaration includes componentconfigurations and block configurations



USE WORK.ALL;CONFIGURATION single_gate_delay OF d_register IS FOR latch_based FOR dr FOR di : dl USE ENTITY WORK.d_latch(sr_based); FOR sr_based FOR c1 : sr USE ENTITY WORK.sr_latch(gate_level); FOR gate_level FOR g2, g4 : n2 USE ENTITY WORK.nand3(single_delay) PORT MAP (i1, i1, i2, o1); END FOR; FOR g1, g3 : n2 USE ENTITY WORK.nand2(single_delay); END FOR; END FOR; END FOR; FOR c2 : n1 USE ENTITY WORK.inv(single_delay); END FOR; END FOR; END FOR; END FOR; END FOR;END single_gate_delay;

• Configuring d_register for using single_delayarchitectures of inv and nand2

• Deep inside to reach basic gates and their genericparameters

ARCHITECTURE single OF d_register_test_bench IS COMPONENT reg PORT

(d : IN BIT_VECTOR (7 DOWNTO 0); c : IN BIT; q : OUT BIT_VECTOR (7 DOWNTO 0) ); END COMPONENT; FOR r8 : reg USE CONFIGURATION WORK.single_gate_delay; SIGNAL data, outdata : BIT_VECTOR (7 DOWNTO 0); SIGNAL clk : BIT;BEGIN r8: reg PORT MAP (data, clk, outdata); data <= X"00", X"AA" AFTER 0500 NS, X"55" AFTER 1500 NS; clk <= '0', '1' AFTER 0200 NS, '0' AFTER 0300 NS, '1' AFTER 0700 NS, '0' AFTER 0800 NS, '1' AFTER 1700 NS, '0' AFTER 1800 NS;END single;

• Demonstrating the use of configurations inconfiguration specifications

• Test bench for the single_delay architecture ofd_register



• The final example• Will illustrate indexing for alternative binding• Parity generator/checker circuit

im(1)

a(3)

im(0)

a(2)im(2)

a(4)

im(3)

a(5)

im(4)

a(6)

im(5)

a(7)

a(0)

a(1)

im(6)

even

odd

One more configurationdeclaration example,iterative hardware

ENTITY xor2_t IS GENERIC (tplh : TIME := 9 NS; tphl : TIME := 7 NS); PORT (i1, i2 : IN BIT; o1 : OUT BIT);END xor2_t;--ARCHITECTURE average_delay OF xor2_t ISBEGIN o1 <= i1 XOR i2 AFTER (tplh + tphl) / 2;END average_delay;----

ENTITY inv_t IS GENERIC (tplh : TIME := 5 NS; tphl : TIME := 3 NS); PORT (i1 : IN BIT; o1 : OUT BIT);END inv_t;--ARCHITECTURE average_delay OF inv_t ISBEGIN o1 <= NOT i1 AFTER (tplh + tphl) / 2;END average_delay;

• Components needed for this design• Timed XOR and INV gates needed for the design of the

parity circuit

ENTITY parity IS PORT (a : IN BIT_VECTOR (7 DOWNTO 0); odd, even : OUT BIT);END parity;--ARCHITECTURE iterative OF parity IS COMPONENT

x2 PORT (i1, i2: IN BIT; o1: OUT BIT); END COMPONENT; COMPONENT

n1 PORT (i1: IN BIT; o1: OUT BIT); END COMPONENT; SIGNAL im : BIT_VECTOR ( 0 TO 6 );BEGIN first: x2 PORT MAP (a(0), a(1), im(0)); middle: FOR i IN 1 TO 6 GENERATE m: x2 PORT MAP (im(i-1), a(i+1), im(i)); END GENERATE; last: odd <= im(6); inv: n1 PORT MAP (im(6), even);END iterative;

• Parity circuit description• No configuration specification for the inverter and the

exclusive OR gate



CONFIGURATION parity_binding OF parity IS FOR iterative FOR first : x2 USE ENTITY WORK.xor2_t (average_delay) GENERIC MAP (5 NS, 5 NS); END FOR; FOR middle (1 TO 5) FOR m : x2 USE ENTITY WORK.xor2_t (average_delay) GENERIC MAP (5 NS, 5 NS); END FOR; END FOR; FOR middle ( 6) FOR m : x2 USE ENTITY WORK.xor2_t (average_delay) GENERIC MAP (6 NS, 7 NS); END FOR; END FOR; FOR inv : n1 USE ENTITY WORK.inv_t (average_delay) GENERIC MAP (5 NS, 5 NS); END FOR; END FOR;END parity_binding;

• Parity circuit configuration declaration• Index label of the generate statement• Can use OTHERS, pick some, and OTHERS the rest


Use of Libraries

Value Representing'U' Uninitialized'X' Forcing Unknown'0' Forcing 0'1' Forcing 1'Z' High Impedance'W' Weak Unknown'L' Weak 0'H' Weak 1'-' Don't care

• None standard values• Std_logic logic value system• Satisfies most hardware design needs

Standard and user libraries,start with the nine-valuestandard logic


Use of Libraries

. U X 0 1 Z W L H -U 'U' 'U' '0' 'U' 'U' 'U' '0' 'U' 'U’X 'U' 'X' '0' 'X' 'X' 'X' '0' 'X' 'X'0 '0' '0' '0' '0' '0' '0' '0' '0' '0'1 'U' 'X' '0' '1' 'X' 'X' '0' '1' 'X’Z 'U' 'X' '0' 'X' 'X' 'X' '0' 'X' 'X'W 'U' 'X' '0' 'X' 'X' 'X' '0' 'X' 'X'L '0' '0' '0' '0' '0' '0' '0' '0' '0'H 'U' 'X' '0' '1' 'X' 'X' '0' '1' 'X'- 'U' 'X' '0' 'X' 'X' 'X' '0' 'X' 'X'

• AND table for std_logic type• All logic tables are defined and available• Changing BIT to std_logic works in most cases

Use of Libraries

LIBRARY IEEE;USE IEEE.std_logic_1164.ALL;--ENTITY nand2_t IS GENERIC (tplh : TIME := 6 NS; tphl : TIME := 4 NS); PORT (i1, i2 : IN std_logic; o1 : OUT std_logic);END nand2_t;--ARCHITECTURE average_delay_mvla OF nand2_t ISBEGIN o1 <= i1 NAND i2 AFTER (tplh + tphl) / 2;END average_delay_mvla;

• A two-input NAND gate in std_logic value system• Specify library and package• All basic functions are available in this package


Use of Libraries

LIBRARY ls7400 User: John Designer Date

simple_gates PACKAGE DECLARATION June 9, 1997inv ENTITY June 8, 1997inv(single_delay) ARCHITECTURE June 8, 1997nand2 ENTITY June 6, 1997nand2(single_delay) ARCHITECTURE June 6, 1997nand3 ENTITY June 6, 1997nand3(single_delay) ARCHITECTURE June 6, 1997

• Other libraries• Can define our own• Directory of ls7400 library containing package

declarations, entities and architectures


Use of Libraries

• WORK is the default library,

• STD is the standard library that includes the STANDARD and

TEXTIO packages

• All other libraries and packages must be explicitly specified

• Use ls7400 as a user defined library

LIBRARY ls7400;USE ls7400.simple_gates.ALL;

• Visibility of user libraries and packages• Making all declarations of simple_gates package of

ls7400 library available

Use of Libraries

LIBRARY ls7400;USE ls7400.simple_gates.ALL;--ARCHITECTURE gate_level OF sr_latch IS SIGNAL im1, im2, im3, im4 : BIT;BEGIN g1 : n2 PORT MAP (s, c, im1); g2 : n2 PORT MAP (r, c, im2); g3 : n2 PORT MAP (im1, im4, im3); g4 : n2 PORT MAP (im3, im2, im4); q <= im3;END gate_level;

• Using user libraries• Using component declarations of simple_gates package

of ls7400 library for description of set-reset latch


Use of Libraries

LIBRARY ls7400;USE ls7400.ALL;

• Visibility into libraries• Making all entities and architectures of the ls7400

library available


Use of Libraries

LIBRARY ls7400;USE ls7400.ALL;..… FOR g1, g3 : n2… USE ENTITY ls7400.nand2 (single_delay);… END FOR;

• Binding indication needs library name• Using a component configuration for associating g1

and g3 instances of n2 of Figure 661 with nand2 ofls7400


Summary

This chapter provides tools for better hardware

descriptions and design organization. We began with the

definition of subprograms and emphasized on the use of

functions and procedures for simplifying descriptions.

Next, the subject of packaging utilities and components was

addressed. As stated earlier, this topic is used mainly for

the organization of a design. Design parameterization and

configuration of designs were also discussed in great detail.

Although simple examples and college level exercises can

avoid some of these language issues, a large design

environment with many logic families and technologies to

choose from requires a great deal of library management

and parameter specification. We believe VHDL is very

strong in this area and serious designers should learn to

take advantage of such capabilities of the language. For

small circuits and experimental models, design

parameterization methods save many compilation runs.



CHAPTER 7UTILITIES FOR HIGH LEVEL

DESCRIPTIONS

7.1 TYPE DECLARATIONS AND USAGE7.1.1 Enumeration Type for Multi-Value Logic7.1.2 Using Real Numbers For Timing Calculations7.1.3 Physical Types and RC Timing7.1.4 Array Declarations7.1.5 File Type and External File I/O

7.2 VHDL OPERATORS7.2.1 Logical Operators7.2.2 Relational Operators7.2.3 Shift Operators7.2.4 Adding Operators7.2.5 Sign Operators7.2.6 Multiplying Operators7.2.7 Nota Operators7.2.8 Aggregate Operation

7.3 SUBPROGRAM PARAMETER TYPES AND OVERLOADING7.4 OTHER TYPES AND TYPE RELATED ISSUES

7.4.1 Subtypes7.4.2 Record Types7.4.3 Alias Declaration7.4.4 Access Types7.4.5. Global Objects7.4.6 Type Conversions

7.5 PREDEFINED ATTRIBUTES7.5.1 Array Attributes7.5.2 Type Attributes7.5.3 Signal Attributes7.5.4 Entity Attributes

7.6 USER-DEFINED ATTRIBUTES7.7 PACKAGING BASIC UTILITIES7.8 SUMMARY


TYPE DECLARATIONS AND USAGE

• 4-value qit type will be used• Enumeration type declaration• Initial value of objects of this type is the left-most

enumeration element of the base type

enumeration element

)

,

,

,

(

qitTYPE

IS

‘0’

‘1’

‘Z’

‘X’

;

identifier

enumeration element

enumeration element

enumeration element

enumerationtypedefinition

typedefinition

typedeclaration

Will use an enumeration typefor demonstrating typedeclarations

TYPE qit IS ('0', '1', 'Z', 'X');initial



• Will develop basic logic gates based on this type• Input-Output mapping of an inverter in qit logic value

system

Out

0

1

X

Z

In: 1

0

0

X

USE WORK.basic_utilities.ALL;-- From PACKAGE USE : qitENTITY inv_q IS GENERIC (tplh : TIME := 5 NS; tphl : TIME := 3 NS); PORT (i1 : IN qit; o1 : OUT qit);END inv_q;--ARCHITECTURE double_delay OF inv_q ISBEGIN o1 <= '1' AFTER tplh WHEN i1 = '0' ELSE '0' AFTER tphl WHEN i1 = '1' OR i1 = 'Z' ELSE 'X' AFTER tplh;END double_delay;

• VHDL description of an inverter in qit logic value system• Inputs and outputs are of type qit• Assumes out package contains this type definition

Z <= a AFTER 5 NS WHEN d = ’1’ ELSEUNAFFECTED WHEN e = ’1’ ELSEb AFTER 5 NS WHEN f = ’1’ ELSEc AFTER 5 NS;

o1<= ‘1’ AFTER tplh WHEN i1 = ‘0’ ELSE‘0’ AFTER tphl WHEN i1 = ‘1’ OR i1 = ‘Z’ ELSEUNAFFECTED;

o1 <= a WHEN cond =’1’ ELSE o1;or

o1 <= a WHEN cond =’1’ ELSE UNAFFECTED;

• A new construct is presented• This is conditional signal assignment• Several alternatives exist in its usage• Can use unaffected for assignments to outputs

• Syntax details of a conditional signal assignment• Condition waveform has a series of waveforms with or

without condition

ELSE

WHEN

ELSE

WHEN

<=o1 target

conditionwaveform

‘1’ AFTER tplh

i1 = ‘0’

‘0’ AFTER tphl

i1 = ‘1’ OR i1 = ‘Z’

‘X’ AFTER tplh

waveform

condition

waveform

condition

waveform

;

conditionalsignalassignment



• We will develop more basic structures in this 4-value logicsystem

• Input-Output mapping of a NAND gate in qit logic valuesystem

• Here we assume 1 for high impedance

0 1In1: Z X

Out

0

1

X

Z

In2: 1

1

1

0

0

X

1

0

0

X

1

X

X

1 X

1

USE WORK.basic_utilities.ALL;-- FROM PACKAGE USE : qitENTITY nand2_q IS GENERIC (tplh : TIME := 7 NS; tphl : TIME := 5 NS); PORT (i1, i2 : IN qit; o1 : OUT qit);END nand2_q;--ARCHITECTURE double_delay OF nand2_q ISBEGIN o1 <= '1' AFTER tplh WHEN i1 = '0' OR i2 = '0' ELSE '0' AFTER tphl WHEN (i1 = '1' AND i2 = '1') OR (i1 = '1' AND i2 = 'Z') OR (i1 = 'Z' AND i2 = '1') OR (i1 = 'Z' AND i2 = 'Z') ELSE 'X' AFTER tplh; -- Can Use: UNAFFECTED;END double_delay;

• VHDL description of a NAND gate in qit logic system• A conditional signal assignment is used• This is a concurrent statement• Conditions are checked sequentially from left to right



• Composition aspect of an inverter with RC timing• Timing depends on the R and C values• Exponential timing is ≅≅ 3RC• Will first demonstrate floating point numbers

Ω

Ω

inv_rc(double_delay)

c_load

o1i1

25K

15K

A CMOS inverter examplefor demonstrating floatingpoint and physical types

USE WORK.basic_utilities.ALL;-- FROM PACKAGE USE: qitENTITY inv_rc IS GENERIC (c_load : REAL := 0.066E-12); -- Farads PORT (i1 : IN qit; o1 : OUT qit); CONSTANT rpu : REAL := 25000.0; -- Ohms CONSTANT rpd : REAL := 15000.0; -- OhmsEND inv_rc;--ARCHITECTURE double_delay OF inv_rc IS CONSTANT tplh : TIME := INTEGER ( rpu * c_load * 1.0E15) * 3 FS; CONSTANT tphl : TIME := INTEGER ( rpd * c_load * 1.0E15) * 3 FS;BEGIN o1 <= '1' AFTER tplh WHEN i1 = '0' ELSE '0' AFTER tphl WHEN i1 = '1' OR i1 = 'Z' ELSE 'X' AFTER tplh;END double_delay;

• An inverter model with RC timing parameters• Delay cannot be a fraction of FS• Delay values are calculated based on pull-up, oull-down

and load capacitance• Constant values are used in the conditional signal

assignment



TYPE capacitance IS RANGE 0 TO 1E16 UNITS ffr; -- Femto Farads (base unit) pfr = 1000 ffr; nfr = 1000 pfr; ufr = 1000 nfr; mfr = 1000 ufr; far = 1000 mfr; kfr = 1000 far; END UNITS;

• Type definition for defining the capacitance physical type• Use physical types instead of floating point• Base unit must be there• All others are then defined



TYPE resistance IS RANGE 0 TO 1E16 UNITS l_o; -- Milli-Ohms (base unit) ohms = 1000 l_o; k_o = 1000 ohms; m_o = 1000 k_o; g_o = 1000 m_o; END UNITS;

• Type definition for defining the resistance physical type• Another physical type• RANGE specifies the largest value in terms of base units

that an object of this type can get• Intermediate values can take larger values

USE WORK.basic_utilities.ALL;-- FROM PACKAGE USE: qit, resistance, capacitanceENTITY inv_rc IS GENERIC (c_load : capacitance := 66 ffr); PORT (i1 : IN qit; o1 : OUT qit); CONSTANT rpu : resistance := 25000 ohms; CONSTANT rpd : resistance := 15000 ohms;END inv_rc;--ARCHITECTURE double_delay OF inv_rc IS CONSTANT tplh : TIME := (rpu / 1 l_o) * (c_load / 1 ffr) * 3 FS / 1000; CONSTANT tphl : TIME := (rpd / 1 l_o) * (c_load / 1 ffr) * 3 FS / 1000;BEGIN o1 <= '1' AFTER tplh WHEN i1 = '0' ELSE '0' AFTER tphl WHEN i1 = '1' OR i1 = 'Z' ELSE 'X' AFTER tplh;END double_delay;

• Using resistance and capacitance physical types in thedescription of an inverter

• Resolutions of Millie-ohms and Femto-farads are takeninto account

• Divide by 1000 adjusts the time units to FS• Will do it with a better style later



TYPE qit_nibble IS ARRAY ( 3 DOWNTO 0 ) OF qit;

TYPE qit_byte IS ARRAY ( 7 DOWNTO 0 ) OF qit;

TYPE qit_word IS ARRAY ( 15 DOWNTO 0 ) OF qit;

TYPE qit_4by8 IS ARRAY ( 3 DOWNTO 0, 0 TO 7 ) OF qit;

TYPE qit_nibble_by_8 IS ARRAY ( 0 TO 7 ) OF qit_nibble;

• Declaring array types• Arrays may be ascending or descending• Objects can be indexed as declared• n-dimensional arrays may be declared

Demonstrating arraydefinition and objectdeclaration



• Syntax details of an array type declaration• This is a type declaration• Contains constraint array definition

identifier

OF

0

7

ARRAY

qit_byteTYPE

IS

(

DOWNTO

)

qit;

discreterange

range indexconstrained

constraintarraydefinition

typedeclaration

element_subtype_indication



SIGNAL sq8 : qit_byte := "ZZZZZZZZ";

SIGNAL sq8 : qit_byte := (‘Z’, ‘Z’, ‘Z’, ‘Z’, ‘1’, ‘1’, ‘1’, ‘1’);

SIGNAL sq8 : qit_byte := (5 => ‘Z’, OTHERS => ‘1’);

SIGNAL sq8 : qit_byte := (1 DOWN TO 0 => ‘Z’,OTHERS => ‘1’);

SIGNAL sq8 : qit_byte := (1 DOWN TO 0 => ‘Z’,3 TO 4 => ‘X’,OTHERS => ‘1’);

• Objects of array type may be initialized when declared• If explicit initialization is missing, all elements are

initialized to left-most of array element• Can form a vector of initial values• Can use aggregate operation, association by position• Can use aggregate operation, association by name

Signal Declarations:

SIGNAL sq1 : qit;SIGNAL sq4 : qit_nibble;SIGNAL sq8 : qit_byte;SIGNAL sq16 : qit_word;SIGNAL sq_4_8 : qit_4by_8;SIGNAL sq_nibble_8 : qit_nibble_by_8;

Valid Operations:

sq8 <= sq16 (11 DOWNTO 4); -- middle 8 bit slice of sq16 to sq8;sq16 (15 DOWNTO 12) <= sq4; -- sq4 into left 4 bit slice of sq16;sq1 <= sq_4_8 (0, 7); -- lower right bit of sq_4_8 into sq1;sq4 <= sq_nibble_8 (2); -- third nibble (number 2) of sq_nibble_8 into sq4;sq1 <= sq_nibble_8(2)(3); -- nibble 2, bit 3 of sq_nibble_8 into sq1;sq8 <= sq8(0) & sq8 (7 DOWNTO 1); -- right rotate sq8;sq4 <= sq8(2) & sq8(3) & sq8(4) & sq8(5); -- reversing sq8 into sq4;sq4 <= (sq8(2), sq8(3), sq8(4), sq8(5)); -- reversing sq8 into sq4;(sq4(0), sq4(1), sq4(2), sq4(3)) <= sq8 (5 DOWNTO 2);-- reversing sq8 into sq4;

• Signal declarations and signal assignments• Arrays may be sliced and used on RHS or LHS• Aggregate may be used on RHS and LHS• Can concatenate any length or slice size• Aggregates operation works with array elements only

Concatenation example:

Slice example:

sq_nibble_8(2)(3 DOWN To 2)

• Referencing bits of a vector; reversing bits of sq8 andassigning them to sq4

• Cannot index opposite to what the type is defined as.Nice try!

• An slicing example is also shown here

3 2 1 0 7 6 5 4 3 2 1 0sq4: sq8:

sq4 <= sq8(2) & sq8(3) & sq8(4) & sq8(5);

SIGNAL sq_4_8 : qit_4by8 := ( ( '0', '0', '1', '1', 'Z', 'Z', 'X', 'X' ), ( 'X', 'X', '0', '0', '1', '1', 'Z', 'Z' ), ( 'Z', 'Z', 'X', 'X', '0', '0', '1', '1' ), ( '1', '1', 'Z', 'Z', 'X', 'X', '0', '0' ) );

SIGNAL sq_4_8 : qit_4by8 := (OTHERS => “11000000”);

SIGNAL sq_4_8 : qit_4by8 := (OTHERS => (OTHERS => ‘Z’));

SIGNAL sq_4_8 : qit_4by8 := (OTHERS => (0 TO 1 => ‘1’, OTHERS =>’0’));

SIGNAL sq_4_8 : qit_4by8 := (OTHERS => (0 TO 1 => ‘1’, OTHERS =>’0’));

… := (OTHERS => (OTHERS => ‘0’))

sq_4_8 <= ( 3 => (OTHERS => ‘X’), 0 => (OTHERS => ‘X’),OTHERS => (0 => ‘X’, 7 => ‘X’, OTHERS =>’1’);

• Initializing or assignment to a two dimensional array• Right most index applies to deepest set of parenthesis• Can initialize the same way as signal and variable

assignment• Constants must have static values



TYPE qit_2d IS ARRAY (qit, qit) OF qit;

CONSTANT qit_nand2_table : qit_2d := (‘0’ => (OTHERS => ‘1’),‘X’ => (‘0’ => ‘1’, OTHERS => ‘X’),OTHERS => (‘0’ => ‘1’, ‘X’ => ‘1’, OTHERS =>’0’));

• Instead of integers, can use other types for array rangespecification

• Then an object of this type may be indexed byenumeration elements of the type in the array rangespecification

Demonstrating non-integerRANGE and indexspecification

USE WORK.basic_utilities.ALL;-- FROM PACKAGE USE: qit, qit_2dENTITY nand2_q IS GENERIC (tplh : TIME := 7 NS; tphl : TIME := 5 NS); PORT (i1, i2 : IN qit; o1 : OUT qit);END nand2_q; --ARCHITECTURE average_delay OF nand2_q IS CONSTANT qit_nand2_table : qit_2d := ( ('1','1','1','1'), ('1','0','0','X'), ('1','0','0','X'), ('1','X','X','X'));BEGIN o1 <= qit_nand2_table (i1, i2) AFTER (tplh + tphl) / 2;END average_delay;

• Using qit enumeration type for the discrete range of atwo-dimensional array

• The constant table is an array qit qit if qit elements

TYPE BIT_VECTOR ISARRAY (NATURAL RANGE <>) OF BIT;

TYPE STRING ISARRAY (POSITIVE RANGE <>) OF CHARACTER;

TYPE integer_vector ISARRAY (NATURAL RANGE <>) OF INTEGER;

• BIT_VECTOR is a predefined unconstrained array ofBITs

• STRING is that of CHARACTERS• Can define our own• This is read as RANGE Box

Unconstrained arraydeclarations, usage anddefinition

• Syntax details of an unconstrained array declaration• We will use this array in our basic utilities• Cannot have unconstrained array of an unconstrained

array; Nice try!

identifier

OF

<>

NATURAL

ARRAY

integer_vectorTYPE

IS

(

RANGE

)

INTEGER;

index_subtypedefinition

unconstrainedarraydefinition

typedeclaration

element_subtype_indication

type_mark

PROCEDURE apply_data (SIGNAL target : OUT BIT_VECTOR;CONSTANT values : IN integer_vector;CONSTANT period : IN TIME) IS

VARIABLE buf : BIT_VECTOR (target'RANGE); BEGIN FOR i IN values'RANGE LOOP int2bin (values(i), buf); target <= TRANSPORT buf AFTER i * period; END LOOP; END apply_data;

• A generic version of the apply_data procedure• Uses our own integer_vector from basic_utilities• Procedure output, target, is also unconstrained• All will be known when procedure is called

ENTITY n_bit_comparator IS PORT (a, b : IN BIT_VECTOR; gt, eq, lt : IN BIT; a_gt_b, a_eq_b, a_lt_b : OUT BIT);END n_bit_comparator;--ARCHITECTURE structural OF n_bit_comparator IS COMPONENT comp1 PORT (a, b, gt, eq, lt : IN BIT; a_gt_b, a_eq_b, a_lt_b : OUT BIT); END COMPONENT; FOR ALL : comp1 USE ENTITY WORK.bit_comparator (functional); CONSTANT n : INTEGER := a'LENGTH; SIGNAL im : BIT_VECTOR ( 0 TO (n-1)*3-1);BEGIN c_all: FOR i IN 0 TO n-1 GENERATE l: IF i = 0 GENERATE least: comp1 PORT MAP (a(i), b(i), gt, eq, lt, im(0), im(1), im(2) ); END GENERATE; m: IF i = n-1 GENERATE most: comp1 PORT MAP (a(i), b(i), im(i*3-3), im(i*3-2), im(i*3-1), a_gt_b, a_eq_b, a_lt_b); END GENERATE; r: IF i > 0 AND i < n-1 GENERATE rest: comp1 PORT MAP (a(i), b(i), im(i*3-3), im(i*3-2), im(i*3-1), im(i*3+0), im(i*3+1), im(i*3+2) ); END GENERATE; END GENERATE;END structural;

• Keeping our promise of a better n-bit comparator• An n-bit comparator• Wiring n number of one-bit comparators• The integer n depends on the size of a



ENTITY n_bit_comparator_test_bench ISEND n_bit_comparator_test_bench ;--USE WORK.basic_utilities.ALL;-- FROM PACKAGE USE: apply_data which uses integer_vectorARCHITECTURE procedural OF n_bit_comparator_test_bench IS COMPONENT comp_n PORT (a, b : IN bit_vector; gt, eq, lt : IN BIT; a_gt_b, a_eq_b, a_lt_b : OUT BIT); END COMPONENT; FOR a1 : comp_n USE ENTITYWORK.n_bit_comparator(structural); SIGNAL a, b : BIT_VECTOR (5 DOWNTO 0); SIGNAL eql, lss, gtr : BIT; SIGNAL vdd : BIT := '1'; SIGNAL gnd : BIT := '0';BEGIN a1: comp_n PORT MAP (a, b, gnd, vdd, gnd, gtr, eql, lss); apply_data (a, 00&15&57&17, 500 NS); apply_data (b, 00&43&14&45&11&21&44&11, 500 NS);END procedural;

• Using generic apply_data procedure for testingn_bit_comparator

• All unconstrained arrays are fixed according to theparameters passed to them

• Can use different size integer vectors



First, the file has to be declared as what goes into a file

TYPE logic_data IS FILE OF CHARACTER;

Then a logical file name must be declared

FILE input_logic_value_file1: logic_data;--Just declare a logical file

FILE input_logic_value_file2: logic_data IS “input.dat”;--Declare a logical file and open in READ_MODE

FILE input_logic_value_file3: logic_data OPEN READ_MODEIS “input.dat”;

--Declare a logical file and open with the specified mode

• input_logic_value_file: logical name for file of logic_datatype

• An explicit OPEN statement must be used for opening• Can open a file in READ_MODE, WRITE_MODE or

APPEND_MODE

Primitive utilities for filedeclaration and filespecification



First, the file has to be declared as what goes into a file

TYPE logic_data IS FILE OF CHARACTER;

Then a logical file name must be declared

FILE output_logic_value_file1: logic_data;--Just declare a logical file, open later

FILE output_logic_value_file2:logic_data OPEN WRITE_MODE IS “input.dat”;

--Declare a logical file and open with the specified mode

OUPUT FILE : WRITE_MODE or APPEND MODE

• An explicit OPEN statement must be used for opening thefile in the first alternative

• Can open a file in READ_MODE, WRITE_MODE orAPPEND_MODE



An explicit OPEN is needed if file is not implicitly opened

FILE_OPEN (input_logic_value_file, “input.dat”, READ_MODE);

FILE_OPEN (output_logic_value_file, “output.dat”, WRITE_MODE);

FILE_OPEN (parameter_of_type_FILE_OPEN_STATUS,

output_logic_value_file, “output.dat”, WRITE_MODE);

The standard package includes:

TYPE FILE_OPEN_STATUS IS(OPEN_OK, STATUS_ERROR, NAME_ERROR, MODE_ERROR)

Closing a file:

FILE_CLOSE (input_logic_value_file);FILE_CLOSE (output_logic_value_file);

• File open alternatives• Status parameter must be declared first• Close a file using its logical name

PROCEDURE assign_bits ( SIGNAL s : OUT BIT; file_name : IN STRING; period : IN TIME) IS VARIABLE char : CHARACTER; VARIABLE current : TIME := 0 NS; FILE input_value_file : logic_data;BEGIN FILE_OPEN (input_value_file, file_name, READ_MODE); WHILE NOT ENDFILE (input_value_file) LOOP READ (input_value_file, char); IF char = '0' OR char = '1' THEN current := current + period; IF char = '0' THEN s <= TRANSPORT '0' AFTER current; ELSIF char = '1' THEN s <= TRANSPORT '1' AFTER current; END IF; END IF; END LOOP;END assign_bits;

Calling this procedure:

assign_bits (a_signal, "unix_file.bit", 1500 NS);

• file_name is a string input containing physical file name• A procedure for reading characters from a file and

assigning them to a BIT type• File type is declared in the procedure• En explicit open statement is used



Declare in an architecture:

FILE input_value_file: logic_data IS “my_file.bit”;

Call the pocedure:

read_from_file (SIGNAL target : OUT BIT, this_file : IN FILE);

• In the previous example, when assign_bits is called, itreads the entire unix_file.bit

• Each time reading begins from the top of the file, becausea new file object is declared each time it is called

• To avoid, declare a file object outside of the procedure

VHDL OPERATORS

Logical Operators:

AND, OR, NAND, NOR, XOR, XNOR, NOT

Examples of use:

x <= a XNOR b;

x_vector <= a_vector AND b_vector;

x <= “XOR” (a, b);

x_vector <= “AND” (a_vector, b_vector);

• Logical operators• Order of operand must remain the same• The second format makes operands appear as functions

Outlining VHDL operatorsand their format of use

VHDL OPERATORS

Relational operators:

=, /=, <, <=, >, >=

Examples of use:

a_boolean <= i1 > i2;

b_boolean <= i1 /= i2;

--if a_bit_vector is “00011” and b_bit_vector is “00100”

a_bit_vector < b_bit_vector returns TRUE

--for qitt: ‘0’ is less than ‘1’, and ‘X’ is larger all the rest

--for BIT: ‘1’ is greater than ‘0’

• = and /= operate on operands of any type• (<, <=, >, and >=) when used with array operands

perform ordering operations• These return TRUE or FALSE based on values of array

elements starting from the left


VHDL OPERATORS

• Shift operators• operand SIFT_OPERATOR number_of_shifts• fill value is the left-most enumeration element

Shift/Rotate Left/Right Logical/ArithmeticSLL Shift Left LogicalSLA Shift Left ArithmeticSRL Shift Right LogicalSRA Shift Right ArithmeticROL Rotate Left LogicalROR Rotate Right Logical

VHDL operators areformally presented in thenext few slides


VHDL OPERATORS

• Application of shift operators• The result must be placed in a LHS• Left operand remains unchanged

Start with aq Z 0 1 X Z 1 0 X

aq SLL 1 0 1 X Z 1 0 X 0

aq SLA 1 0 1 X Z 1 0 X X

aq SRL 1 0 Z 0 1 X Z 1 0

aq SRA 1 Z Z 0 1 X Z 1 0

aq ROL 1 0 1 X Z 1 0 X Z

aq ROR 1 X Z 0 1 X Z 1 0


VHDL OPERATORS

Adding operators:

+, -, &

Multiplying operators:

*, /, MOD, REM

Other operators:

(), **, ABS

Examples of use:

a + b

“+” (a, b)

a_int MOD b_int -- both integers

a_int REM b_int -- returns remainder of absolute value division

(a, b, c) – aggregate, like concatenation, but allows only elements

• Adding, multiplying, aggregate and other operators• Format of use is shown for each operator


SUBPROGRAM PARAMETER TYPES ANDOVERLOADING

• Want to use AND, OR, and NOT for qit as easily as forBIT

• Tables for the basic logic functions in the qit four valuelogic system

0 1 a: Z X

z = a.b

0

1

X

Z

b: 0

0

0

1

1

X

0

1

1

X

0

X

X

0 X

0

0 1 a: Z X

z = a + b

0

1

X

Z

b: 0

1

1

1

1

1

1

1

1

1

X

1

X

1 1

X

(a)

(b)

0

1

X

Z

a: 1

0

0

X

z = a'

(c)

Demonstrating overloadingVHDL operators andsubprograms



TYPE qit IS ('0', '1', 'Z', 'X');

TYPE qit_2d IS ARRAY (qit, qit) OF qit;

TYPE qit_1d IS ARRAY (qit) OF qit;

--

FUNCTION "AND" (a, b : qit) RETURN qit;

FUNCTION "OR" (a, b : qit) RETURN qit;

FUNCTION "NOT" (a : qit) RETURN qit;

• In a package declare qit and arrays based on this type• Declare functions to be overloaded• Overloading: identify a function with its operands and

name



FUNCTION "AND" (a, b : qit) RETURN qit IS CONSTANT qit_and_table : qit_2d := ( ('0','0','0','0'), ('0','1','1','X'), ('0','1','1','X'), ('0','X','X','X')); BEGIN RETURN qit_and_table (a, b); END "AND";

FUNCTION "OR" (a, b : qit) RETURN qit IS CONSTANT qit_or_table : qit_2d := ( ('0','1','1','X'), ('1','1','1','1'), ('1','1','1','1'), ('X','1','1','X')); BEGIN RETURN qit_or_table (a, b); END "OR";

FUNCTION "NOT" (a : qit) RETURN qit IS CONSTANT qit_not_table : qit_1d := ('1','0','0','X'); BEGIN RETURN qit_not_table (a); END "NOT";

• Overloading basic logical functions for the qit four valuelogic system

• Definition of functions

USE WORK.basic_utilities.ALL;-- FROM PACKAGE USE: qit, "NOT"ENTITY inv_q IS GENERIC (tplh : TIME := 5 NS; tphl : TIME := 3 NS); PORT (i1 : IN qit; o1 : OUT qit);END inv_q;--ARCHITECTURE average_delay OF inv_q ISBEGIN o1 <= NOT i1 AFTER (tplh + tphl) / 2;END average_delay;

USE WORK.basic_utilities.ALL;-- FROM PACKAGE USE: qit, "AND"ENTITY nand2_q IS GENERIC (tplh : TIME := 6 NS; tphl : TIME := 4 NS); PORT (i1, i2 : IN qit; o1 : OUT qit);END nand2_q;--ARCHITECTURE average_delay OF nand2_q ISBEGIN o1 <= NOT ( i1 AND i2 ) AFTER (tplh + tphl) / 2;END average_delay;

• Using overloaded operators• Cannot use NAND since it is only defined for BIT

USE WORK.basic_utilities.ALL;-- FROM PACKAGE USE: qit, "AND"ENTITY nand3_q IS GENERIC (tplh : TIME := 7 NS; tphl : TIME := 5 NS); PORT (i1, i2, i3 : IN qit; o1 : OUT qit);END nand3_q;--ARCHITECTURE average_delay OF nand3_q ISBEGIN o1 <= NOT ( i1 AND i2 AND i3) AFTER (tplh + tphl) / 2;END average_delay;

• Basic gates in the qit logic value system using overloadedAND operators

• Can also overload NAND and other operators• Std_logic has done this for its types



In the declaration:

FUNCTION "*" (a : resistance; b : capacitance) RETURN TIME;

In a package body:

FUNCTION "*" (a : resistance; b : capacitance) RETURN TIME IS BEGIN RETURN ( ( a / 1 l_o) * ( b / 1 ffr ) * 1 FS ) / 1000; END "*";

• Overloading the multiplication operator• Returns TIME when multiplying resistance and

capacitance physical types• Function declaration, the "*" subprogram body

USE WORK.basic_utilities.ALL;-- FROM PACKAGE USE: qit, capacitance, resistance, "*"ENTITY inv_rc IS GENERIC (c_load : capacitance := 66 ffr); PORT (i1 : IN qit; o1 : OUT qit); CONSTANT rpu : resistance := 25 k_o; CONSTANT rpd : resistance := 15 k_o;END inv_rc;

--

ARCHITECTURE double_delay OF inv_rc IS CONSTANT tplh : TIME := rpu * c_load * 3; CONSTANT tphl : TIME := rpd * c_load * 3;BEGIN o1 <= '1' AFTER tplh WHEN i1 = '0' ELSE '0' AFTER tphl WHEN i1 = '1' OR i1 = 'Z' ELSE 'X' AFTER tplh;END double_delay;

• Using the overloaded multiplication operator• The double_delay architecture of inv_rc

TYPE qit IS ('0', '1', 'Z', 'X');TYPE logic_data IS FILE OF CHARACTER;

PROCEDURE assign_bits ( SIGNAL s : OUT qit; file_name : IN STRING; period : IN TIME);

PROCEDURE assign_bits ( SIGNAL s : OUT qit; file_name : IN STRING; period : IN TIME) IS VARIABLE char : CHARACTER; VARIABLE current : TIME := 0 NS; FILE input_value_file : logic_data; BEGIN FILE_OPEN (input_value_file, file_name, READ_MODE); WHILE NOT ENDFILE (input_value_file) LOOP READ (input_value_file, char); current := current + period; CASE char IS WHEN '0' => s <= TRANSPORT '0' AFTER current; WHEN '1' => s <= TRANSPORT '1' AFTER current; WHEN 'Z' | 'z' => s <= TRANSPORT 'Z' AFTER current; WHEN 'X' | 'x' => s <= TRANSPORT 'X' AFTER current; WHEN OTHERS => current := current - period; END CASE; END LOOP; END assign_bits;

• Overloading the assign_bits procedure for accepting andproducing qit data

• Procedure and other necessary declarations• Subprogram body uses a case statement

• Syntax details of a sequential case statement• Consists of several case alternatives• All choices must be filled

WHEN ‘1’ =>

TRANSPORT ‘0’

=>

char

WHEN

TRANSPORT ‘1’

IS

CASE

‘0’

target <=

AFTER current;

target <=

AFTER current; WHEN

=>

TRANSPORT ‘Z’

‘Z’ ‘z’

target <=

AFTER current;

WHEN ‘X’ ‘x’ =>

TRANSPORT ‘X’

WHEN

target <=

AFTER current;

OTHERS =>

current – period; current :=

END CASE;

expression

sequence_ofstatements

choice


choices



choice


case_statementalternative



USE WORK.basic_utilities.ALL;-- FROM PACKAGE: qit, capacitance, resistance, assign_bitsENTITY tester ISEND tester;--ARCHITECTURE input_output OF tester IS COMPONENT inv GENERIC (c_load : capacitance := 11 ffr); PORT (i1 : IN qit; o1 : OUT qit); END COMPONENT; FOR ALL : inv USE ENTITY WORK.inv_rc(double_delay); SIGNAL a, z : qit;BEGIN assign_bits (a, "data.qit", 500 NS); i1 : inv PORT MAP (a, z);END input_output;

• Calling the overloaded assign_bits for testing an inverter• The inverter with RC delay is being tested• Type qit operand of the procedure causes the new

assign_bits to be called


OTHER TYPES AND RELATED ISSUES

SUBTYPE compatible_nibble_bits IS BIT_VECTOR ( 3 DOWNTO 0);

TYPE nibble_bits IS ARRAY ( 3 DOWNTO 0 ) OF BIT;

SUBTYPE ten_value_logic IS INTEGER RANGE 0 TO 9;

SUBTYPE rit IS qit RANGE '0' TO 'Z';

SUBTYPE bin IS qit RANGE '0' TO '1';

• Subtypes are used for compatibility• Base type of a subtype is the original type• nibble_bits is not compatible with any BIT_VECTOR• rit and bin are fully compatible with qit

Other type related issues,subtypes, records, andaliases are discussed

TYPE opcode IS (sta, lda, add, sub, and, nop, jmp, jsr);TYPE mode IS RANGE 0 TO 3;TYPE address IS BIT_VECTOR (10 DOWNTO 0);

TYPE instruction_format IS RECORD opc : opcode; mde : mode; adr : address;END RECORD;

SIGNAL instr : instruction_format := (nop, 0, "00000000000");

instr.opc <= lda;instr.mde <= 2;instr.adr <= "00011110000";

instr <= (adr => (OTHERS => ‘1’), mde => 2, opc => sub)

• Record Type• Three fields of an instruction• Declaration of instruction format• A signal of record type• Referencing fields of a record type signal• Record aggregate

15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00

opcode mode address

Instruction format

ALIAS page :BIT_VECTOR (2 DOWNTO 0) IS instr.adr (10 DOWNTO 8);

ALIAS offset :BIT_VECTOR (7 DOWNTO 0) IS instr.adr (7 DOWNTO 0);

page <= "001";offset <= X"F1";

• Alias declaration, page and offset addresses• Alias declaration for the page and offset parts of the

address• Assignments to page and offset parts of address

15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00

opcode mode page offset

address



TYPE node; TYPE pointer IS ACCESS node; TYPE node IS RECORD data : INTEGER; link : pointer; END RECORD;

• Linked list graphical representation• Definition in VHDL starts with an incomplete type

definition

link

head

data linkInteger Type Pointer Type

data link

node

data link

node

data NULL

node

ACCESS type andimplementation and usage oflinked lists is demonstrated



Declaration of head as the head of a linked list to be created:

VARIABLE head : pointer := NULL;

Assigning the first node to head.

head := NEW node;

Linking the next node:

head.link := NEW node;

• Using the above linked list• Declaring head and linking to it



PROCEDURE lineup (VARIABLE head : INOUT pointer; int :integer_vector) IS

VARIABLE t1 : pointer; BEGIN -- Insert data in the linked list head := NEW node; t1 := head; FOR i IN int'RANGE LOOP t1.data := int(i); IF i = int'RIGHT THEN t1.link := NULL; ELSE t1.link := NEW node; t1 := t1.link; END IF; END LOOP; END lineup;

Declare mem: VARIABLE mem, cache : pointer := NULL;

Inserting integers into the mem linked list: lineup (mem, (25, 12, 17, 18, 19, 20));

• Creating a linked list and entering data into it• Head is returned as the first node of the linked list• A new node of type node is obtained and assigned to head• Fields of node are accessed and data is entered into them



PROCEDURE remove (VARIABLE head : INOUT pointer; v : IN INTEGER) IS

VARIABLE t1, t2 : pointer; BEGIN -- Remove node following that with value v t1 := head; WHILE t1 /= NULL LOOP IF t1.data = v THEN t2 := t1.link; t1.link := t2.link; DEALLOCATE (t2); END IF; t1 := t1.link; END LOOP; END remove;

• Removing an item from a linked list• The head of the linked list is passed• Node that follows node with value v is removed



PROCEDURE clear (VARIABLE head : INOUT pointer) IS VARIABLE t1, t2 : pointer;BEGIN -- Free all the linked list t1 := head; head := NULL; WHILE t1 /= NULL LOOP t2 := t1; t1 := t1.link; DEALLOCATE (t2); END LOOP; END clear;END ll_utilities;

• Freeing a linked list• Start with he head of a linked list and clear it• All nodes must be deallocated

PACKAGE ll_utilities IS TYPE node; TYPE pointer IS ACCESS node; TYPE node IS RECORD data : INTEGER; link : pointer; END RECORD; TYPE integer_vector IS ARRAY (INTEGER RANGE <>) OF INTEGER; PROCEDURE lineup (VARIABLE head : INOUT pointer; int : integer_vector); PROCEDURE remove (VARIABLE head : INOUT pointer; v : IN INTEGER); PROCEDURE clear (VARIABLE head : INOUT pointer);END ll_utilities;--PACKAGE BODY ll_utilities IS PROCEDURE lineup (VARIABLE head : INOUT pointer; int : integer_vector) IS VARIABLE t1 : pointer; BEGIN -- Insert data in the linked list head := NEW node; t1 := head; FOR i IN int'RANGE LOOP t1.data := int(i); IF i = int'RIGHT THEN t1.link := NULL; ELSE t1.link := NEW node; t1 := t1.link; END IF; END LOOP; END lineup; -- PROCEDURE remove (VARIABLE head : INOUT pointer; v : IN INTEGER) IS VARIABLE t1, t2 : pointer; BEGIN -- Remove node following that with value v t1 := head; WHILE t1 /= NULL LOOP IF t1.data = v THEN t2 := t1.link; t1.link := t2.link; DEALLOCATE (t2); END IF; t1 := t1.link; END LOOP; END remove; -- PROCEDURE clear (VARIABLE head : INOUT pointer) IS VARIABLE t1, t2 : pointer; BEGIN -- Free all the linked list t1 := head; head := NULL; WHILE t1 /= NULL LOOP t2 := t1; t1 := t1.link; DEALLOCATE (t2); END LOOP; END clear;END ll_utilities;

• Linked list utilities

SHARED VARIABLE dangerous : INTEGER := 0;

In the assignment:

(sq4(0), sq4(1), sq4(2), sq4(3)) <= (OTHER => ‘X’);

‘X’ can be interpreted as character ‘X’, requires a qualifier:

(sq4(0), sq4(1), sq4(2), sq4(3)) <= qit_nibble’ (OTHERS => ‘X’);

Now ‘X’s are qualified for size and element type

Explicit type conversions for closely related types, e.g., INTEGER and REAL

TYPE qit_byte IS ARRAY (7 DOWNTO 0) of qit;

TYPE qit_octal IS ARRAY (7 DOWNTO 0) of qit;

. . .

SIGNAL qb : qit_byte;

SIGNAL qo : qit_octal;

qb <= qo; -- CANNOT DO

qb <= qit_byte (qo); -- Must do explicit type conversion

• Share variables• Using qualifiers• Explicit type conversion between closely related types



LIBRARY IEEE;

USE IEEE.std_logic_1164.ALL;

std_logic is an enumeration type with nine logic values

‘U’ is the default initial value

std_logic_vector is an unconstraned array of std_logic

All logical and shift operators are overloaded for std_logic andstd_logic_vector

Conversion functions for all subtypes and the BIT type to and fromstd_logic

• Provides types for most applications• Overloading is done for all operators• Includes conversion functions where needed

std_logic, its overloadingand its subtypes is a goodexample of the above topics



• std_logic subtypes• Enumeration elements are arranged for such subtypes• Our qit is like UX01 or X01Z, different initial values

TYPEX01 ‘X’, ‘0’, ‘1’X01Z ‘X’, ‘0’, ‘1’, ‘Z’UX01 ‘U’, ‘X’, ‘0’, ‘1’UX01Z ‘U’, ‘X’, ‘0’, ‘1’, ‘Z’


PREDEFINED ATTRIBUTES

Attribute Description Example Result

‘LEFT Left bound sq_4_8’LEFT(1) 3

‘RIGHT Right bound sq_4_8’RIGHTsq_4_8’RIGHT(2)

07

‘HIGH Upper bound sq_4_8’HIGH(2) 7

‘LOW Lower bound sq_4_8’LOW(2) 0

‘RANGE Range sq_4_8’RANGE(2)sq_4_8’RANGE(1)

0 TO 73 DOWNTO 0

‘REVERSE_RANGE Reverse range sq_4_8’REVERSE_RANGE(2)sq_4_8’REVERSE_RANGE(1)

7 DOWNTO 00 TO 3

‘LENGTH Length sq_4_8’LENGTH 4

‘ASCENDING TRUEIf Ascending

sq_4_8’ASCENDING(2)sq_4_8’ASCENDING(1)

TRUEFALSE

• Predefined Array Attributes• Type of sq_4_8 is qit_4by8

Predefined attributes aredemonstrated here. Array,Type, Signal, and Entity




‘BASE Base of type rit’BASE qit

‘LEFT Left bound of typeor subtype

rit’LEFTqit’LEFT

‘0’‘0’

‘RIGHT Right bound of typeor subtype

rit’RIGHTqit’RIGHT

‘Z’‘X’

‘HIGH Upper bound of typeor subtype

INTEGER’HIGHrit’HIGH

Large‘Z’

‘LOW Lower bound of typeor subtype

POSITIVE’LOWqit’LOW

1‘0’

‘POS(V) Position of value Vin base of type.

qit’POS(‘Z’)rit’POS(‘X’)

23

‘VAL(P) Value at Position Pin base of type.

qit’VAL(3)rit’VAL(3)

‘X’‘X’

‘SUCC(V) Value, after valueV in base of type.

rit’SUCC(‘Z’) ‘X’

‘PRED(V) Value, before valueV in base of type.

rit’PRED(‘1’) ‘0’

. . . . . . . . . . . .

• Predefined type attributes• The type of qit and rit are enumeration types• More follows . . .




. . . . . . . . . . . .

‘LEFTOF(V) Value, left of valueV in base of type.

rit’LEFTOF(‘1’)rit’LEFTOF(‘0’)

‘0’Error

‘RIGHTOF(V) Value, right of valueV in base of type.

rit’RIGHTOF(‘1’)rit’RIGHTOF(‘Z’)

‘Z’‘X’

‘ASCENDING TRUE if range is ascending qit’ASCENDINGqqit’ASCENDING

TRUETRUE

‘IMAGE (V) Converts valueV of type to string.

qit’IMAGE(‘Z’)qqit’IMAGE(qZ)

“’Z’”“qZ”

‘VALUE(S) Converts stringS to value of type.

qqit’VALUE(“qZ”) qZ

• Predefined type attributes• The type of qit and rit are enumeration types• Note type versus base of type



Attribute T/E Example Kind Type

Attribute description for the specified example

‘DELAYED - s1’DELAYED (5 NS) SIGNAL As s1

A copy of s1, but delayed by 5 NS. If no parameter or 0, delayed by delta. Equivalentto TRANSPORT delay of s1.

‘STABLE EV s1’STABLE (5 NS) SIGNAL BOOLEAN

A signal that is TRUE if s1 has not changed in the last 5 NS. If no parameter or 0, theresulting signal is TRUE if s1 has not changed in the current simulation time.

‘EVENT EV s1’EVENT VALUE BOOLEAN

In a simulation cycle, if s1 changes, this attribute becomes TRUE.

‘LAST_EVENT EV s1’LAST_VALUE VALUE TIME

The amount of time since the last value change on s1. If s1’EVENT is TRUE, thevalue of s1’LAST_VALUE is 0.

‘LAST_VALUE EV s1’LAST_VALUE VALUE As s1

The value of s1 before the most recent event occurred on this signal.

. . .

• Predefined signal attributes• Signal s is assumed to be of type BIT• More follows . . .



Attribute T/E Example Kind Type

. . .

‘QUIET TR s1’QUIET (5 NS) SIGNAL BOOLEAN

A signal that ir TRUE if no transaction has been placed on s1 in the last 5 NS. If noparameter or 0, the current simulation cycle is assumed.

‘ACTIVE TR s1’ACTIVE VALUE BOOLEAN

If s1 has had a transaction in the current simulation cycle, s1’ACTIVE will be TRUEfor this simulation cycle, for delta time.

‘LAST_ACTIVE TR s1’LAST_ACTIVE VALUE TIME

The amount of time since the last transaction occurred on s1. If s1’ACTIVE is TRUE,s1’LAST_ACTIVE is 0.

‘TRANSACTION TR s1’TRANACTION SIGNAL BIT

A signal that toggles each time a transaction occurs on s1. Initial value of thisattribute is not defined.

‘DRIVING - s1’DRIVING VALUE BOOLEAN

If s1is being driven in a process, s1’DRIVING is TRUE in the same process.

‘DRIVING_VALUE - s1’DRIVING_VALUE VALUE As s1

The driving value of s1 from within the process this attribute is being applied.

• Predefined signal attributes• Signal s is assumed to be of type BIT



• Results of signal attributes when applied to the BIT typesignal, s1

• Blocks show Boolean results

TIME (NS)

s1

s1'DELAYED (5NS)

s1'STABLE

s1'EVENT

s1'LAST_EVENT

s1'LAST_VALUE

s1'QUIET (5NS)

s1'ACTIVE

s1'LAST_ACTIVE

s1'TRANSACTION

15 30 45 60

10 15 20 25 0 5 10 0 5 10 15

10 0 5 10 0 5 10 0 5 10 0

ENTITY brief_d_flip_flop IS PORT (d, c : IN BIT; q : OUT BIT);END brief_d_flip_flop;--ARCHITECTURE falling_edge OF brief_d_flip_flop IS SIGNAL tmp : BIT;BEGIN tmp <= d WHEN (c = '0' AND NOT c'STABLE) ELSE tmp; q <= tmp AFTER 8 NS;END falling_edge;

• A simple falling edge Flip-Flop using signal attributes• Two events occur when c changes• Cannot delay the first statement

ENTITY brief_t_flip_flop IS PORT (t : IN BIT; q : OUT BIT);END brief_t_flip_flop;--ARCHITECTURE toggle OF brief_t_flip_flop IS SIGNAL tmp : BIT;BEGIN tmp <= NOT tmp WHEN ( (t = '0' AND NOT t'STABLE) AND (t'DELAYED'STABLE(20 NS)) ) ELSE tmp; q <= tmp AFTER 8 NS;END toggle;

• A simple toggle Flip-Flop using signal attributes• Combining several signal attributes• Can only apply if result of an attribute is signal



Entity Attributes generate a string corresponding to the name of an entity class

“entity_class”entities, architectures, configurations, procedures, functions, packages, types,subtypes, constants, signals, variables, components, labels, literals, units,groups, and files

‘SIMPLE_NAME:

Generates simple name of a named entity

‘PATH_NAME :

Generates a string containing entity names and labels from the top of

hierarchy leading to the named entity.

‘INSTANCE_NAME:

Generates a name that contains entity, architecture, and instantiation labels

leading to the design entity.

• Entity attributes• Generate a string for the name for an entity class

ENTITY nand2 IS PORT (i1, i2 : IN BIT; o1 : OUT BIT);END ENTITY;--ARCHITECTURE single_delay OF nand2 IS

SIGNAL simple : STRING (1 TO nand2'SIMPLE_NAME'LENGTH):= (OTHERS => '.');

SIGNAL path : STRING (1 TO nand2'PATH_NAME'LENGTH):= (OTHERS => '.');

SIGNAL instance : STRING (1 TO and2'INSTANCE_NAME'LENGTH):= (OTHERS => '.');

BEGIN o1 <= i1 NAND i2 AFTER 3 NS; simple <= nand2'SIMPLE_NAME; instance <= nand2'INSTANCE_NAME; path <= nand2'PATH_NAME;END single_delay;--ENTITY xoring IS PORT (i1, i2 : IN BIT; o1 : OUT BIT);END ENTITY;--ARCHITECTURE gate_level OF xoring IS SIGNAL a, b, c : BIT;BEGIN u1 : ENTITY WORK.nand2 PORT MAP (i1, i2, a); u2 : ENTITY WORK.nand2 PORT MAP (i1, a, b); u3 : ENTITY WORK.nand2 PORT MAP (a, i2, c); u4 : ENTITY WORK.nand2 PORT MAP (b, c, o1);END gate_level;

• Examples for entity attributes• Simple, path, and instance attributes



• Simple, path, and instance strings• Results from simulation of the above nand2

Simple: nand2

Path: :xoring:u1:

Instance: “xoring(gate_level):u1@nand2(single_delay):


USER-DEFINED ATTRIBUTES

User-defined attributes may be applied to the elements of an entity class

Must declare first:

ATTRIBUTE sub_dir : STRING;

Then attribute specification:

ATTRIBUTE sub_dir OF brief_d_flip_flop : ENTITY IS “/user/vhdl”;

brief_d_flip_flop’sub_dir evaluates to “/user/vhdl”.

• User defined attributes• No simulation semantics

User-defined attributes aredemonstrated here.

USER-DEFINED ATTRIBUTES

PACKAGE utility_attributes IS TYPE timing IS RECORD rise, fall : TIME; END RECORD; ATTRIBUTE delay : timing; ATTRIBUTE sub_dir : STRING;END utility_attributes;--USE WORK.utility_attributes.ALL;-- FROM PACKAGE USE: delay, sub_dirENTITY brief_d_flip_flop IS PORT (d, c : IN BIT; q : OUT BIT); ATTRIBUTE sub_dir OF brief_d_flip_flop : ENTITY IS "/user/vhdl"; ATTRIBUTE delay OF q : SIGNAL IS (8 NS, 10 NS);END brief_d_flip_flop;--ARCHITECTURE attributed_falling_edge OF brief_d_flip_flop IS SIGNAL tmp : BIT;BEGIN tmp <= d WHEN ( c= '0' AND NOT c'STABLE ) ELSE tmp; q <= '1' AFTER q'delay.rise WHEN tmp = '1' ELSE '0' AFTER q'delay.fall;END attributed_falling_edge;

• Associating attributes to entities and signals• A package declares attributes• An entity defines• An architecture uses attributes

PACKAGING BASIC UTILITIES

PACKAGE basic_utilities IS

. . .

TYPE qit_vector IS ARRAY (NATURAL RANGE <>) OF qit;

SUBTYPE rit IS qit RANGE '0' TO 'Z';

TYPE rit_vector IS ARRAY (NATURAL RANGE <>) OF rit;

TYPE integer_vector IS ARRAY (NATURAL RANGE <>) OF INTEGER;

TYPE natural_vector IS ARRAY (NATURAL RANGE <>) OF NATURAL;

. . .

FUNCTION to_integer (bin : BIT_VECTOR) RETURN INTEGER;

FUNCTION to_integer (qin : qit_vector) RETURN INTEGER;

FUNCTION to_bitvector (qin : qit_vector) RETURN bit_vector;

. . .

FUNCTION "+" (a : qit_vector; b : qit_vector) RETURN qit_vector;

FUNCTION "+" (a : qit_vector; b : INTEGER) RETURN qit_vector;

FUNCTION "-" (a : qit_vector; b : qit_vector) RETURN qit_vector;

FUNCTION "-" (a : qit_vector; b : INTEGER) RETURN qit_vector;

. . .

END basic_utilities;

• Adding what was done to our basic utilities package• Will use this package for homeworks and in other

chapters

PACKAGE basic_utilities IS TYPE qit IS ('0', '1', 'Z', 'X'); TYPE qit_2d IS ARRAY (qit, qit) OF qit; TYPE qit_1d IS ARRAY (qit) OF qit; TYPE qit_vector IS ARRAY (NATURAL RANGE <>) OF qit; SUBTYPE rit IS qit RANGE '0' TO 'Z'; TYPE rit_vector IS ARRAY (NATURAL RANGE <>) OF rit; TYPE integer_vector IS ARRAY (NATURAL RANGE <>) OF INTEGER; TYPE logic_data IS FILE OF CHARACTER; TYPE capacitance IS RANGE 0 TO 1E16 UNITS ffr; -- Femto Farads (base unit) pfr = 1000 ffr; nfr = 1000 pfr; ufr = 1000 nfr; mfr = 1000 ufr; far = 1000 mfr; kfr = 1000 far; END UNITS; TYPE resistance IS RANGE 0 TO 1E16 UNITS l_o; -- Milli-Ohms (base unit) ohms = 1000 l_o; k_o = 1000 ohms; m_o = 1000 k_o; g_o = 1000 m_o; END UNITS; FUNCTION fgl (w, x, gl : BIT) RETURN BIT; FUNCTION feq (w, x, eq : BIT) RETURN BIT; FUNCTION to_integer (bin : BIT_VECTOR) RETURN INTEGER; PROCEDURE bin2int (bin : IN BIT_VECTOR; int : OUT INTEGER); PROCEDURE int2bin (int : IN INTEGER; bin : OUT BIT_VECTOR); PROCEDURE apply_data ( SIGNAL target : OUT BIT_VECTOR; CONSTANT values : IN integer_vector; CONSTANT period : IN TIME); PROCEDURE assign_bits ( SIGNAL s : OUT BIT; file_name : IN STRING; period : IN TIME); PROCEDURE assign_bits ( SIGNAL s : OUT qit; file_name : IN STRING; period : IN TIME); FUNCTION "AND" (a, b : qit) RETURN qit; FUNCTION "OR" (a, b : qit) RETURN qit; FUNCTION "NOT" (a : qit) RETURN qit; FUNCTION "*" (a : resistance; b : capacitance) RETURN TIME; END basic_utilities;

• Complete package declaration



PACKAGE BODY basic_utilities IS FUNCTION "AND" (a, b : qit) RETURN qit IS CONSTANT qit_and_table : qit_2d := ( ('0','0','0','0'), ('0','1','1','X'), ('0','1','1','X'), ('0','X','X','X')); BEGIN RETURN qit_and_table (a, b); END "AND"; FUNCTION "OR" (a, b : qit) RETURN qit IS CONSTANT qit_or_table : qit_2d := ( ('0','1','1','X'), ('1','1','1','1'), ('1','1','1','1'), ('X','1','1','X')); BEGIN RETURN qit_or_table (a, b); END "OR"; FUNCTION "NOT" (a : qit) RETURN qit IS CONSTANT qit_not_table : qit_1d := ('1','0','0','X'); BEGIN RETURN qit_not_table (a); END "NOT"; FUNCTION "*" (a : resistance; b : capacitance) RETURN TIME IS BEGIN RETURN ( ( a / 1 l_o) * ( b / 1 ffr ) * 1 FS ) / 1000; END "*"; FUNCTION fgl (w, x, gl : BIT) RETURN BIT IS BEGIN RETURN (w AND gl) OR (NOT x AND gl) OR (w AND NOT x); END fgl; FUNCTION feq (w, x, eq : BIT) RETURN BIT IS BEGIN RETURN (w AND x AND eq) OR (NOT w AND NOT x AND eq); END feq; FUNCTION to_integer (bin : BIT_VECTOR) IS VARIABLE result: INTEGER; BEGIN result := 0; FOR i IN bin'RANGE LOOP IF bin(i) = '1' THEN result := result + 2**i; END IF; END LOOP; RETURN result; END;

• Package body

PROCEDURE bin2int (bin : IN BIT_VECTOR; int : OUT INTEGER) IS VARIABLE result: INTEGER; BEGIN result := 0; FOR i IN bin'RANGE LOOP IF bin(i) = '1' THEN result := result + 2**i; END IF; END LOOP; int := result; END bin2int; PROCEDURE int2bin (int : IN INTEGER; bin : OUT BIT_VECTOR) IS VARIABLE tmp : INTEGER; BEGIN tmp := int; FOR i IN 0 TO (bin'LENGTH - 1) LOOP IF (tmp MOD 2 = 1) THEN bin (i) := '1'; ELSE bin (i) := '0'; END IF; tmp := tmp / 2; END LOOP; END int2bin; PROCEDURE apply_data ( SIGNAL target : OUT BIT_VECTOR; CONSTANT values : IN integer_vector; CONSTANT period : IN TIME) IS VARIABLE buf : BIT_VECTOR (target'RANGE); BEGIN FOR i IN values'RANGE LOOP int2bin (values(i), buf); target <= TRANSPORT buf AFTER i * period; END LOOP; END apply_data;®BB¯

• Package body

PROCEDURE assign_bits ( SIGNAL s : OUT BIT; file_name : IN STRING; period : IN TIME) IS VARIABLE char : CHARACTER; VARIABLE current : TIME := 0 NS; FILE input_value_file : logic_data; BEGIN FILE_OPEN (input_value_file, file_name, READ_MODE); WHILE NOT ENDFILE (input_value_file) LOOP READ (input_value_file, char); IF char = '0' OR char = '1' THEN current := current + period; IF char = '0' THEN s <= TRANSPORT '0' AFTER current; ELSIF char = '1' THEN s <= TRANSPORT '1' AFTER current; END IF; END IF; END LOOP; END assign_bits;PROCEDURE assign_bits ( SIGNAL s : OUT qit; file_name : IN STRING; period : IN TIME) IS VARIABLE char : CHARACTER; VARIABLE current : TIME := 0 NS; FILE input_value_file : logic_data; BEGIN FILE_OPEN (input_value_file, file_name, READ_MODE); WHILE NOT ENDFILE (input_value_file) LOOP READ (input_value_file, char); current := current + period; CASE char IS WHEN '0' => s <= TRANSPORT '0' AFTER current; WHEN '1' => s <= TRANSPORT '1' AFTER current; WHEN 'Z' | 'z' => s <= TRANSPORT 'Z' AFTER current; WHEN 'X' | 'x' => s <= TRANSPORT 'X' AFTER current; WHEN OTHERS => current := current - period; END CASE; END LOOP; END assign_bits;END basic_utilities;

• The basic_utilities package as will be used in the examplesin the chapters that follow


Summary

This chapter presented tools for high level descriptions.

Declaration of types and the usage of objects of various

types were covered in the first part of the chapter. In

the context of describing type-related issues, we

introduced the unconstrained array and file type. The

basic I/O presented in this chapter showed a simple way

to read or write from files. The overloading which is

related to types was discussed next. Predefined

attributes in VHDL can be looked upon as operators or

predefined functions. In modeling, hardware behavior

attributes are very useful, as we will see in the following,

chapters. Finally in this chapter, we presented the

basic_utilities package. Elements of this package are

useful for hardware modeling and the creation of the

package demonstrates the importance of packaging

capability in VHDL.



CHAPTER 8

DATAFLOW DESCRIPTIONS IN VHDL

8.1 MULTIPLEXING AND DATA SELECTION 8.1.1 General Multiplexing 8.1.2 Guarded Signal Assignments 8.1.3 Block Declarative Part 8.1.4 Nesting Guarded Blocks 8.1.5 Disconnecting From Driver 8.1.6 Resolving Between Several Driving Values 8.1.7 MOS Implementation of Multiplexer 8.1.8 A General Multiplexer 8.1.9 Resolving INOUT Signals

8.2 STATE MACHINE DESCRIPTION 8.2.1 A Sequence Detector 8.2.2 Allowing Multiple Active States 8.2.3 Outputs of Mealy and Moore Machines 8.2.4 A Generic State Machine

8.3 OPEN COLLECTOR GATES 8.4 THREE STATE BUSSING

8.4.1 Std_logic Bussing 8.5 A GENERAL DATAFLOW CIRCUIT 8.6 UPDATING BASIC UTILITIES 8.7 SUMMARY

• Constructs for dataflow descriptions • Multiplexing and clocking, selection constructs; guarded assignments • Multiple assignments; Resolutions: anding, oring, wiring • Guarded signals • State machines, simple sequence detector, multiple active states • Open collectors using resolution functions • A complete dataflow example


MULTIPLEXING AND DATA SELECTION

• Basic data selection hardware, logic diagram, symbols • Multiplexers are used for data selection

out

select1

select2

data1

data2

(a)

1D2D

S1S2

y

D1

D2

Y

S1 S2

Will use VHDL for modeling various selection logic implementations



• Flip flop clocking selects data • Various forms of data selection may be combined • Will show language constructs for such selections

1D

Q

enable

clk

data

C1



• Multiplexing and clock enabling.

1D2D

S1S2

Y 1D

Q

C1

data1data2

select1select2

enable

clk



• An eight-to-one multiplexer.

G0

G1

G2

G3

G4

G5

G6

G7

0

1

2

3

4

5

6

7

MUX

selectlines

datainputs

Z

MULTIPLEXING AND DATA SELECTION USE WORK.basic_utilities.ALL; -- FROM PACKAGE USE: qit, qit_vector ENTITY mux_8_to_1 IS PORT ( i7, i6, i5, i4, i3, i2, i1, i0 : IN qit; s7, s6, s5, s4, s3, s2, s1, s0 : IN qit; z : OUT qit ); END mux_8_to_1; -- ARCHITECTURE dataflow OF mux_8_to_1 IS BEGIN WITH qit_vector’(s7, s6, s5, s4, s3, s2, s1, s0) SELECT z <= '0' AFTER 3 NS WHEN "00000000", i7 AFTER 3 NS WHEN "10000000" | "Z0000000", i6 AFTER 3 NS WHEN "01000000" | "0Z000000", i5 AFTER 3 NS WHEN "00100000" | "00Z00000", i4 AFTER 3 NS WHEN "00010000" | "000Z0000", i3 AFTER 3 NS WHEN "00001000" | "0000Z000", i2 AFTER 3 NS WHEN "00000100" | "00000Z00", i1 AFTER 3 NS WHEN "00000010" | "000000Z0", i0 AFTER 3 NS WHEN "00000001" | "0000000Z", 'X' WHEN OTHERS; END dataflow;

• Description of a simple multiplexer • Selected signal assignment is used • Dataflow multiplexing • Selected waveforms use choice or choices



• Syntax details of a selected signal assignment.



• Decoder description uses selected signal assignment • A three-to-eight decoder.

DCDS0

S1

S2

S3

S4

S5

S6

S7

A0

A1

A2

Another form of selection is a decoder, which we will model in VHDL

MULTIPLEXING AND DATA SELECTION USE WORK.basic_utilities.ALL; -- FROM PACKAGE USE: qit_vector ENTITY dcd_3_to_8 IS PORT (adr : IN qit_vector (2 DOWNTO 0); so : OUT qit_vector (7 DOWNTO 0)); END dcd_3_to_8; -- ARCHITECTURE dataflow OF dcd_3_to_8 IS BEGIN WITH adr SELECT so <= "00000001" AFTER 2 NS WHEN "000", "00000010" AFTER 2 NS WHEN "00Z" | "001", "00000100" AFTER 2 NS WHEN "0Z0" | "010", "00001000" AFTER 2 NS WHEN "0ZZ" | "0Z1" | "01Z" | "011", "00010000" AFTER 2 NS WHEN "100" | "Z00", "00100000" AFTER 2 NS WHEN "Z0Z" | "Z01" | "10Z" | "101" , "01000000" AFTER 2 NS WHEN "ZZ0" | "Z10" | "1Z0" | "110", "10000000" AFTER 2 NS WHEN "ZZZ" | "ZZ1" | "Z1Z" | "Z11" | "1ZZ" | "1Z1" | "11Z" | "111", "XXXXXXXX" WHEN OTHERS; END dataflow;

• VHDL description for the three-to-eight decoder. • All possibilities must be considered

MULTIPLEXING AND DATA SELECTION ENTITY d_flipflop IS GENERIC (delay1 : TIME := 4 NS; delay2 : TIME := 5 NS); PORT (d, c : IN BIT; q, qb : OUT BIT); END d_flipflop; -- ARCHITECTURE assigning OF d_flipflop IS SIGNAL internal_state : BIT; BEGIN internal_state <= d WHEN (c ='1' AND NOT c'STABLE) ELSE internal_state; q <= internal_state AFTER delay1; qb <= NOT internal_state AFTER delay2; END assigning;

• A simple flip-flop uses internal_state • On clock edge d is transferred to internal_state • Events on internal_state cause assignments to q and qb

1D Q

C1

Q-

1D Q

C1

Q-

MULTIPLEXING AND DATA SELECTION target <= GUARDED waveforms__or__conditional_waveforms__or__selected_waveforms; ARCHITECTURE guarding OF d_flipflop IS BEGIN ff: BLOCK ( c = '1' AND NOT c'STABLE ) BEGIN q <= GUARDED d AFTER delay1; qb <= GUARDED NOT d AFTER delay2; END BLOCK ff; END guarding;

• The guarding architecture for the d_flipflop entity. • Better representation of clocking disconnects d from q • Disconnection is specified by GUARDED • GUARDED assignments are guarded by guard expression • Can also guard selected and conditional signal assignments

Several examples will demonstrate guarded blocks and assignments

• Syntax details of a guarded block statement with guarded signal assignments

• Label is mandatory • Use GUARDED for guard to apply

concurrent statement GUARDED

q

)

:

(

qb

GUARDED

END BLOCK ff;

block_label

BLOCK

ff

c = ‘1’ AND NOT c’STABLE

BEGIN

<=

d AFTER delay1;

<=

NOT d AFTER delay2;

concurrent statement

guard_expression

block statement part

block statement

Concurrent statem

ent

MULTIPLEXING AND DATA SELECTION ENTITY flipflop_test IS END flipflop_test; -- ARCHITECTURE input_output OF flipflop_test IS COMPONENT flop PORT (d, c : IN BIT; q, qb : OUT BIT); END COMPONENT; FOR c1 : flop USE ENTITY WORK.d_flipflop (assigning); FOR c2 : flop USE ENTITY WORK.d_flipflop (guarding); SIGNAL dd, cc, q1, q2, qb1, qb2 : BIT; BEGIN cc <= NOT cc AFTER 400 NS WHEN NOW < 2 US ELSE cc; dd <= NOT dd AFTER 1000 NS WHEN NOW < 2 US ELSE dd; c1: flop PORT MAP (dd, cc, q1, qb1); c2: flop PORT MAP (dd, cc, q2, qb2); END input_output;

• A test bench for testing assigning and guarding architectures of d_flipflop

• Testbench tests and verifies both descriptions • A simple method for generation of periodic signals



TIME (ns)

cc

dd

q1

q2

qb1

qb2

c1: state

c2:ff GUARD

0000 '0' '0' '0' '0' '0' '0' '0' FALSE +1δδ ... ... ... ... ... ... '0' .....

0004 ... ... '0' ... ... ... ... ..... 0005 ... ... ... ... '1' ... ... ..... 0400 '1' ... ... ... ... ... ... TRUE

+1δδ ... ... ... ... ... ... '0' FALSE +2δδ ... ... ... ... ... ... '0' .....

0404 ... ... ... '0' ... ... ... ..... 0405 ... ... ... ... ... '1' ... ..... 0800 '0' ... ... ... ... ... ... FALSE

+1δδ ... ... ... ... ... ... '0' FALSE +2δδ ... ... ... ... ... ... '0' .....

1000 ... '1' ... ... ... ... ... ..... +1δδ ... ... ... ... ... ... '0' .....

1200 '1' ... ... ... ... ... ... TRUE +1δδ ... ... ... ... ... ... '1' FALSE +2δδ ... ... ... ... ... ... '1' .....

1204 ... ... '1' '1' ... ... ... ..... 1205 ... ... ... ... '0' '0' ... ..... 1600 '0' ... ... ... ... ... ... FALSE

+1δδ ... ... ... ... ... ... '1' FALSE +2δδ ... ... ... ... ... ... '1' .....

2000 '1' '0' ... ... ... ... ... TRUE +1δδ '1' '0' ... ... ... ... '0' FALSE +2δδ ... ... ... ... ... ... '0' .....

2004 ... ... '0' '0' ... ... ... ..... 2005 ... ... ... ... '1' '1' ... .....

• Simulation results of the input_output architecture of the flipflop_test • All transactions are observed • In assigning:Two transactions on internal_state for every clock edge • Transaction on q1 at time 0004, is due to initialization • In guarding:c2.ff : GUARD sees GUARD inside guarding • Guard expression is only TRUE for 1 delta

• Events on edge detection expression • Demonstrating difference between ‘EVENT and NOT ‘STABLE

(d, 0)

Scheduling on S

c

s

(d, 6)

Value = s Value = d

Value = s Value = s

Value = s Value = d

Value = s Value = d

s

Scheduling on S

c

s

Scheduling on S

c

Scheduling on S

s

c

s <= d WHEN (c= ‘1’ AND NOT c’STABLE) ELSE UNAFFECTED;

UNAFFECTED

(a)

s <= d WHEN (c= ‘1’ AND c’EVENT) ELSE UNAFFECTED;

(d, 0)

(b)

s <= d AFTER 6 NS WHEN (c= ‘1’ AND NOT c’STABLE) ELSE s;

(c)

s <= d AFTER 6 NS WHEN (c= ‘1’ AND c’EVENT) ELSE s;

(d, 6)

(d)

(s, 0)

ENTITY d_flipflop IS GENERIC (delay1: TIME := 4 NS; delay2 : TIME := 5 NS); PORT (d, c : IN BIT; q, qb : OUT BIT); END ENTITY; -- ARCHITECTURE guarding OF d_flipflop IS BEGIN ff: BLOCK (c= '1' AND NOT c'STABLE) PORT (din : IN BIT; qout, qbar : OUT BIT); PORT MAP (din => d, qout => q, qbar => qb); BEGIN qout <= GUARDED din AFTER delay1; qbar <= GUARDED NOT din AFTER delay2; END BLOCK ff; END guarding;

• Using declarative part of a block statement • PORT specifies signals on the outside • PORT MAP maps outside signals with those inside • Association format is used as expected

• Syntax details for block statement with header • Uses this to draw a dashed line around a section of your hardware

PORT ( . . . );

qbar <= . . .;

BEGIN

ff : BLOCK ( . . . ) block_statement

port_clause block_header

block_statement_part

PORT MAP ( . . . );

qout <= . . .;

END BLOCK ff;

port_map_aspect



• A positive edge trigger flip-flop with enable input • Can nest block statements • Combining guard expressions must be done explicitly

1, 2D Q

C1

Q-

E2

MULTIPLEXING AND DATA SELECTION ENTITY de_flipflop IS GENERIC (delay1 : TIME := 4 NS; delay2 : TIME := 5 NS); PORT (d, e, c : IN BIT; q, qb : OUT BIT); END de_flipflop; -- ARCHITECTURE guarding OF de_flipflop IS BEGIN edge: BLOCK ( c = '1' AND NOT c'STABLE ) BEGIN gate: BLOCK ( e = '1' AND GUARD ) BEGIN q <= GUARDED d AFTER delay1; qb <= GUARDED NOT d AFTER delay2; END BLOCK gate; END BLOCK edge; END guarding;

• VHDL description for the positive edge trigger flip-flop with enable input

• Implicit GUARD signals in each block • Useful if different second conditions were used

MULTIPLEXING AND DATA SELECTION ENTITY dee_flipflop IS GENERIC (delay1 : TIME := 4 NS; delay2 : TIME := 5 NS); PORT (d2, d3, e2, e3, c : IN BIT; q, qb : OUT BIT); END dee_flipflop; -- ARCHITECTURE guarding OF dee_flipflop IS BEGIN edge: BLOCK ( c = '1' AND NOT c'STABLE ) BEGIN gate2: BLOCK ( e2 = '1' AND GUARD ) BEGIN q <= GUARDED d2 AFTER delay1; qb <= GUARDED NOT d2 AFTER delay2; END BLOCK gate2; gate3: BLOCK ( e3 = '1' AND GUARD ) BEGIN q <= GUARDED d3 AFTER delay1; qb <= GUARDED NOT d3 AFTER delay2; END BLOCK gate3; END BLOCK edge; END guarding;

• A positive edge trigger, double d flip-flop with independent enable inputs

• Clock expression is specified only once

1, 2D Q

C1

Q-

E2

E3

1, 3D

MULTIPLEXING AND DATA SELECTION ENTITY flipflop_test IS END flipflop_test; -- ARCHITECTURE input_output OF flipflop_test IS COMPONENT ff1 PORT (d, e, c : IN BIT; q, qb : OUT BIT); END COMPONENT; FOR c1 : ff1 USE ENTITY WORK.de_flipflop (guarding); SIGNAL dd, ee, cc, q1, qb1 : BIT; BEGIN cc <= NOT cc AFTER 400 NS WHEN NOW < 3 US ELSE cc; dd <= NOT dd AFTER 1000 NS WHEN NOW < 3 US ELSE dd; ee <= '1', '0' AFTER 2200 NS; c1: ff1 PORT MAP (dd, ee, cc, q1, qb1); END input_output;

• A test bench for testing the guarding architectures of de_flipflop • Testbench verifies operation of de_flipflop • After 2200 q1 is disconnected from d



TIME (ns)

cc

ee

dd

q1

qb1

0000 '0' '0' '0' '0' '0' +1δδ ... '1' ... ... ...

0400 '1' ... ... ... ... 0404 ... ... ... '0' ... 0405 ... ... ... ... '1' 0800 '0' ... ... ... ... 1000 ... ... '1' ... ... 1200 '1' ... ... ... ... 1204 ... ... ... '1' ... 1205 ... ... ... ... '0' 1600 '0' ... ... ... ... 2000 '1' ... '0' ... ... 2004 ... ... ... '0' ... 2005 ... ... ... ... '1' 2200 ... '0' ... ... ... 2400 '0' ... ... ... ... 2800 '1' ... ... ... ... 3000 ... ... '1' ... ...

+1δδ ... ... '1' ... ... 3200 '0' ... ... ... ...

+1δδ '0' ... ... ... ...

• Simulation results of the input_output architecture of the flipflop_test • All transactions are observed • No transactions on the outputs after 2200 NS



• Symbolizing guarded signal assignments • Disconnection in a guarded signal assignment • Driving value continues to be updated even if the guard expression is

false

Driving Value

RHS Activation

GUARD

0

Projected Output Waveform



• Normally several sources cannot drive a signal • Real circuits smoke, • So does VHDL

What follows concentrates on definition & applications of resolution functions

MULTIPLEXING AND DATA SELECTION USE WORK.basic_utilities.ALL; -- FROM PACKAGE USE: qit ENTITY y_circuit IS PORT (a, b, c, d : IN qit; z : OUT qit); END y_circuit; -- ARCHITECTURE smoke_generator OF y_circuit IS SIGNAL circuit_node : qit; BEGIN circuit_node <= a; circuit_node <= b; circuit_node <= c; circuit_node <= d; z <= circuit_node; END smoke_generator;

• Multiple sources for a simple signal • This results in an error message



• Multiple drivers is possible only if a resolution exists • Example in hardware is "open collector" • Pull_up provides resolution

A happy circuit, a happy VHDL

simulator



-- USE qit, qit_vector, “AND” from basic_utilities FUNCTION anding ( drivers : qit_VECTOR) RETURN qit IS VARIABLE accumulate : qit := '1'; BEGIN FOR i IN drivers'RANGE LOOP accumulate := accumulate AND drivers(i); END LOOP; RETURN accumulate; END anding;

• The anding resolution function, ANDs all its drivers • Performs the AND function two operand at a time • Collect all ANDs and return • A notation that we will use

anding circuit_node

d

c

b

a

MULTIPLEXING AND DATA SELECTION USE WORK.basic_utilities.ALL; -- FROM PACKAGE USE: qit ARCHITECTURE wired_and OF y_circuit IS FUNCTION anding (drivers : qit_vector) RETURN qit IS VARIABLE accumulate : qit := '1'; BEGIN FOR i IN drivers'RANGE LOOP accumulate := accumulate AND drivers(i); END LOOP; RETURN accumulate; END anding; SIGNAL circuit_node : anding qit; BEGIN circuit_node <= a; circuit_node <= b; circuit_node <= c; circuit_node <= d; z <= circuit_node; END wired_and;

• Multiple sources for a simple signal • The difference is in the declaration of the left-hand-side • This results in ANDing all sources • Specify anding for the resolution on circuit_node • Type of circuit_node is a subtype of qit • ANDing simultaneously receives all drivers



• Projected output waveforms and resolution functions • Every assignment in a concurrent body creates a driver • All assignments is a sequential body create only one driver • Resolution functions act on expired values

lhs_signal

0

v1 v2 v3 v4

t4 t3 t2 t1

0

t1 t2 t3 v4

t4 t3 t2 t1

0

v1 v2 v3 v4

t4 t3 t2 t1



• Guarded signal assignments into resolved signals • Drivers continue to perform normal in spite of disconnection • Resolution function cannot tell the difference, it only sees the driving

value

lhs_signal

RHS Activation

GUARD

0

v1 v2 v3 v4

t4 t3 t2 t1

Driver 1

RHS Activation

GUARD

0

v1 v2 v3 v4

t4 t3 t2 t1

Driver 2

MULTIPLEXING AND DATA SELECTION USE WORK.basic_utilities.ALL; -- FROM PACKAGE USE: qit ARCHITECTURE multiple_assignments OF mux_8_to_1 IS FUNCTION oring ( drivers : qit_vector) RETURN qit IS VARIABLE accumulate : qit := '0'; BEGIN FOR i IN drivers'RANGE LOOP accumulate := accumulate OR drivers(i); END LOOP; RETURN accumulate; END oring; SIGNAL t : oring qit; BEGIN t <= i7 AND s7; t <= i6 AND s6; t <= i5 AND s5; t <= i4 AND s4; t <= i3 AND s3; t <= i2 AND s2; t <= i1 AND s1; t <= i0 AND s0; z <= t; END multiple_assignments;

• Implementing the eight-to-one multiplexer using eight concurrent assignments

• ORing resolution function is used


MULTIPLEXING AND DATA SELECTION FUNCTION wire (a, b : qit) RETURN qit IS CONSTANT qit_wire_table : qit_2d := ( ('0','X','0','X'), ('X','1','1','X'), ('0','1','Z','X'), ('X','X','X','X')); BEGIN RETURN qit_wire_table (a, b); END wire;

• The wire function for modeling wiring two qit type nodes. • Input-output mapping • Circuit notation

0 1In1: Z X

Out

0

1

X

Z

In2: 0

0

X

1

1

X

0

1

Z

X

X

X

X

X X

X

Out

In1

In2

MULTIPLEXING AND DATA SELECTION FUNCTION wiring ( drivers : qit_vector) RETURN qit IS VARIABLE accumulate : qit := 'Z'; BEGIN FOR i IN drivers'RANGE LOOP accumulate := wire (accumulate, drivers(i)); END LOOP; RETURN accumulate; END wiring;

FUNCTION wiring ( drivers : qit_vector) RETURN qit; SUBTYPE wired_qit IS wiring qit; TYPE wired_qit_vector IS

ARRAY (NATURAL RANGE <>) OF wired_qit;

• The wiring resolution function for qit type operands • Necessary declarations for visibility of the wiring resolution function

and its related types and subtypes • If no drivers exist, ‘Z’ will be returned • To declare an array of this resolution

MULTIPLEXING AND DATA SELECTION FUNCTION oring ( drivers : BIT_VECTOR) RETURN BIT; SUBTYPE ored_bit IS oring BIT; TYPE ored_bit_vector IS ARRAY (NATURAL RANGE <>) OF ored_bit; FUNCTION oring ( drivers : BIT_VECTOR) RETURN BIT IS VARIABLE accumulate : BIT := '0'; BEGIN FOR i IN drivers'RANGE LOOP accumulate := accumulate OR drivers(i); END LOOP; RETURN accumulate; END oring;

SIGNAL t_byte : ored_qit_vector ( 7 DOWNTO 0 );

• Another complete example • The oring resolution function for the BIT type operands • OR for BIT is already defined • If no drivers, '0' is returned • Necessary type and subtype definitions for the basic_utilities package • Example signal declaration



• Will now model this circuit • An NMOS eight-to-one multiplexer • The CMOS version uses transmission gates instead of pass

transistors

bi: BLOCK ( si = '1' OR si = 'Z') BEGIN t <= GUARDED ii; END BLOCK;

A block statement modeling a transmission gate

• Disconnection is realized by block statements • If all drivers are disconnected actual hardware returns to 'Z'

si

ii t

MULTIPLEXING AND DATA SELECTION USE WORK.basic_utilities.ALL; -- FROM PACKAGE USE: wired_qit ARCHITECTURE multiple_guarded_assignments OF mux_8_to_1 IS SIGNAL t : wired_qit BUS; BEGIN b7: BLOCK (s7 = '1' OR s7 = 'Z') BEGIN t <= GUARDED i7;

END BLOCK; b6: BLOCK (s6 = '1' OR s6 = 'Z') BEGIN t <= GUARDED i6;







END BLOCK; z <= t; END multiple_guarded_assignments;

• Each ii connects to t if si is '1'; ii is disconnected from t if si is '0' • Use BUS to implement this behavior • Default in wire function is specified as 'Z' • This default is used if wiring is called with Null • Last disconnection causes call to wiring with Null



• An NMOS half-register with multiplexed input • Modeling this circuit must take inverter input capacitance into

account • t holds charge if all are disconnected • Circuit shows a register effect

USE WORK.basic_utilities.ALL; -- FROM PACKAGE USE: qit, wired_qit ENTITY multiplexed_half_register IS PORT (i7, i6, i5, i4, i3, i2, i1, i0 : IN qit; s7, s6, s5, s4, s3, s2, s1, s0 : IN qit; z : OUT qit ); END multiplexed_half_register; -- ARCHITECTURE guarded_assignments OF

multiplexed_half_register IS SIGNAL t : wired_qit REGISTER; BEGIN b7: BLOCK (s7 = '1' OR s7 = 'Z') BEGIN t <= GUARDED i7;








END BLOCK; z <= NOT t AFTER 8 NS; END guarded_assignments;

• Use REGISTER to model retaining of last value • No call is made to wiring upon last disconnection • BUS and REGISTER are kind specification • Signals with kind are guarded signals • Guarded signals must be used on LHS of guarded assignments • Ok to use unguarded signals on LHS of guarded assignments

BLOCK (guard_expression) BEGIN Guarded_lhs <= GUARDED rls_values; END;

--------------------------------------------------------------------------------------------- BLOCK (guard_expression) BEGIN Unguarded_resolved_signal <= GUARDED rls_values; END;

• Turning off drivers from guarded signals • Guard expression controls driver contribution to the resolution

function • Continuous contribution stops, even if a static value remains (if

unguarded LHS)

guarded_lhs_signal

RHS Activation

guard_expression

0

v1 v2 v3 v4

t4 t3 t2 t1

Driver i



Last disconnections: BUS kind, REGISTER kind, unguarded

• Disconnection disconnects if guarded • BUS kind, last disconnection calls resolution function with Null • REGISTER, last disconnection does not call the resolution function • Unguarded, disconnection disconnects, but holds static value at the

time of disconnection • For unguarded, last disconnection is no different than others

v v f(v) nullv

v f(null)

v v f(v) null v f(v)

v v f(v) v v f(v)

Before Last Disconnection After Last Disconnection

(a) BUS Kind (b) REGISTER Kind (c) Not Guarded

MULTIPLEXING AND DATA SELECTION USE WORK.basic_utilities.ALL; -- FROM PACKAGE USE: qit, qit_vector, wired_qit ENTITY mux_n_to_1 IS PORT (i, s : IN qit_vector; z : OUT wired_qit BUS); END mux_n_to_1; -- ARCHITECTURE multiple_guarded_assignments OF mux_n_to_1 IS BEGIN bi: FOR j IN i'RANGE GENERATE bj: BLOCK (s(j) = '1' OR s(j) = 'Z') BEGIN z <= GUARDED i(j); END BLOCK; END GENERATE; END multiple_guarded_assignments;

• mutliple_guarded_assignments architecture of the mux_n_to_1 • A general n-bit multiplexer • Ports can be resolved signals • BUS kind can also be specified, not REGISTER

MULTIPLEXING AND DATA SELECTION USE WORK.basic_utilities.ALL; ENTITY mux_tester IS END mux_tester; -- ARCHITECTURE input_output OF mux_tester IS COMPONENT mux

PORT (i, s : IN qit_vector; z : OUT wired_qit BUS); END COMPONENT; FOR ALL : mux USE ENTITY WORK.mux_n_to_1 (multiple_guarded_assignments); SIGNAL ii, ss : qit_vector (3 DOWNTO 0) := "0000"; SIGNAL zz : qit; BEGIN ii <= "1010" AFTER 10 US, "Z100" AFTER 20 US,

"0011" AFTER 30 US; ss <= "0010" AFTER 05 US, "1100" AFTER 15 US,

"000Z" AFTER 25 US; mm : mux PORT MAP (ii, ss, zz); END input_output;

• A test bench for the generic multiple_guarded_assignments architecture of mux_n_to_1

• This entity is used as a four bit multiplexer



TIME (ns)

ii(3:0)

ss(3:0)

zz

00000 "0000" "0000" '0' +1δδ ...... ...... 'Z'

05000 ...... "0010" ... +1δδ ...... ...... '0'

10000 "1010" ...... ... +1δδ ...... ...... '1'

15000 ...... "1100" ... +1δδ ...... ...... 'X'

20000 "Z100" ...... ... +1δδ ...... ...... '1'

25000 ...... "000Z" ... +1δδ ...... ...... '0'

30000 "0011" ...... ... +1δδ ...... ...... '1'

• Simulation results of the input_output architecture of the mux_tester • Simulation produces 'X' for two conflicting enabled inputs • Produces 'Z' when no inputs are enabled



Remaining issues:

Disconnection

Right and left

INOUT

• Will discuss other issues, then will start using resolved, guarded, and other signal types

• Several examples will follow

More issues on resolutions, guarded signals & resolved signals will de discussed

MULTIPLEXING AND DATA SELECTION ARCHITECTURE . . . SIGNAL t : wired_qit; BEGIN

. . . t <= GUARDED ii AFTER n NS; . . . END ARCHITECTURE;

Connection is timed: After connection, it takes n NS for t to get ii ARCHITECTURE . . . SIGNAL t : wired_qit; DISCONNECT t : wired_qit AFTER 6 NS; BEGIN

. . . t <= GUARDED ii AFTER n NS; . . . END ARCHITECTURE;

Time disconnection by DISCONNECT statement: Disconnection from t occurs m NS after GUARD becomes FALSE

• Specify disconnection in the declaration • Use ALL for all signals of that type • Use OTHERS if some specified otherwise

si

ii t

a <= a AND b AFTER delay;

• Resolved signals on right and left hand sides • What you get is not what you put in • Others contribute to a resolved signal

Value placed on driver of a

Value used on the right hand side

0

v1 v2 v3 v4

t4 t3 t2 t1

Other Drivers


MULTIPLEXING AND DATA SELECTION ENTITY one (a : IN BIT; x : INOUT BIT) … ENTITY two (b : IN BIT; y : INOUT BIT) …

-- ENTITY three IS END three; ARCHITECTURE connecting OF three IS SIGNAL z : oring BIT; . . . BEGIN c1 : ENTITY WORK.one PORT MAP (a, z); c2 : ENTITY WORK.two PORT MAP (b, z); . . END connecting;

• Connecting INOUT ports require resolved signals • There are two drivers for each interconnection

ax

by

oring

z


STATE MACHINE DESCRIPTION

• State names indicate detected sequences • Use resolutions & guarded blocks • A simple 1011 Mealy detector • A block statement for each state

Will use resolutions and guarded assignments in several examples

ENTITY detector IS PORT (x, clk : IN BIT; z : OUT BIT); END detector; ARCHITECTURE singular_state_machine OF detector IS TYPE state IS (reset, got1, got10, got101); TYPE state_vector IS ARRAY (NATURAL RANGE <>) OF state; FUNCTION one_of (sources : state_vector) RETURN state IS BEGIN RETURN sources(sources'LEFT); END one_of; SIGNAL current : one_of state REGISTER := reset; BEGIN clocking : BLOCK (clk = '1' AND NOT clk'STABLE) BEGIN s1: BLOCK ( current = reset AND GUARD ) BEGIN current <= GUARDED got1 WHEN x = '1' ELSE reset; END BLOCK s1; s2: BLOCK ( current = got1 AND GUARD ) BEGIN current <= GUARDED got10 WHEN x = '0' ELSE got1; END BLOCK s2; s3: BLOCK ( current = got10 AND GUARD ) BEGIN current <= GUARDED got101 WHEN x = '1' ELSE reset; END BLOCK s3; s4: BLOCK ( current = got101 AND GUARD) BEGIN current <= GUARDED got1 WHEN x = '1' ELSE got10; z <= '1' WHEN ( current = got101 AND x = '1') ELSE '0'; END BLOCK s4; END BLOCK clocking; END singular_state_machine;

• VHDL description of 1011 detector • Only one simultaneous active state • Current receives four concurrent assignments • Current must be resolved; use one_of

STATE MACHINE DESCRIPTION USE WORK.basic_utilities.ALL; -- FROM PACKAGE USE: ored_bit_vector ARCHITECTURE multiple_state_machine OF detector IS SIGNAL s : ored_bit_vector (1 TO 4) REGISTER := "1000"; BEGIN clocking : BLOCK (clk = '1' AND NOT clk'STABLE) BEGIN s1: BLOCK (s(1) = '1' AND GUARD) BEGIN s(1) <= GUARDED '1' WHEN x = '0' ELSE '0'; s(2) <= GUARDED '1' WHEN x = '1' ELSE '0'; END BLOCK s1; s2: BLOCK (s(2) = '1' AND GUARD) BEGIN s(3) <= GUARDED '1' WHEN x = '0' ELSE '0'; s(2) <= GUARDED '1' WHEN x = '1' ELSE '0'; END BLOCK s2; s3: BLOCK (s(3) = '1' AND GUARD) BEGIN s(1) <= GUARDED '1' WHEN x = '0' ELSE '0'; s(4) <= GUARDED '1' WHEN x = '1' ELSE '0'; END BLOCK s3; s4: BLOCK (s(4) = '1' AND GUARD) BEGIN s(3) <= GUARDED '1' WHEN x = '0' ELSE '0'; s(2) <= GUARDED '1' WHEN x = '1' ELSE '0'; z <= '1' WHEN (s(4) = '1' AND x = '1') ELSE '0'; END BLOCK s4; s <= GUARDED "0000"; END BLOCK clocking; END multiple_state_machine;

• VHDL description of 1011 detector • More than one state can simultaneously be active • The last description does not allows multiple active states • To remedy: use a signal for each state • State 3 : goes to 1 when x = '0'; goes to 4 when x = '1'

STATE MACHINE DESCRIPTION USE WORK.basic_utilities.ALL; -- FROM PACKAGE USE: ored_bit_vector ARCHITECTURE multiple_state_machine OF detector IS SIGNAL s : ored_bit_vector (1 TO 4) REGISTER := "1000"; BEGIN clocking : BLOCK (clk = '1' AND NOT clk'STABLE) BEGIN . . . s2: BLOCK (s(2) = '1' AND GUARD) BEGIN s(3) <= GUARDED '1' WHEN x = '0' ELSE '0'; s(2) <= GUARDED '1' WHEN x = '1' ELSE '0'; END BLOCK s2; s3: BLOCK (s(3) = '1' AND GUARD) BEGIN s(1) <= GUARDED '1' WHEN x = '0' ELSE '0'; s(4) <= GUARDED '1' WHEN x = '1' ELSE '0'; END BLOCK s3; . . . s <= GUARDED "0000"; END BLOCK clocking; END multiple_state_machine;

• State 3 : goes to 1 when x = '0'; goes to 4 when x = '1' • S must be resolved vector REGISTER kind • S <= GUARDED "0000"; Causes removal of retained value upon

last disconnection

ENTITY detector_m IS PORT (x,clk : IN BIT; z : OUT BIT); GENERIC (n : INTEGER); END detector_m; -- ARCHITECTURE multiple_moore_machine_1 OF detector_m IS FUNCTION oring( drivers : BIT_VECTOR) RETURN BIT IS VARIABLE accumulate : BIT := '0'; BEGIN FOR i IN drivers'RANGE LOOP accumulate := accumulate OR drivers(i); END LOOP; RETURN accumulate; END oring; SUBTYPE ored_bit IS oring BIT; TYPE ored_bit_vector IS ARRAY (NATURAL RANGE <>) OF ored_bit; TYPE next_table IS ARRAY (1 TO n, BIT) OF INTEGER; TYPE out_table IS ARRAY (1 TO n, BIT) OF BIT; -- Fill in next_val, out_val, and s arrays SIGNAL o : ored_bit REGISTER; BEGIN clocking : BLOCK (clk = '1' AND (NOT clk'STABLE)) BEGIN g: FOR i IN s'RANGE GENERATE si: BLOCK (s(i) = '1' AND GUARD) BEGIN s(next_val(i,'0')) <= GUARDED '1' WHEN x='0' ELSE '0'; s(next_val(i,'1')) <= GUARDED '1' WHEN x='1' ELSE '0'; o <= GUARDED out_val(i, x); END BLOCK si; s (i) <= GUARDED '0'; END GENERATE; END BLOCK clocking; z <= o; END multiple_moore_machine_1;

• A generic state machine • A Moore sequence detector • Specify transitions & outputting in constant tables • Allows multiple machines in one


STATE MACHINE DESCRIPTION ----------------------------------------------------------------- --Tables for programming the configurable Moore description -- ----------------------------------------------------------------- -- -- Next States: ----- x=0, x=1 -- CONSTANT next_val : next_table := ( (1 , 2), --S1: -> S1, S2 -- (1 , 3), --S2: -> S1, S3 -- (1 , 4), --S3: -> S1, S4 -- (1 , 1), --S4: -> S1, S1 -- (5 , 6), --S5: -> S5, S6 -- (5 , 6) );--S6: -> S5, S6 -- -- -- -- -- Output Values: ----- x=0, x=1 -- CONSTANT out_val : out_table := ( ('0' , '0'), --S1: == z=0, 0 -- ('0' , '0'), --S2: == z=0, 0 -- ('0' , '0'), --S3: == z=0, 0 -- ('1' , '1'), --S4: == z=1, 1 -- ('0' , '0'), --S5: == z=0, 0 -- ('1' , '1') );--S6: == z=1, 1 -- -- -- -- Initial Active States: -- SIGNAL s : ored_bit_vector (1 TO 6) REGISTER := "100010"; -- ----------------------------------------------------------------- -----------------------------------------------------------------

• Next state and output tables • The next_val constant holds next state values • The out_val constant holds the output values on the z output • Initial starting states are set to '1' in the s vector


OPEN COLLECTOR GATES

• Open collector NAND gate • A two-input NAND gate, TTL 74LS03 SSI package • Resolution functions are used in bussing • Will use open collector to illustrate

y

GND

VCC

a

b

OPEN COLLECTOR GATES USE WORK.basic_utilities.ALL; -- FROM PACKAGE USE: qit, "AND" ENTITY nand2 IS PORT (a, b : IN qit; y : OUT qit); CONSTANT tplh : TIME := 10 NS; CONSTANT tphl : TIME := 12 NS; END nand2; -- ARCHITECTURE open_output OF nand2 IS BEGIN y <= '0' AFTER tphl WHEN (a AND b) = '1' ELSE 'Z' AFTER tplh WHEN (a AND b) = '0' ELSE 'X' AFTER tphl; END open_output;

• VHDL description of a NAND gate with open collector output • Use qit type • Output is ‘Z’ and not ‘1’


OPEN COLLECTOR GATES ENTITY test_nand2 IS END test_nand2; -- USE WORK.basic_utilities.ALL; -- FROM PACKAGE USE: qit, assign_bits ARCHITECTURE input_output OF test_nand2 IS COMPONENT nand2 PORT (a, b : IN qit; y : OUT qit);

END COMPONENT; FOR ALL : nand2 USE ENTITY WORK.nand2 (open_output); SIGNAL aa, bb, yy : qit; BEGIN assign_bits (aa, "qit_data", 500 NS); assign_bits (bb, "qit_data", 750 NS); c1: nand2 PORT MAP (aa, bb, yy); END input_output;

• Testing the open-collector NAND gate • Test bench uses external data file • Output is either ‘0’ or ‘Z’, never ‘1’

TIME (ns)

aa

bb

yy

0000 '0' '0' '0' 0010 ... ... 'Z' 1000 '1' ... ... 1500 ... '1' ... 1512 ... ... '0’ 2500 '0' ... ... 2510 ... ... 'Z' 3000 'Z' ... ... 3012 ... ... '0' 3750 ... '0' ... 3760 ... ... 'Z' 4000 '0' ... ... 4500 '1' 'Z' ... 4512 ... ... '0' 5000 '0' ... ... 5010 ... ... 'Z' 5500 'Z' ... ... 5512 ... ... '0' 6000 ... '0' ... 6010 ... ... 'Z' 6750 ... '1' ... 6762 ... ... '0' 7500 ... '0' ... 7510 ... ... 'Z' 8250 ... 'Z' ... 8262 ... ... '0'


OPEN COLLECTOR GATES USE WORK.basic_utilities.ALL; -- FROM PACKAGE USE: qit ENTITY sn7403 IS PORT (a1, a2, a3, a4, b1, b2, b3, b4 : IN qit; y1, y2, y3, y4 : OUT qit); END sn7403; -- ARCHITECTURE structural OF sn7403 IS COMPONENT nand2 PORT (a, b : IN qit; y : OUT qit);

END COMPONENT; FOR ALL : nand2 USE ENTITY WORK.nand2 (open_output); BEGIN g1: nand2 PORT MAP ( a1, b1, y1 ); g2: nand2 PORT MAP ( a2, b2, y2 ); g3: nand2 PORT MAP ( a3, b3, y3 ); g4: nand2 PORT MAP ( a4, b4, y4 ); END structural;

• VHDL description of TTL 74LS03 • Contains four open collector NAND gates • Will use in a design



yy = (aa' . bb)’ . (bb' . aa)' = ( aa ⊕⊕ bb )'

• Implementing XNOR logic using open collector NAND gates • Using 74LS03 for implementing an XNOR • pull_up3 has two drivers • pull_up1 and pull_up2 must be turned to ‘0’, ‘1’ logic

a1

b1

a2

b2

g1

g2

g3

g4

aa

bb

y1

y2

a4

b4

y4

a3

b3

y3

yy

pull_up_3

pull_up_1

pull_up_2

OPEN COLLECTOR GATES USE WORK.basic_utilities.ALL; -- FROM PACKAGE USE: qit, anded_qit ENTITY test_xnor IS END test_xnor; -- ARCHITECTURE input_output OF test_xnor IS COMPONENT sn7403 PORT (a1, a2, a3, a4, b1, b2, b3, b4 : IN qit;

y1, y2, y3, y4 : OUT qit); END COMPONENT; FOR ALL : sn7403 USE ENTITY WORK.sn7403 (structural); SIGNAL aa, bb : qit; SIGNAL pull_up_1, pull_up_2, pull_up_3 : anded_qit := 'Z'; BEGIN aa <= '1', '0' AFTER 10US, '1' AFTER 30US,

'0' AFTER 50US, 'Z' AFTER 60US; bb <= '0', '1' AFTER 20US, '0' AFTER 40US, 'Z' AFTER 70US; c1: sn7403 PORT MAP ( aa, bb, pull_up_1, pull_up_2, aa, bb, bb, aa, pull_up_1, pull_up_2, pull_up_3, pull_up_3); END input_output;

• Wiring and testing XNOR function implemented by four open collector AND gates

• pull_up_1 and pull_up_2 turn 0,Z to 0,1 • anded_qit resolution function implements wired logic



TIME (us)

aa

bb

pull_up_1

pull_up_2

pull_up_3

00 '1' '0' '0' '0' '0' 02 '1' '0' '0' '1' '0' 04 '1' '0' '0' '1' '0' 06 '1' '0' '0' '1' '0' 08 '1' '0' '0' '1' '0' 10 '0' '0' '0' '1' '0' 12 '0' '0' '1' '1' '1' 14 '0' '0' '1' '1' '1' 16 '0' '0' '1' '1' '1' 18 '0' '0' '1' '1' '1' 20 '0' '1' '1' '1' '1' 22 '0' '1' '1' '0' '0' 24 '0' '1' '1' '0' '0' 26 '0' '1' '1' '0' '0' 28 '0' '1' '1' '0' '0' 30 '1' '1' '1' '0' '0' 32 '1' '1' '0' '0' '1' 34 '1' '1' '0' '0' '1' 36 '1' '1' '0' '0' '1' 38 '1' '1' '0' '0' '1' 40 '1' '0' '0' '0' '1' 42 '1' '0' '0' '1' '0' 44 '1' '0' '0' '1' '0' 46 '1' '0' '0' '1' '0' 48 '1' '0' '0' '1' '0' 50 '0' '0' '0' '1' '0' 52 '0' '0' '1' '1' '1' 54 '0' '0' '1' '1' '1' 56 '0' '0' '1' '1' '1' 58 '0' '0' '1' '1' '1' 60 'Z' '0' '1' '1' '1' 62 'Z' '0' '0' '1' '0' 64 'Z' '0' '0' '1' '0' 66 'Z' '0' '0' '1' '0' 68 'Z' '0' '0' '1' '0' 70 'Z' 'Z' '0' '1' '0'

• Results are observed at 2 us intervals • Simulation shows XNOR implementation • Pull up resolutions turn gate output 'Z' values to '1'


THREE STATE BUSSING

• A bussing system (bus_sys) • Will use resolution functions for describing it • A very common hardware for RT level descriptions • Some components have three-state outputs some do not

alu reg1bus1

unit1 unit2

u1 : u2 : u3 :

8

8

8

u4 : u5 :

bus a


THREE STATE BUSSING

ENTITY alu IS PORT (… ; zout : out qit_vector (7 DOWNTO 0)); END alu; -- ENTITY reg1 IS PORT (… ; zout : out wired_qit_vector (7 DOWNTO 0)); END reg1; -- SIGNAL bus1 : wired_qit_vector (7 DOWNTO 0); -- ENTITY unit1 IS PORT (zin : IN qit_vector (7 DOWNTO 0); …); END unit1; -- ENTITY unit2 IS PORT (zin : IN wired_qit_vector (7 DOWNTO 0); …); END unit2;

• Interface of bus sources and destinations • Wired_qit_vector is used for those with three-state outputs • Connection of others must be through three-state constructs

THREE STATE BUSSING ARCHITECTURE partial OF bus_sys IS SIGNAL busa : wired_qit_vector (7 DOWNTO 0); SIGNAL bus1 : wired_qit_vector (7 DOWNTO 0); SIGNAL aluout, unit1in : qit_vector (7 DOWNTO 0); BEGIN . . . u1 : ENTITY WORK.alu PORT MAP (…; aluout); busa <= wired_qit_vector (aluout); ... u2 : ENTITY WORK.reg1 PORT MAP (…; busa); … u3 : busa <= bus1; … unit1in <= qit_vector (busa); u4 : ENTITY WORK.unit1 PORT MAP (unit1in;…); … u5 : ENTITY WORK.unit2 PORT MAP (busa;…); … END partial;

• Partial VHDL description for bussing system example • reg1 with three-state output directly drives the bus • aluout goes through three-state constructs • All required hardware structures are explicitly coded


Std_logic BUSSING

std_ulogic for “standard unresolved logic” A resolution function: resolution std_logic is defined as resolution subtype of std_logic Vectorized std_logic and std_ulogic are defined, e.g., std_logic_vector Conversions from one type to another are provided Logic operators are overloaded for both types and their vectorized forms

• Std_logic provides multi-value logic for most applications • No need for new user types • Most designers use the resolved type


A GENERAL DATAFLOW CIRCUIT

• Seen dataflow primitives • Use dataflow for system description • A sequential comparator example

Count equal sequential

data on parallel input

lines.

8-bit Parallel data

Reset input

4-bit Count output

A GENERAL DATAFLOW CIRCUIT USE WORK.basic_utilities.ALL; -- FROM PACKAGE USE: bin2int, int2bin ENTITY sequential_comparator IS PORT (data : IN BIT_VECTOR (7 DOWNTO 0); clk, reset : IN BIT; matches : OUT BIT_VECTOR (3 DOWNTO 0)); END sequential_comparator; -- ARCHITECTURE dataflow OF sequential_comparator IS FUNCTION inc (x : BIT_VECTOR) RETURN BIT_VECTOR IS VARIABLE i : INTEGER; VARIABLE t : BIT_VECTOR (x'RANGE); BEGIN bin2int (x, i); i := i + 1; IF i >= 2**x'LENGTH THEN i := 0; END IF; int2bin (i, t); RETURN t; END inc; SIGNAL buff : BIT_VECTOR (7 DOWNTO 0); SIGNAL count : BIT_VECTOR (3 DOWNTO 0); BEGIN edge: BLOCK (clk = '0' AND NOT clk'STABLE) BEGIN buff <= GUARDED data; count <= GUARDED "0000" WHEN reset = '1' ELSE inc (count) WHEN data = buff ELSE count; END BLOCK; matches <= count; END dataflow;

• Dataflow description of the sequential comparator circuit • inc function is unconstrained • Save old data in buff • Compares old and new


A GENERAL DATAFLOW CIRCUIT

TIME (ns)

reset

clk

data(7:0)

buff(7:0)

count(3:0)

matches

0000 '0' '0' "00000000" "00000000" "0000" "0000" +1δδ ... ... .......... .......... ...... "0000"

0200 ... ... "11110101" .......... ...... ...... 0500 ... '1' .......... .......... ...... ...... 1000 ... '0' .......... .......... ...... ......

+1δδ ... ... .......... "11110101" "0000" ...... 1200 ... ... "01010110" .......... ...... ...... 1500 ... '1' .......... .......... ...... ...... 1700 ... ... "11111110" .......... ...... ...... 2000 ... '0' .......... .......... ...... ......

+1δδ ... ... .......... "11111110" "0000" ...... 2500 ... '1' .......... .......... ...... ...... 3000 ... '0' .......... .......... ...... ......

+1δδ ... ... .......... "11111110" "0001" ...... +2δδ ... ... .......... .......... ...... "0001"

3200 ... ... "01010100" .......... ...... ...... 3500 ... '1' .......... .......... ...... ...... 3700 ... ... "00010001" .......... ...... ...... 4000 ... '0' .......... .......... ...... ......

+1δδ ... ... .......... "00010001" "0001" ...... 4200 ... ... "10010110" .......... ...... ...... 4500 ... '1' .......... .......... ...... ...... 5000 ... '0' .......... .......... ...... ......

+1δδ ... ... .......... "10010110" "0001" ...... 5500 ... '1' .......... .......... ...... ...... 6000 ... '0' .......... .......... ...... ......

+1δδ ... ... .......... "10010110" "0010" ...... +2δδ ... ... .......... .......... ...... "0010"

6500 ... '1' .......... .......... ...... ...... 7000 ... '0' .......... .......... ...... ......

+1δδ ... ... .......... "10010110" "0011" ...... +2δδ ... ... .......... .......... ...... "0011"

7500 ... '1' .......... .......... ...... ...... 8000 ... '0' .......... .......... ...... ......

+1δδ ... ... .......... "10010110" "0100" ...... +2δδ ... ... .......... .......... ...... "0100"

8500 ... '1' .......... .......... ...... ......

• matches shows count of matching data

UPDATING BASIC UTILITIES

PACKAGE basic_utilities IS . . FUNCTION wire (a, b : qit) RETURN qit; -- FUNCTION oring ( drivers : qit_vector) RETURN qit; SUBTYPE ored_qit IS oring qit; TYPE ored_qit_vector IS ARRAY (NATURAL RANGE <>) OF ored_qit; -- FUNCTION anding ( drivers : qit_vector) RETURN qit; SUBTYPE anded_qit IS anding qit; TYPE anded_qit_vector IS

ARRAY (NATURAL RANGE <>) OF anded_qit; -- FUNCTION wiring ( drivers : qit_vector) RETURN qit; SUBTYPE wired_qit IS wiring qit; TYPE wired_qit_vector IS

ARRAY (NATURAL RANGE <>) OF wired_qit; -- FUNCTION oring ( drivers : BIT_VECTOR) RETURN BIT; SUBTYPE ored_bit IS oring BIT; TYPE ored_bit_vector IS

ARRAY (NATURAL RANGE <>) OF ored_bit; -- FUNCTION anding ( drivers : BIT_VECTOR) RETURN BIT; SUBTYPE anded_bit IS anding bit; TYPE anded_bit_vector IS

ARRAY (NATURAL RANGE <>) OF anded_bit; -- FUNCTION inc (x : BIT_VECTOR) RETURN BIT_VECTOR; END basic_utilities;


UPDATING BASIC UTILITIES

PACKAGE BODY basic_utilities IS . . . FUNCTION wire (a, b : qit) RETURN qit IS CONSTANT qit_wire_table : qit_2d := ( ('0','X','0','X'), ('X','1','1','X'), ('0','1','Z','X'), ('X','X','X','X')); BEGIN RETURN qit_wire_table (a, b); END wire; FUNCTION oring ( drivers : qit_vector) RETURN qit IS VARIABLE accumulate : qit := '0'; BEGIN FOR i IN drivers'RANGE LOOP accumulate := accumulate OR drivers(i); END LOOP; RETURN accumulate; END oring; FUNCTION anding ( drivers : qit_vector) RETURN qit IS VARIABLE accumulate : qit := '1'; BEGIN FOR i IN drivers'RANGE LOOP accumulate := accumulate AND drivers(i); END LOOP; RETURN accumulate; END anding;

FUNCTION wiring ( drivers : qit_vector) RETURN qit IS VARIABLE accumulate : qit := 'Z'; BEGIN FOR i IN drivers'RANGE LOOP accumulate := wire (accumulate, drivers(i)); END LOOP; RETURN accumulate; END wiring;


UPDATING BASIC UTILITIES FUNCTION oring ( drivers : BIT_VECTOR) RETURN BIT IS VARIABLE accumulate : BIT := '0'; BEGIN FOR i IN drivers'RANGE LOOP accumulate := accumulate OR drivers(i); END LOOP; RETURN accumulate; END oring; FUNCTION anding ( drivers : BIT_VECTOR) RETURN BIT IS VARIABLE accumulate : BIT := '1'; BEGIN FOR i IN drivers'RANGE LOOP accumulate := accumulate AND drivers(i); END LOOP; RETURN accumulate; END anding;

FUNCTION inc (x : BIT_VECTOR) RETURN BIT_VECTOR IS VARIABLE i : INTEGER; VARIABLE t : BIT_VECTOR (x'RANGE); BEGIN bin2int (x, i); i := i + 1; IF i >= 2**x'LENGTH THEN i := 0; END IF; int2bin (i, t); RETURN t; END inc; END basic_utilities;

• Resolution functions and inc function added to basic_utilities


SUMMARY

This chapter presented signal assignment, guarded

assignments, and resolution functions, which are

considered to be among the most important hardware

related constructs in the VHDL language.

Guarded signal assignment and the concept of

disconnection, or turning off a source, were presented.

This prepared the way for describing resolution

functions, multiple drivers of signals, and guarded

signals. Although VHDL only requires resolution of

signals with multiple concurrent sources, in general a

resolved signal is a better representation of a circuit

node. A resolution function for a node can be written to

match its technology-dependent behavior. The

resolution functions developed in this chapter are typical

of the way buses function in a digital system.



CHAPTER 9 BEHAVIORAL DESCRIPTION

OF HARDWARE

9.1 PROCESS STATEMENT 9.1.1 Declarative Part of a Process 9.1.2 Statement Part of a Process 9.1.3 Sensitivity List 9.1.4 A First Process Example 9.1.5 Syntax Details of Process Statements 9.1.6 Postponed Processes 9.1.7 Passive Processes 9.1.8 Behavioral Flow Control Constructs

9.2 ASSERTION STATEMENT 9.2.1 Sequential Use of Assertion Statements 9.2.2 Concurrent Assertion Statements

9.3 SEQUENTIAL WAIT STATEMENTS 9.3.1 A Behavioral State Machine 9.3.2 Two Phase Clocking 9.3.3 Implementing Handshaking 9.3.4 Interface Handshaking

9.4 FORMATTED ASCII I/O OPERATIONS 9.4.1 Basic Screen Output 9.4.2 A Display Procedure 9.4.3 Simulation Report

9.5 MSI BASED DESIGN 9.5.1 Top Level Partitioning 9.5.2 Description of Components 9.5.3 Design Implementation

9.6 SUMMARY

• Constructs for sequential descriptions • Process statement is a key construct • Assertion for behavioral checks • Handshaking constructs • Timing control • Formatted I/O


PROCESS STATEMENT

• PROCESS: • A concurrent statement, enclosing sequential statements • Declarative part contains only variables and constants • Use only sequential constructs

Always active process statement_part (sequential) . . .

Always alive process declarative_part (non-signal) . . .

PROCESS

BEGIN

END PROCESS;

Concurrent process statement

Process statements describe hardware without much hardware details


PROCESS STATEMENT

• Unless a sequential body is suspended • It executes in zero real and delta time • It repeats itself forever

END PROCESS;

PROCESS BEGIN

Reapets forever,

In zero time,

S e q u e n t i a l Unless suspended

PROCESS STATEMENT ARCHITECTURE sequentiality_demo OF partial_process IS BEGIN PROCESS BEGIN ... x <= a; y <= b; ... END PROCESS; END sequentiality_demo;

• First: a is scheduled for x • Next: b is scheduled for y • x and y receive values at the same time • Both assignments occur a delta later • Zero time between both scheduling

PROCESS STATEMENT ARCHITECTURE execution_time_demo OF partial_process IS BEGIN PROCESS BEGIN ... x <= a AFTER 10 NS; y <= b AFTER 6 NS; ... END PROCESS; END execution_time_demo;

• First: a is scheduled for x • Next: b is scheduled for y • y receives b sooner than x receiving a

PROCESS STATEMENT

ARCHITECTURE data_availability_demo OF partial_process IS BEGIN PROCESS BEGIN ... x <= '1'; IF x = '1' THEN Perform_action_1 ELSE Perform_action_2 END IF; ... END PROCESS; END data_availability_demo;

• Assume x_sig is initially '0' • Assignment of '1' to x_sig takes a delta • Action_2 will be taken • Variable x_var had to be declared inside the Process statement • If x_var was used instead of x_sig, action_1 would be taken

PROCESS STATEMENT ARCHITECTURE … ARCHITECTURE … BEGIN BEGIN … … a <= b; PROCESS (b) … … c <= d; a <= b; … END PROCESS; END …; … c <= d; … END …;

Process is a concurrent statement

Signal assignment is a concurrent statement Process sensitivity plays the role of RHS activation

Any signal assignment can be expressed by a process statement

• Can use a signal assignment in a sequential body • On the left: events on b cause assignment • Process is executed when an event occurs on b • On the right: (b) is sensitivity list of process • Process statement executes only once for every event on b • Process suspends till next event on b occurs


PROCESS STATEMENT

1D Q

C1 Q-

S

R

• Have modeled flip-flops with concurrent statements • A process statement is a powerful construct for such descriptions

A flip-flop will demonstrate assignments and flow in process statements

PROCESS STATEMENT ENTITY d_sr_flipflop IS GENERIC (sq_delay, rq_delay, cq_delay : TIME := 6 NS); PORT (d, set, rst, clk : IN BIT; q, qb : OUT BIT); END d_sr_flipflop; -- ARCHITECTURE behavioral OF d_sr_flipflop IS SIGNAL state : BIT := '0'; BEGIN dff: PROCESS (rst, set, clk) BEGIN IF set = '1' THEN state <= '1' AFTER sq_delay; ELSIF rst = '1' THEN state <= '0' AFTER rq_delay; ELSIF clk = '1' AND clk'EVENT THEN state <= d AFTER cq_delay; END IF; END PROCESS dff; q <= state; qb <= NOT state; END behavioral;

• Three concurrent processes • dff process is sensitive to (rst, set, clk) • Internal state receives proper value • Events on state cause events on q and qb

PROCESS STATEMENT ARCHITECTURE average_delay_behavioral OF d_sr_flipflop IS BEGIN dff: PROCESS (rst, set, clk) VARIABLE state : BIT := '0'; BEGIN IF set = '1' THEN state := '1'; ELSIF rst = '1' THEN state := '0'; ELSIF clk = '1' AND clk'EVENT THEN state := d; END IF; q <= state AFTER (sq_delay + rq_delay + cq_delay) /3; qb <= NOT state AFTER (sq_delay + rq_delay + cq_delay) /3; END PROCESS dff; END average_delay_behavioral;

• Single process assigns values to q and qb • This description eliminates the δδ delay of the last description • Less precise timing


PROCESS STATEMENT

• Simulation run compares flip-flop descriptions • The 3 process description has a δδ delay • However, potential of more precise timing

TIME (NS)

ss

rr

cc

dd

q1

q2

qb1

qb2

0 '0' '0' '0' '0' '0' '0' '0' '0' +1δδ ... ... ... ... ... ... '1' ...

6 ... ... ... ... ... ... ... '1' 200 '1' ... ... ... ... ... ... ... 206 ... ... ... ... ... '1' ... '0'

+1δδ ... ... ... ... '1' ... '0' ... 500 ... ... '1' ... ... ... ... ...

1000 ... ... '0' ... ... ... ... ... 1200 '0' ... ... ... ... ... ... ... 1400 ... '1' ... ... ... ... ... ... 1406 ... ... ... ... ... '0' ... '1' +1δδ ... ... ... ... '0' ... '1' ...

1500 ... ... '1' ... ... ... ... ... 2000 ... ... '0' ... ... ... ... ... 2200 ... '0' ... ... ... ... ... ... 2400 ... ... ... '1' ... ... ... ... 2500 ... ... '1' ... ... ... ... ... 2506 ... ... ... ... ... '1' ... '0' +1δδ ... ... ... ... '1' ... '0' ... 3000 ... ... '0' ... ... ... ... ... 3300 ... ... ... '0' ... ... ... ... 3500 ... ... '1' ... ... ... ... ... 3506 ... ... ... ... ... '0' ... '1' +1δδ ... ... ... ... '0' ... '1' ... 4000 ... ... '0' ... ... ... ... ...

PROCESS STATEMENT

ENTITY d_sr_flipflop IS GENERIC (sq_delay, rq_delay, cq_delay : TIME := 6 NS); PORT (d, set, rst, clk : IN BIT; q, qb : OUT BIT); END ENTITY; -- ARCHITECTURE behavioral OF d_sr_flipflop IS BEGIN dff: PROCESS (rst, set, clk) TYPE bit_time IS RECORD state : BIT; delay : TIME; END RECORD; VARIABLE sd : bit_time := ('0', 0 NS); BEGIN IF set = '1' THEN sd := ('1', sq_delay); ELSIF rst = '1' THEN sd := ('0', rq_delay); ELSIF clk = '1' AND clk'EVENT THEN sd := (d, cq_delay); END IF; q <= sd.state AFTER sd.delay; qb <= NOT sd.state AFTER sd.delay; END PROCESS dff; END behavioral;

• This example uses a record for delay and flip-flop values • Logic value and delay are assigned to variables • Assignment to variables are done in zero time without the δδ delay

PROCESS STATEMENT

• Syntax details include sensitivity list

variable declaration

state := ‘0’;

state := ‘1’;

BEGIN

(rst, set, clk)

state :

state := d;

q <= state AFTER

cq_delay)/3;

(sq_delay + rq_delay +

sensitivity_list

sequential statement

process declarative part

VARIABLE

dff: PROCESS

BIT := ‘0’

IF set = ‘1’ THEN

ELSEIF rst = ‘1’ THEN

ELSEIF clk = -‘1’ AND clk’EVENT THEN

END IF;

(sq_delay + rq_delay +

qb <= NOT state AFTER

cq_delay)/3; END PROCESS dff;



process statement part

process statem

ent


PROCESS STATEMENT

• Postponed process • Wait until the last event in a real time increment • Signal assignments can become postponed

clk

set

rst

dff : PROCESS(rst, set, clk) BEGIN . . . END;

dff : POSTPONED PROCESS(rst, set, clk) BEGIN . . . END;

becomes active becomes active

t1+1δδ

t1+2δδ

t1+3δδ

PROCESS STATEMENT

PACKAGE bt IS TYPE bit_time IS RECORD state : BIT; delay : TIME; END RECORD; SHARED VARIABLE sd : bit_time := ('0', 0 NS); END PACKAGE bt; -- USE WORK.bt.ALL; ENTITY d_sr_flipflop IS GENERIC (sq_delay, rq_delay, cq_delay : TIME := 6 NS); PORT (d, set, rst, clk : IN BIT; q, qb : OUT BIT); BEGIN dff: PROCESS (rst, set, clk) BEGIN IF set = '1' THEN sd := ('1', sq_delay); ELSIF rst = '1' THEN sd := ('0', rq_delay); ELSIF clk = '1' AND clk'EVENT THEN sd := (d, cq_delay); END IF; END PROCESS dff; END ENTITY; -- ARCHITECTURE behavioral OF d_sr_flipflop IS BEGIN dff_arch: PROCESS (rst, set, clk) BEGIN q <= sd.state AFTER sd.delay; qb <= NOT sd.state AFTER sd.delay; END PROCESS dff_arch; END behavioral;

• A passive process statement may appear in the entity statement part

• Cannot make assignments to signals • This models the same flip-flop


PROCESS STATEMENT

long_runing : LOOP . . . IF x = 25 THEN EXIT; END IF; . . . END LOOP long_runing;

• Loop is a sequential statement • Example runs forever unless exited • EXIT & NEXT control flow of loops • EXIT & NEXT can be conditioned

NEXT loop_label WHEN condition;

EXIT WHEN condition;

PROCESS STATEMENT loop_1 : FOR i IN 5 TO 25 LOOP . . . sequential_statement_1; . . . sequential_statement_2; . . . loop_2 : WHILE j <= 90 LOOP . . . sequential_statement_3; sequential_statement_4; . . . NEXT loop_1 WHEN condition_1; . . . sequential_statement_5; sequential_statement_6; . . . END LOOP loop_2; . . . END LOOP loop_1;

• Conditional Next Statements in a Loop • FOR, WHILE are controlled forms of loop • Can still use NEXT and EXIT • The above NEXT statement causes looping to continue with

statements 1


ASSERTION STATEMENT

ASSERT assertion_condition REPORT "reporting_message" SEVERITY severity_level;

MAKE SURE THAT assertion_condition IS TRUE, OTHERWISE REPORT "reporting_message"

AND TAKE THE ACTION AT THIS severity_level;

MAKE SURE THAT false IS TRUE, OTHERWISE REPORT "reporting_message";

REPORT “reporting_message” SEVERITY severity_level;

• Use assert to flag violations • Use assert to report events • Can be sequential or concurrent • Severity: FAILURE ERROR WARNING NOTE

ASSERTION STATEMENT ARCHITECTURE behavioral OF d_sr_flipflop IS SIGNAL state : BIT := '0'; BEGIN dff: PROCESS (rst, set, clk) BEGIN ASSERT (NOT (set = '1' AND rst = '1')) REPORT "set and rst are both 1" SEVERITY NOTE; IF set = '1' THEN state <= '1' AFTER sq_delay; ELSIF rst = '1' THEN state <= '0' AFTER rq_delay; ELSIF clk = '1' AND clk'EVENT THEN state <= d AFTER cq_delay; END IF; END PROCESS dff; q <= state; qb <= NOT state; END behavioral;

• Conditions are checked only when process is activated • Make sure that set='1' AND rst='1' does not happen • Severity NOTE issues message


Good conditions

Violation of good conditions

Level;

ASSERTION STATEMENT

ASSERT

REPORT

SEVERITY

ASSERT NOT things_that_should_not_happen REPORT

a_message_that_bad_things_have_happened SEVIRITY action_to_take;

• Good conditions may be too many to list • Good conditions = NOT (Bad conditions) • Easier to use NOT of unwanted cases


ASSERTION STATEMENT

clock

data

setuptime

holdtime

• Use ASSERT to check setup and hold • ASSERT set_up_violation check REPORT... • ASSERT hold_violation check REPORT...

Setup and Hold time checks use assert statement and signal attributes


ASSERTION STATEMENT

clock

data

setuptime

holdtime

• When the clock changes, check for stable data • Check is placed after clock changes

When (clock changes from zero to 1),

if (data input has not been stable at least for the amount of the setup time),

then a setup time violation has occurred.

Setup Check in English

(clock = '1' AND NOT clock'STABLE)

AND

(NOT data'STABLE (setup_time))

Setup Check in VHDL


ASSERTION STATEMENT

clock

data

setuptime

holdtime

• When data changes while clock is '1', check for stable clock • Check is placed after data changes

When (there is a change on the data input)

if the (logic value on the clock is '1')

and the (clock has got a new value more recent than the amount of hold time),

then hold time violation has occurred.

Hold Check in English

(data'EVENT)

AND

(clock = '1')

AND

(NOT clock'STABLE (hold_time))

Hold Check in VHDL

ASSERTION STATEMENT

ENTITY d_sr_flipflop IS GENERIC (sq_delay, rq_delay, cq_delay : TIME := 6 NS; setup, hold : TIME := 4 NS); PORT (d, set, rst, clk : IN BIT; q, qb : OUT BIT); BEGIN ASSERT (NOT (clk = '1' AND clk'EVENT AND NOT d'STABLE(setup) )) REPORT "setup time violation" SEVERITY WARNING; ASSERT (NOT (d'EVENT AND clk = '1' AND NOT clk'STABLE(hold) )) REPORT "Hold time violation" SEVERITY WARNING; END d_sr_flipflop; -- ARCHITECTURE behavioral OF d_sr_flipflop IS SIGNAL state : BIT := '0'; BEGIN dff: PROCESS (rst, set, clk) BEGIN ASSERT (NOT (set = '1' AND rst = '1')) REPORT "set and rst are both 1" SEVERITY NOTE; IF set = '1' THEN state <= '1' AFTER sq_delay; ELSIF rst = '1' THEN state <= '0' AFTER rq_delay; ELSIF clk = '1' AND clk'EVENT THEN state <= d AFTER cq_delay; END IF; END PROCESS dff; q <= state; qb <= NOT state; END behavioral;

• Using assertion statements for illegal Set-Reset combinations • Setup and Hold time violations • Concurrent and sequential assertion statements


SEQUENTIAL WAIT STATEMENTS

WAIT statements for flow control of sequential statements

• Sequential statements; Used for handshaking and delay modeling • WAIT FOR real_time; • WAIT FOR; --"a long time" • WAIT ON (event on a signal); • WAIT UNTIL event makes condition true; • WAIT; --"forever"

WAIT FOR waiting_time; WAIT ON waiting_sensitivity_list; WAIT UNTIL waiting_condition; WAIT; WAIT FOR 0 NS; WAIT ON some_event UNTIL a_condition FOR some_time; WAIT UNTIL a_signal_is_true; Is the same as WAIT ON a_signal UNTIL signal_is_true; WAIT UNTIL expression_with_signal_and_variable_is_true; Is the same as WAIT ON the_signal UNTIL expression_is_true;



ARCHITECTURE … ARCHITECTURE … … … BEGIN BEGIN … … PROCESS PROCESS (a, b, c) . . . . . . BEGIN BEGIN … … … … … … WAIT ON (a, b, c); … END PROCESS; END PROCESS; END ARCHITECTURE; END ARCHITECTURE;

A process with sensitivity behaves as A process with WAIT ON at the end

• WAIT ON at the end is equivalent to using sensitivity list • Cannot use WAIT in a process with sensitivity list • WAIT suspends a Process



• A Moore 1011 detector • Can use WAIT in a Process statement

Several examples will demonstrate WAIT statements in processes

ENTITY moore_detector IS PORT (x, clk : IN BIT; z : OUT BIT); END moore_detector; -- ARCHITECTURE behavioral_state_machine OF moore_detector IS TYPE state IS (reset, got1, got10, got101, got1011); SIGNAL current : state := reset; BEGIN PROCESS BEGIN CASE current IS WHEN reset => WAIT UNTIL clk = '1'; IF x = '1' THEN current <= got1; ELSE current <= reset; END IF; WHEN got1 => WAIT UNTIL clk = '1'; IF x = '0' THEN current <= got10; ELSE current <= got1; END IF; WHEN got10 => WAIT UNTIL clk = '1'; IF x = '1' THEN current <= got101; ELSE current <= reset; END IF; WHEN got101 => WAIT UNTIL clk = '1'; IF x = '1' THEN current <= got1011; ELSE current <= got10; END IF; WHEN got1011 => z <= '1'; WAIT UNTIL clk = '1'; IF x = '1' THEN current <= got1; ELSE current <= got10; END IF; END CASE; WAIT FOR 1 NS; z <= '0'; END PROCESS; END behavioral_state_machine;

• VHDL Description of the 1011 Sequence Detector • Using Process and Wait Statements • Each choice corresponds to a state • Each state can be independently timed, and clocked

ENTITY moore_detector IS PORT (x, clk : IN BIT; z : OUT BIT); END moore_detector; -- ARCHITECTURE behavioral_state_machine OF moore_detector IS TYPE state IS (reset, got1, got10, got101, got1011); SIGNAL current : state := reset; BEGIN PROCESS BEGIN CASE current IS . . . WHEN got1 =>

WAIT UNTIL clk = '1'; IF x = '0' THEN current <= got10; ELSE current <= got1; END IF; . . . END CASE;

WAIT FOR 1 NS; z <= '0'; END PROCESS; END behavioral_state_machine;

• WAIT for rising edge of clk • Assign new state to current • Wait for transaction on current • Can use WAIT ON current 'TRANSACTION instead • Timing check flexibility in each state

SEQUENTIAL WAIT STATEMENTS ENTITY moore_detector IS PORT (x, clk : IN BIT; z : OUT BIT); END moore_detector; -- ARCHITECTURE behavioral_state_machine OF moore_detector IS TYPE state IS (reset, got1, got10, got101, got1011); SIGNAL current : state := reset; BEGIN PROCESS (clk) BEGIN IF clk = '1' THEN CASE current IS WHEN reset => IF x = '1' THEN current <= got1; ELSE current <= reset; END IF; WHEN got1 => IF x = '0' THEN current <= got10; ELSE current <= got1; END IF; WHEN got10 => IF x = '1' THEN current <= got101; ELSE current <= reset; END IF; WHEN got101 => IF x = '1' THEN current <= got1011; ELSE current <= got10; END IF; WHEN got1011 => IF x = '1' THEN current <= got1; ELSE current <= got10; END IF; END CASE; END IF; END PROCESS; z <= '1' WHEN current = got1011 ELSE '0'; END behavioral_state_machine;

• A simple state machine description • Not much timing flexibility • Allows a single clock • But easy and covers most cases



Logic

outputsnextstate

presentstate

REG

• Mealy machine detecting 101 • Use a style that separates logic and register parts • Also use an asynchronous reset

ENTITY asynch_reset_detector IS PORT (x, r, clk : IN BIT; z : OUT BIT); END ENTITY; -- ARCHITECTURE behavioral OF asynch_reset_detector IS TYPE state IS (a, b, c); SIGNAL nxt, present : state; BEGIN reg : PROCESS (clk, r) BEGIN IF r = '1' THEN present <= a; ELSIF (clk'EVENT AND clk = '1') THEN present <= nxt; END IF; END PROCESS; -- logic : PROCESS (present, x) BEGIN z <= '0'; CASE present IS WHEN a => IF x = '0' THEN nxt <= a; ELSE nxt <= b; END IF; WHEN b => IF x = '0' THEN nxt <= c; ELSE nxt <= b; END IF; WHEN c => IF x = '0' THEN nxt <= a; ELSE nxt <= b; END IF; END CASE; IF present = c AND x = '1' THEN z <= '1'; END IF; END PROCESS; END behavioral;

• VHDL description for a state machine with asynchronous reset • Most synthesis tools accept this style • Flexible in register part control

SEQUENTIAL WAIT STATEMENTS ... phase2: PROCESS BEGIN WAIT UNTIL c1 = '0'; WAIT FOR 10 NS; c2 <= '1'; WAIT FOR 480 NS; c2 <= '0'; END PROCESS phase2; ...

Time

c1

c2

10NS

10NS

0.5 1.0 1.5 2.0 US

• Generation of the second phase of a two phase non-overlapping clocking

• c2 is generated by phase2 process

Process Data

accepted

system B

valid data

data_ready

data_lines

system A

System A: -- start the following when ready to send data_lines <= newly_prepared_data; data_ready <= '1'; WAIT UNTIL accepted = '1'; data_ready <= '0'; --can use data_lines for other purposes System B: -- start the following when ready to accept data WAIT UNTIL data_ready = '1'; accepted <= '1'; -- start processing the newly received data WAIT UNTIL data_ready = '0'; accepted <= '0';

• Systems A & B talk • A prepares data, B accepts data • B releases A when data is picked



SYSTEM I

A B

in_data

in_ready

in_receivedout_data

out_ready

out_received

4

16

• Use handshaking mechanism in an interface • A prepares 4 bit data, B needs 16 bit data • Create interface system I • Talk to A to get data, talk to B to put data


SEQUENTIAL WAIT STATEMENTS ENTITY system_i IS PORT (in_data : IN BIT_VECTOR (3 DOWNTO 0); out_data : OUT BIT_VECTOR (15 DOWNTO 0); in_ready, out_received : IN BIT; in_received, out_ready : OUT BIT); END system_i; -- ARCHITECTURE waiting OF system_i IS SIGNAL buffer_full, buffer_picked : BIT := '0'; SIGNAL word_buffer : BIT_VECTOR (15 DOWNTO 0); BEGIN a_talk: PROCESS BEGIN . . .

-- Talk to A, collect 4 4-bit data, keep a count -- When ready, pass 16-bit data to b_talk

. . . END PROCESS a_talk; b_talk: PROCESS BEGIN . . .

-- Wait for 16-bit data from a_talk -- When data is received, send to B using proper handshaking

. . . END PROCESS b_talk; END waiting;

• a_talk process & b_talk process also talk to each other • Use buffer_full, buffer_picked, and word_buffer for a_talk and

b_talk communication

SEQUENTIAL WAIT STATEMENTS a_talk: PROCESS VARIABLE count : INTEGER RANGE 0 TO 4 := 0; BEGIN WAIT UNTIL in_ready = '1'; count := count + 1; CASE count IS WHEN 0 => NULL; WHEN 1 => word_buffer (03 DOWNTO 00) <= in_data; WHEN 2 => word_buffer (07 DOWNTO 04) <= in_data; WHEN 3 => word_buffer (11 DOWNTO 08) <= in_data; WHEN 4 => word_buffer (15 DOWNTO 12) <= in_data; buffer_full <= '1'; WAIT UNTIL buffer_picked = '1'; buffer_full <= '0'; count := 0; END CASE; in_received <= '1'; WAIT UNTIL in_ready = '0'; in_received <= '0'; END PROCESS a_talk; b_talk: PROCESS BEGIN IF buffer_full = '0' THEN WAIT UNTIL buffer_full = '1'; END IF; out_data <= word_buffer; buffer_picked <= '1'; WAIT UNTIL buffer_full = '0'; buffer_picked <= '0'; out_ready <= '1'; WAIT UNTIL out_received = '1'; out_ready <= '0'; END PROCESS b_talk;

• a_talk gets data from A and talks to b_talk • b_talk talks to a_talk and sends data to B



Arbiter

clock

requ

est0

gran

t0

requ

est1

requ

est2

requ

est3

gran

t1

gran

t2

gran

t3

• Bus arbiter interface • Simplified for this first example • Synchronized arbitration • A request input stays asserted until granted • A request input is granted only one clock cycle of bus use

ENTITY arbiter IS PORT (request : IN BIT_VECTOR (3 DOWNTO 0); grant : BUFFER BIT_VECTOR (3 DOWNTO 0); clock : IN BIT); END arbiter; -- ARCHITECTURE behavioral OF arbiter IS BEGIN wait_cycle: PROCESS BEGIN IF clock = '0' THEN WAIT FOR 20 NS; FOR i IN request'RANGE LOOP IF request(i) = '1' THEN grant <= "0000"; grant (i) <= '1'; ELSE grant (i) <= '0'; END IF; END LOOP; END IF; WAIT ON clock; END PROCESS wait_cycle; END behavioral;

• Bus arbiter description • Check all requests after the falling edge of the clock • Because of the 20 NS wait, process sensitivity cannot be used

ENTITY arbtest IS END arbtest; -- ARCHITECTURE io OF arbtest IS SIGNAL clk : BIT; SIGNAL r, g : BIT_VECTOR (3 DOWNTO 0); CONSTANT t : TIME := 1 US; TYPE time_array IS ARRAY (3 DOWNTO 0) OF TIME; CONSTANT delays : time_array := (4 US, 3 US, 15 US, 8 US); BEGIN arb : ENTITY WORK.arbiter PORT MAP (r, g, clk); clk <= NOT clk AFTER t / 2 WHEN NOW < 40 US ELSE clk; sources : FOR i IN r'RANGE GENERATE PROCESS BEGIN WAIT FOR delays (i); r(i) <= '1'; WAIT UNTIL g(i) = '1'; WAIT UNTIL clk = '0'; r(i) <= '0'; END PROCESS; END GENERATE; END io;

• Testing the arbiter • Four processes for generating data are generated • The time_array constant specifies timing requests coming from a

source



S2P

8

serial

rece

ived

data

read

y

fram

e_er

ror

over

run

para

llel_

out

• Another example using WAIT statements • Serial_to_parallel interface • RS232 frame with one start bit and one stop bit • Framing error, if stop bit is not seen • Overrun error if start bit appears too soon

A 10 bit frame

start bit data bits stop bit

reading begins

collect : PROCESS VARIABLE buff : qit_vector (7 DOWNTO 0); CONSTANT half_bit : TIME := (1E6/REAL(bps))/2.0 * 1 US; CONSTANT full_bit : TIME := (1E6/REAL(bps)) * 1 US; BEGIN WAIT UNTIL serial = '0'; WAIT FOR half_bit; FOR count IN 0 TO 7 LOOP WAIT FOR full_bit; buff (count) := serial; END LOOP; WAIT FOR full_bit; IF serial = '0' THEN frame_error <= '1'; WAIT UNTIL serial = '1'; ELSE frame_error <= '0'; dataready <= '1'; parallel_out <= buff; WAIT UNTIL received = '1'; WAIT UNTIL received = '0'; dataready <= '0'; END IF; END PROCESS collect;

too_fast : PROCESS BEGIN IF dataready = '1' THEN WAIT UNTIL serial = '0'; IF dataready = '1' THEN overrun <= '1'; END IF; ELSE overrun <= '0'; END IF; WAIT ON dataready; END PROCESS too_fast;


ENTITY serial2parallel IS GENERIC (bps : INTEGER); PORT (serial, received : IN qit; dataready : BUFFER qit; overrun, frame_error : OUT qit; parallel_out : BUFFER qit_vector (7 DOWNTO 0)); END serial2parallel; -- ARCHITECTURE waiting OF serial2parallel IS BEGIN --

END waiting;

• Serial2parallel VHDL description • Two concurrent processes • One waits for prepared data to be picked up (collect), while • The other waits for untimely serial data to arrive (too_fast) • WAIT statements are used in both processes


FORMATTED ASCII I/O OPERATIONS

TEXTIO package is in the STD library

TEXTIO contains:

LINE type, a pointer to STRING

TEXT file type, of CHARACTER type

INPUT, OUTPUT files for standard device IO

READLINE procedure, to read a line from file

READ procedure, to read data from a line a line

WRITE procedure, to write data into a

WRITELINE procedure, to write line to file

READ procedure, to read data from a line a line

ENDFILE function, to check the end of a file

• Only CHARACTERS are handled • All predefined standard types are converted to CHARACTERS • Subprograms are overloaded for all standard types

Examples will demonstrate TEXTIO package and its applications



VARIALE I : LINE; FILE f : TEXT;

FILE f : TEXT IS “input.txt”; FILE f : TEXT OPEN READ_MODE IS “input.txt”;

FILE_OPEN (f, “input.txt”, READ_MODE); FILE_OPEN (f, “output.txt”, WRITE_MODE); FILE_OPEN (f, “output.txt”, APPEND_MODE); FILE_CLOSE (f); READLINE(f, l); -- read a line of file f into buffer l

READ(l, v, ...); -- reads a value v of its type from l WRITE(l, v, ...) -- writes the value v to LINE l WRITELINE(f, l) -- writes l to file f ENDFILE(f) -- returns TRUE if the end of f

• READ and WRITE procedures are valid for: BIT, BIT_VECTOR, BOOLEAN, CHARACTER, INTEGER, REAL, STRING, and TIME

• Other parameters of these procedures include orientation, size, and unit if v is of type TIME

USE STD.TEXTIO.ALL; ... TYPE state IS (reset, got1, got10, got101); TYPE state_vector IS ARRAY (NATURAL RANGE <>) OF state; FUNCTION one_of (sources : state_vector) RETURN state IS VARIABLE l : LINE; FILE flush : TEXT OPEN WRITE_MODE IS "/dev/tty"; BEGIN FOR i IN sources'RANGE LOOP WRITE (l, state'IMAGE(sources(i)), LEFT, 7); END LOOP; WRITELINE (flush, l); RETURN sources(sources'LEFT); END one_of;

• A resolution function that writes its active drivers each time it is called

• New code is highlighted • Unix device tty is the standard output • Can use OUTPUT, defined in VHDL for the standard output • INPUT and OUTPUT work in all operating systems



PROCEDURE display (SIGNAL value1, value2 : BIT) IS FILE flush : TEXT OPEN WRITE_MODE IS "/dev/tty"; VARIABLE filler : STRING (1 TO 3) := " .."; VARIABLE l : LINE; BEGIN WRITE (l, NOW, RIGHT, 8, NS); IF value1'EVENT AND value2'EVENT THEN WRITE (l, value1, RIGHT, 3); WRITE (l, value2, RIGHT, 3); ELSIF value1'EVENT THEN WRITE (l, value1, RIGHT, 3); WRITE (l, filler, LEFT, 0); ELSE WRITE (l, filler, LEFT, 0); WRITE (l, value2, RIGHT, 3); END IF; WRITELINE (flush, l); END display;

• A display procedure for writing time and events • New values are listed • Filler is used for signal values that do not change

USE STD.TEXTIO.ALL; ENTITY two_phase_clock IS END two_phase_clock; -- ARCHITECTURE input_output OF two_phase_clock IS SIGNAL c1 : BIT := '1'; SIGNAL c2 : BIT := '0'; BEGIN display (c1, c2); END input_output;

• Call the display procedure anytime a clock phase changes • This procedure is also called once at the beginning of simulation

PROCEDURE display (SIGNAL value1, value2 : BIT) IS FILE flush : TEXT OPEN WRITE_MODE IS "/dev/tty"; VARIABLE filler : STRING (1 TO 3) := " .."; VARIABLE l : LINE; BEGIN WRITE (l, NOW, RIGHT, 8, NS); IF value1'EVENT AND value2'EVENT THEN WRITE (l, value1, RIGHT, 3); WRITE (l, value2, RIGHT, 3); ELSIF value1'EVENT THEN WRITE (l, value1, RIGHT, 3); WRITE (l, filler, LEFT, 0); ELSE WRITE (l, filler, LEFT, 0); WRITE (l, value2, RIGHT, 3); END IF; WRITELINE (flush, l); END display;

c1 <= NOT c1 AFTER 500 NS WHEN NOW < 4 US ELSE c1; phase2: PROCESS BEGIN WAIT UNTIL c1 = '0'; WAIT FOR 10 NS; c2 <= '1'; WAIT FOR 480 NS; c2 <= '0'; END PROCESS phase2;



PACKAGE displaying IS PROCEDURE display (SIGNAL value1, value2 : BIT; FILE flush : TEXT); END displaying; -- PACKAGE BODY displaying IS PROCEDURE display (SIGNAL value1, value2 : BIT; FILE flush : TEXT) IS VARIABLE filler : STRING (1 TO 3) := " .."; VARIABLE l : LINE; BEGIN WRITE (l, NOW, RIGHT, 8, NS); IF value1'EVENT AND value2'EVENT THEN WRITE (l, value1, RIGHT, 3); WRITE (l, value2, RIGHT, 3); ELSIF value1'EVENT THEN WRITE (l, value1, RIGHT, 3); WRITE (l, filler, LEFT, 0); ELSE WRITE (l, filler, LEFT, 0); WRITE (l, value2, RIGHT, 3); END IF; WRITELINE (flush, l); END display; END displaying;

• A procedure for writing in an already open file • A file of type TEXT is passed to this procedure • This goes in our new displaying package

FORMATTED ASCII I/O OPERATIONS USE STD.TEXTIO.ALL; USE WORK.displaying.ALL; ENTITY two_phase_clock IS END two_phase_clock; -- ARCHITECTURE input_output OF two_phase_clock IS SIGNAL c1 : BIT := '1'; SIGNAL c2 : BIT := '0'; FILE data : TEXT OPEN WRITE_MODE IS "clock.out"; BEGIN display (c1, c2, data); END input_output;

• Passing an open file to a procedure • File declaration takes place in the declarative part of an

architecture • File remains open after being written into • Writing can continue elsewhere

c1 <= NOT c1 AFTER 500 NS WHEN NOW < 4 US ELSE c1;phase2: PROCESS BEGIN WAIT UNTIL c1 = '0'; WAIT FOR 10 NS; c2 <= '1'; WAIT FOR 480 NS; c2 <= '0'; END PROCESS phase2;

USE STD.TEXTIO.ALL; PACKAGE displaying IS PROCEDURE display (SIGNAL value1, value2 : BIT; FILE flush : TEXT); END displaying; -- PACKAGE BODY displaying IS PROCEDURE display (SIGNAL value1, value2 : BIT; FILE flush : TEXT) IS . . . END display; END displaying;



0 ns .. 0 500 ns 0 .. 510 ns .. 1 990 ns .. 0 1000 ns 1 .. 1500 ns 0 .. 1510 ns .. 1 1990 ns .. 0 2000 ns 1 .. 2500 ns 0 .. 2510 ns .. 1 2990 ns .. 0 3000 ns 1 .. 3500 ns 0 .. 3510 ns .. 1 3990 ns .. 0 4000 ns 1 ..

• Output file generated by the input_output architecture • File closes at the end of simulation

USE STD.TEXTIO.ALL; ENTITY two_phase_clock IS END two_phase_clock; -- ARCHITECTURE input_output OF two_phase_clock IS SIGNAL c1 : BIT := '1'; SIGNAL c2 : BIT := '0'; SIGNAL print_tick : BIT := '0'; CONSTANT print_resolution : TIME := 5 NS; BEGIN print_tick <= NOT print_tick AFTER print_resolution WHEN NOW <= 2 US ELSE UNAFFECTED;

writing: PROCESS (print_tick, c1, c2) FILE flush : TEXT OPEN WRITE_MODE IS "clock4.out"; VARIABLE header : STRING (1 TO 18) := " c1 c2 "; VARIABLE l : LINE;

BEGIN IF NOW = 0 US THEN WRITE (l, header, LEFT, 0); WRITELINE (flush, l); END IF; WRITE (l, NOW, RIGHT, 8, NS); append_wave_slice (c1); append_wave_slice (c2); WRITELINE (flush, l); END PROCESS writing; END input_output;

• Generating an ASCII plot file • 5 NS print resolution reports of the two-phase clock description • Process wakes up, calls the append_wave_slice procedure • Buffer l is visible in the procedure, appending is done to this line

c1 <= NOT c1 AFTER 500 NS WHEN NOW < 4 US ELSE c1; phase2: PROCESS BEGIN WAIT UNTIL c1 = '0'; WAIT FOR 10 NS; c2 <= '1'; WAIT FOR 480 NS; c2 <= '0'; END PROCESS phase2;

PROCEDURE append_wave_slice (SIGNAL s : BIT) IS VARIABLE lo_value : STRING (1 TO 3) := "| "; VARIABLE hi_value : STRING (1 TO 3) := " |"; VARIABLE lo_to_hi : STRING (1 TO 3) := ".-+"; VARIABLE hi_to_lo : STRING (1 TO 3) := "+-."; BEGIN IF s'LAST_EVENT < print_resolution AND s'LAST_VALUE /= s THEN IF s = '1' THEN WRITE (l, lo_to_hi, RIGHT, 5); ELSE WRITE (l, hi_to_lo, RIGHT, 5); END IF; ELSE IF s = '1' THEN WRITE (l, hi_value, RIGHT, 5); ELSE WRITE (l, lo_value, RIGHT, 5); END IF; END IF; END PROCEDURE append_wave_slice;



• Plot generated by the ploting process • Plotting is activated every 5 NS • Write " |" for '1'; "| " for '0' • Write "+-." for 1 to 0 • Write ".-+" for 0 to 1

c1 c2 ... 480 ns | | 485 ns | | 490 ns | | 495 ns | | 500 ns +-. | 505 ns | | 510 ns | | 510 ns | .-+ 515 ns | | 520 ns | | 525 ns | |


MSI BASED DESIGN

sequentialcomparator

data_in

clk

clear_bar

load_bar

count_in

count8

4

4

Produces modulo-16 count of consecutive matching data

• Sequential comparator circuit • Design based on MSI parts • 74LS377, 74LS85, 74LS163 • Assume these parts are available

Closing the chapter, will present a top-down design with MSI parts


MSI BASED DESIGN

sequential comparator

8-bitregister

8-bitcomparator

4-bitcounter

4-bitcomparator

4-bitcomparator

• Partition the circuit into smaller components • Partition until library components or synthesizable parts are

reached • Will use top-down technique in designing a CPU in Chapter 10

MSI BASED DESIGN

[1]

[2]

[4]

[8]

CTRDIV165CT=0

M1

1, 5D

3CT=15

74LS163

M2G3G4

C5/2,3,4+

74LS85

<=>

P

Q

P < QP = QP > Q

GI

1C2

2D

74LS377

• Standard MSI parts • Register, comparator, counter

MSI BASED DESIGN USE WORK.basic_utilities.ALL; ENTITY ls85_comparator IS GENERIC (prop_delay : TIME := 10 NS); PORT (a, b : IN qit_vector (3 DOWNTO 0); gt, eq, lt : IN qit; a_gt_b, a_eq_b, a_lt_b : OUT qit); END ls85_comparator; -- ARCHITECTURE behavioral OF ls85_comparator IS BEGIN PROCESS (a, b, gt, eq, lt) BEGIN IF a > b THEN a_gt_b <= '1' AFTER prop_delay; a_eq_b <= '0' AFTER prop_delay; a_lt_b <= '0' AFTER prop_delay; ELSIF a < b THEN a_gt_b <= '0' AFTER prop_delay; a_eq_b <= '0' AFTER prop_delay; a_lt_b <= '1' AFTER prop_delay; ELSIF a = b THEN a_gt_b <= gt AFTER prop_delay; a_eq_b <= eq AFTER prop_delay; a_lt_b <= lt AFTER prop_delay; END IF; END PROCESS; END behavioral;

• 74LS85, four bit comparator • Relational operators, ordering for array operands • Default delays can be configured later

MSI BASED DESIGN USE WORK.basic_utilities.ALL; ENTITY ls377_register IS GENERIC (prop_delay : TIME := 7 NS); PORT (clk, g_bar : IN qit; d8 : IN qit_vector (7 DOWNTO 0); q8 : OUT qit_vector (7 DOWNTO 0)); END ls377_register; -- ARCHITECTURE dataflow OF ls377_register IS SIGNAL GUARD : BOOLEAN; BEGIN GUARD <= NOT clk'STABLE AND clk = '1' AND (g_bar = '0'); q8 <= GUARDED d8 AFTER prop_delay; END dataflow;

• 74LS377, clocked register • Default delays can be used or reconfigured

MSI BASED DESIGN

USE WORK.basic_utilities.ALL; ENTITY ls163_counter IS GENERIC (prop_delay : TIME := 12 NS); PORT (clk, clr_bar, ld_bar, enp, ent : IN qit; abcd : IN qit_vector (3 DOWNTO 0); q_abcd : OUT qit_vector (3 DOWNTO 0); rco : OUT qit); END ls163_counter; -- ARCHITECTURE behavioral OF ls163_counter IS BEGIN counting : PROCESS (clk) VARIABLE internal_count : qit_vector (3 DOWNTO 0) := "0000"; BEGIN IF (clk = '1') THEN IF (clr_bar = '0') THEN internal_count := "0000"; ELSIF (ld_bar = '0') THEN internal_count := abcd; ELSIF (enp = '1' AND ent = '1') THEN internal_count := inc (internal_count); END IF; IF (internal_count = "1111" AND ent = ‘1’) THEN rco <= '1' AFTER prop_delay; ELSE rco <= '0'; END IF; q_abcd <= internal_count AFTER prop_delay; END IF; END PROCESS counting; END behavioral;

• 74LS163, four bit synchronous counter • Default delays can be overwritten


MSI BASED DESIGN

a_gt_bgt

eq

lt a_lt_b

a_eq_b

cmp_hi:comparator

a

b

a_gt_bgt

eq

lt a_lt_b

a_eq_b

cmp_lo:comparator

a

b

g_bar

clk

d8

load_bar

enp

ent

clk

clr_bar

q8

reg:d_register

abcd

rco

q_abcd

cnt:counter

count_in

clk

clear_bar

load_bar

data_in

count

LS163_counter(behavioral)standardLS377_register(behavioral)

sequential comparator(structural)

15NS 18NS 22NS

prop_delay

prop_delay

prop_delayprop_delay

8

8

4

4

4

4

4

4

LS85_comparator(behavioral)

• Design is based on available parts • Configure to use LS library, specify delay


MSI BASED DESIGN

USE WORK.basic_utilities.ALL; ENTITY sequential_comparator IS PORT (data_in : IN qit_vector (7 DOWNTO 0); clk, clear_bar, load_bar : IN qit; count_in : IN qit_vector (3 DOWNTO 0); count : OUT qit_vector (3 DOWNTO 0) ); BEGIN ASSERT NOT ((clk='0' AND NOT clk'STABLE) AND NOT clk'DELAYED'STABLE (1 US)) REPORT "Minimum Clock Width Violation" SEVERITY WARNING; END sequential_comparator; -- ARCHITECTURE structural OF sequential_comparator IS COMPONENT d_register PORT (clk, g_bar : IN qit; d8 : IN qit_vector (7 DOWNTO 0); q8 : OUT qit_vector (7 DOWNTO 0)); END COMPONENT; COMPONENT comparator PORT (a, b : IN qit_vector (3 DOWNTO 0); gt, eq, lt : IN qit; a_gt_b, a_eq_b, a_lt_b : OUT qit); END COMPONENT; COMPONENT counter PORT (clk, clr_bar, ld_bar, enp, ent : IN qit; abcd : IN qit_vector (3 DOWNTO 0); q_abcd : OUT qit_vector (3 DOWNTO 0); rco : OUT qit); END COMPONENT; SIGNAL gnd : qit := '0'; SIGNAL vdd : qit := '1'; SIGNAL old_data : qit_vector (7 DOWNTO 0); SIGNAL compare_out : qit; SIGNAL gt_i, eq_i, lt_i : qit; BEGIN reg: d_register PORT MAP (clk, gnd, data_in, old_data); cmp_lo: comparator PORT MAP (data_in (3 DOWNTO 0), old_data (3 DOWNTO 0), gnd, vdd, gnd, gt_i, eq_i, lt_i); cmp_hi: comparator PORT MAP (data_in (7 DOWNTO 4), old_data (7 DOWNTO 4), gt_i, eq_i, lt_i, OPEN, compare_out, OPEN); cnt: counter PORT MAP (clk, clear_bar, load_bar, vdd, compare_out, count_in, count, OPEN); END structural;

• Design is based on available parts • Assert statement in the entity declaration • Configure to use LS library, specify delay


MSI BASED DESIGN

USE WORK.ALL; CONFIGURATION standard OF sequential_comparator IS FOR structural FOR reg : d_register USE ENTITY WORK.ls377_register (dataflow) GENERIC MAP (prop_delay => 15 NS); END FOR; FOR ALL : comparator USE ENTITY WORK.ls85_comparator (behavioral) GENERIC MAP (prop_delay => 18 NS); END FOR; FOR cnt : counter USE ENTITY WORK.ls163_counter (behavioral) GENERIC MAP (prop_delay => 22 NS); END FOR; END FOR; END standard;

• Configuring the structural architecture of the sequential_comparator

• Configuration declaration binds to 74LS parts • Generic values overwrite those of the 74LS parts

MSI BASED DESIGN USE WORK.basic_utilities.ALL; ENTITY test_sequential_comparator IS

END test_sequential_comparator; -- ARCHITECTURE input_output OF test_sequential_comparator IS COMPONENT seq_comp PORT (data_in : IN qit_vector (7 DOWNTO 0); clk, clear_bar, load_bar : IN qit; count_in : IN qit_vector (3 DOWNTO 0); count : OUT qit_vector (3 DOWNTO 0) ); END COMPONENT; FOR mfi : seq_comp USE CONFIGURATION WORK.standard; SIGNAL data : qit_vector (7 DOWNTO 0); SIGNAL ck, cl_bar, ld_bar : qit; SIGNAL cnt : qit_vector (3 DOWNTO 0); SIGNAL cnt_out : qit_vector (3 DOWNTO 0); BEGIN ck <= NOT ck AFTER 2 US WHEN NOW <= 70 US ELSE ck; cl_bar <= '1', '0' AFTER 60 US; ld_bar <= '1', '0' AFTER 50 US, '1' AFTER 55 US; cnt <= "1111", "1011" AFTER 40 US, "0111" AFTER 55 US; data <= "00000000", "01110111" AFTER 3 US, "10101100" AFTER 5 US, "01010100" AFTER 25 US; mfi : seq_comp PORT MAP (data, ck, cl_bar, ld_bar, cnt, cnt_out); END input_output;

• Testbench verifies behavior • Configuration specification associates mfi: seq_comp with the

standard configuration declaration


SUMMARY

This chapter presented descriptions of hardware at the

behavioral level and discussed how a process statement

can be used to describe the main functionality of a

module. In the first part of the chapter, syntax and

semantics for various forms of this construct were

described. We then showed how process statements are

used to describe controlling hardware, handshaking, and

file I/O. Various forms of wait statements were

extensively used in these descriptions.

Although behavioral level constructs of VHDL provide

a convenient method of describing very complex

hardware, a hardware designer can completely describe

a digital circuit without having to use these constructs.

Behavioral descriptions can be read and understood by

non-technical managers and others who are not very

familiar with VHDL.



CHAPTER 10

CPU MODELING AND DESIGN

10.1 DEFINING A COMPREHENSIVE EXAMPLE 10.2 PARWAN CPU

10.2.1 Memory Organization of Parwan 10.2.2 Instruction Set 10.2.3 Instruction Format 10.2.4 Programming in Parwan Assembly

10.3 BEHAVIORAL DESCRIPTION OF PARWAN 10.3.1 Timing and Clocking 10.3.2 Packages 10.3.3 Interface Description of Parwan 10.3.4 Parwan Behavioral Architecture

10.4 PARWAN BUSSING STRUCTURE 10.4.1 Interconnection of Components 10.4.2 Global View of Parwan Components 10.4.3 Instruction Execution

10.5 DATAFLOW DESCRIPTION OF PARWAN 10.5.1 Data and Control Partitioning 10.5.2 Timing of Data and Control Events 10.5.3 General Description Methodology 10.5.4 Description of Components 10.5.5 Data Section of Parwan 10.5.6 Control Section of Parwan 10.5.7 Wiring Data and Control Sections

10.6 A TEST BENCH FOR THE PARWAN CPU 10.7 A MORE REALISTIC PARWAN

10.7.1 CPU Control Signals 10.7.2 Synthesizability 10.7.3 Hardware Modifications

10.8 SUMMARY


DEFINING A COMPREHENSIVE EXAMPLE

MAR

PC

IR

AC

ALU

SHU

Controller

SR

• General Layout of Parwan • PARWAN; PAR_1; A Reduced Processor • Simple 8-bit CPU; 8-bit Data; 12-bit Address • Primarily designed for educational purposes • Includes most common instructions

Will define a CPU describe it in VHDL, and show its hardware details


PARWAN CPU

Page Offset

1 0 9 81 1 0 0

7 6 5 40 0 0 0

3 2 1 00 0 0 0

7 6 5 4 3 2 1 0

page 0 . .

page 1 . .

page 2 . .

page 14 . .

page 15 . .

MEMORY:

0:00 - 0:FF

1:00 - 1:FF

2:00 - 2:FF

E:00 - E:FF

F:00 - F:FF

• Page and Offset Parts of Parwan addresses • Memory divided into pages • Pages of 256 bytes • Address has page and offset part • Uses memory mapped IO


PARWAN CPU

FULL Address; (12 bits) direct/indirect LDA, AND, ADD, SUB, JMP, STA PAGE Address, (8 bit) JSR, BRA_V, BRA_C, BRA_Z, BRA_N NO Address NOP, CLA, CMA, CMC, ASL, ASR

• Three groups of instructions • Full Address instructions include page and offset • Page address instructions include offset • No Address instructions occupy a single byte


• Summary of Parwan instructions. • Load and store operations • Arithmetic & logical operations • jmp and branch instructions

Instruction Mnemonic

Brief Description

Address Bits

Address Scheme

Indirect Address

Flags Use

Flags Set

LDA loc Load AC w/(loc) 12 FULL YES ---- --zn

AND loc AND AC w/(loc) 12 FULL YES ---- --zn

ADD loc Add (loc) to AC 12 FULL YES -c-- vczn

SUB loc Sub (loc) from AC 12 FULL YES -c-- vczn

JMP adr Jump to adr 12 FULL YES ---- ----

STA loc Store AC in loc 12 FULL YES ---- ----

JSR tos Subroutine to tos 8 PAGE NO ---- ----

BRA_V adr Branch to adr if V 8 PAGE NO v--- ----

BRA_C adr Branch to adr if C 8 PAGE NO -c-- ----

BRA_Z adr Branch to adr if Z 8 PAGE NO --z- ----

BRA_N adr Branch to adr if N 8 PAGE NO ---n ----

NOP No operation - NONE NO ---- ----

CLA Clear AC - NONE NO ---- ----

CMA Complement AC - NONE NO ---- --zn

CMC Complement carry - NONE NO -c-- -c--

ASL Arith shift left - NONE NO ---- vczn

ASR Arith shift right - NONE NO ---- --zn


PARWAN CPU

• Parwan instruction opcodes • CPU contains V C Z N flags • Instructions use and/or influence these flags

Instruction Mnemonic

Opcode Bits 7 6 5

D/I Bit 4

Bits 3 2 1 0

LDA loc 0 0 0 0/1 Page adr AND loc 0 0 1 0/1 Page adr ADD loc 0 1 0 0/1 Page adr SUB loc 0 1 1 0/1 Page adr JMP adr 1 0 0 0/1 Page adr STA loc 1 0 1 0/1 Page adr JSR tos 1 1 0 - - - - - BRA_V adr 1 1 1 1 1 0 0 0 BRA_C adr 1 1 1 1 0 1 0 0 BRA_Z adr 1 1 1 1 0 0 1 0 BRA_N adr 1 1 1 1 0 0 0 1 NOP 1 1 1 0 0 0 0 0 CLA 1 1 1 0 0 0 0 1 CMA 1 1 1 0 0 0 1 0 CMC 1 1 1 0 0 1 0 0 ASL 1 1 1 0 1 0 0 0 ASR 1 1 1 0 1 0 0 1


PARWAN CPU

V

C

Z

N

ADD, SUB, ASL

ADD, SUB, ASL, CMC

ADD, SUB, LDA, AND, CMA, ASL, ASR

ADD, SUB, LDA, AND, CMA, ASL, ASR

BRA_V

BRA_C, ADD, SUB, CMC

BRA_Z

BRA_N

influence use

• Arithmetic instructions influence all flags • Branch instructions use corresponding flags • Shift instructions influence all flags


pageopcpg: loc

pg: loc+1 offset

complete address

• Addressing in full-address instructions • Full address instructions use two bytes • Right hand side of first byte is page • Second byte contains offset • Bit 4 is direct/indirect [0/1] indicator


PARWAN CPU

pg: loc

pg: loc+1 offset

complete address

jsr or branch

• Addressing in page-address instructions • Page address instructions use two bytes • All of first byte is used by opcode • Page part of address uses current page • Second byte is the offset


PARWAN CPU

BRA_C

6A

MEMORY

1 1 1 1 0 1 0 0

6 A

...

...

5:0D

5:0E

5:0F

BRANCH TO 6A if carry is set c=0 : Next instruction from 5:0f c=1 : Next instruction from 5:6A

• Branching is done within current page only • A branch instruction


PARWAN CPU

MEMORY

PC-> 5:11

5:12

5:13

B E F O R E J S R

. . .JSR

3 3

INSTR AFTER JSR

0 0 0 0 0 0 0 0

SUBROUTINE CODE. . .

JMP Indirect3 3

. . .

. . .

5:33

5:34

5:55

. . .

5:56

5:57

MEMORY

5:11

5:12

5:13

A F T E R J S R

. . .JSR

3 3

INSTR AFTER JSR

1 3

SUBROUTINE CODE. . .

JMP Indirect3 3

. . .

5:33

PC-> 5:34

5:55

. . .

5:56

5:57

• An example for the execution of jsr • Memory and pc, before and after jsr • Store jsr return address at tos • Begin subroutine at tos+1 • Use indirect jmp to tos for return from subroutine


PARWAN CPU

DataIndirect address Actual address

Any page and offset Same page

Indirecting effects offset

opc0:25

0:26

61

3 5

6:1F

6:35

operand

1 8

1 F

• An example for indirect addressing in Parwan. • Indirect addressing affects offset only • To obtain actual address full addressing is used • To obtain data page addressing is used


PARWAN CPU

-- load 25 in 4:00 -- load 10 in 4:01 -- load 01 in 4:02

0:15 cla -- clear accumulator 0:16 asl -- clears carry 0:17 add, i 4:00 -- add bytes 0:19 sta 4:03 -- store partial sum 0:1B lda 4:00 -- load pointer 0:1D add 4:02 -- increment pointer 0:1F sta 4:00 -- store pointer back 0:21 lda 4:01 -- load count 0:23 sub 4:02 -- decrement count 0:25 bra_z :2D -- end if zero count 0:27 sta 4:01 -- store count back 0:29 lda 4:03 -- get partial sum 0:2B jmp 0:17 -- go for next byte 0:2D nop -- adding completed

• An example program for Parwan CPU • A program to add 10 bytes • Use location 4:00 for data pointer • Use location 4:01 for counter • Constant 1 in 4:02 is used for +1 and -1


BEHAVIORAL DESCRIPTION OF PARWAN

LIBRARY cmos; USE cmos.basic_utilities.ALL; -- LIBRARY par_library; USE par_library.par_utilities.ALL; USE par_library.par_parameters.ALL; -- ENTITY par_central_processing_unit IS . . . END par_central_processing_unit;

--

ARCHITECTURE behavioral OF par_central_processing_unit IS BEGIN END behavioral;

• Packages used will be described • A single component will describe all of Parwan

Coding for the behavioral description of Parwan will be presented.



LIBRARY cmos; USE cmos.basic_utilities.ALL; -- PACKAGE par_utilities IS FUNCTION "XOR" (a, b : qit) RETURN qit ; FUNCTION "AND" (a, b : qit_vector) RETURN qit_vector; FUNCTION "OR" (a, b : qit_vector) RETURN qit_vector; FUNCTION "NOT" (a : qit_vector) RETURN qit_vector; -- SUBTYPE nibble IS qit_vector (3 DOWNTO 0); SUBTYPE byte IS qit_vector (7 DOWNTO 0); SUBTYPE twelve IS qit_vector (11 DOWNTO 0); -- SUBTYPE wired_nibble IS wired_qit_vector (3 DOWNTO 0); SUBTYPE wired_byte IS wired_qit_vector (7 DOWNTO 0); SUBTYPE wired_twelve IS wired_qit_vector (11 DOWNTO 0); -- SUBTYPE ored_nibble IS ored_qit_vector (3 DOWNTO 0); SUBTYPE ored_byte IS ored_qit_vector (7 DOWNTO 0); SUBTYPE ored_twelve IS ored_qit_vector (11 DOWNTO 0); -- CONSTANT zero_4 : nibble := "0000"; CONSTANT zero_8 : byte := "00000000"; CONSTANT zero_12 : twelve := "000000000000"; -- FUNCTION add_cv (a, b : qit_vector; cin : qit) RETURN qit_vector; FUNCTION sub_cv (a, b : qit_vector; cin : qit) RETURN qit_vector; -- FUNCTION set_if_zero (a : qit_vector) RETURN qit; -- END par_utilities;

• Declarations of par_utilities package of par_library • Machine descriptions require utilities • Use basic_utilities • Additional utilities are included in par_utilities



PACKAGE BODY par_utilities IS FUNCTION "XOR" (a, b : qit) RETURN qit IS CONSTANT qit_xor_table : qit_2d := ( ('0','1','1','X'), ('1','0','0','X'), ('1','0','0','X'), ('X','X','X','X')); BEGIN RETURN qit_xor_table (a, b); END "XOR"; FUNCTION "AND" (a,b : qit_vector) RETURN qit_vector IS VARIABLE r : qit_vector (a'RANGE); BEGIN loop1: FOR i IN a'RANGE LOOP r(i) := a(i) AND b(i); END LOOP loop1; RETURN r; END "AND"; -- FUNCTION "OR" (a,b: qit_vector) RETURN qit_vector IS VARIABLE r: qit_vector (a'RANGE); BEGIN loop1: FOR i IN a'RANGE LOOP r(i) := a(i) OR b(i); END LOOP loop1; RETURN r; END "OR"; -- FUNCTION "NOT" (a: qit_vector) RETURN qit_vector IS VARIABLE r: qit_vector (a'RANGE); BEGIN loop1: FOR i IN a'RANGE LOOP r(i) := NOT a(i); END LOOP loop1; RETURN r; END "NOT";

• Body of par_utilities package of par_library library • Define XOR in qit • Overload logical operators with qit_vector



FUNCTION add_cv (a, b : qit_vector; cin : qit) RETURN qit_vector IS VARIABLE r, c: qit_vector (a'LEFT + 2 DOWNTO 0); -- extra r bits : msb: overflow, next to msb: carry VARIABLE a_sign, b_sign: qit; BEGIN a_sign := a(a'LEFT); b_sign := b(b'LEFT); r(0) := a(0) XOR b(0) XOR cin; c(0) := ((a(0) XOR b(0)) AND cin) OR (a(0) AND b(0)); FOR i IN 1 TO (a'LEFT) LOOP r(i) := a(i) XOR b(i) XOR c(i-1); c(i) := ((a(i) XOR b(i)) AND c(i-1)) OR (a(i) AND b(i)); END LOOP; r(a'LEFT+1) := c(a'LEFT); IF a_sign = b_sign AND r(a'LEFT) /= a_sign THEN r(a'LEFT+2) := '1'; --overflow ELSE r(a'LEFT+2) := '0'; END IF; RETURN r; END add_cv; FUNCTION sub_cv (a, b : qit_vector; cin : qit) RETURN qit_vector IS VARIABLE not_b : qit_vector (b'LEFT DOWNTO 0); VARIABLE not_c : qit; VARIABLE r : qit_vector (a'LEFT + 2 DOWNTO 0); BEGIN not_b := NOT b; not_c := NOT cin; r := add_cv (a, not_b, not_c); RETURN r; END sub_cv; FUNCTION set_if_zero (a : qit_vector) RETURN qit IS VARIABLE zero : qit := '1'; BEGIN FOR i IN a'RANGE LOOP IF a(i) /= '0' THEN zero := '0'; EXIT; END IF; END LOOP; RETURN zero; END set_if_zero; END par_utilities;

• Body of the par_utilities package of par_library library • add_cv adds its operands creates c and v bits • Put overflow in leftmost result bit • Put carry to the right of overflow



LIBRARY cmos; USE cmos.basic_utilities.ALL; -- PACKAGE par_parameters IS CONSTANT single_byte_instructions : qit_vector (3 DOWNTO 0) := "1110"; CONSTANT cla : qit_vector (3 DOWNTO 0) := "0001"; CONSTANT cma : qit_vector (3 DOWNTO 0) := "0010"; CONSTANT cmc : qit_vector (3 DOWNTO 0) := "0100"; CONSTANT asl : qit_vector (3 DOWNTO 0) := "1000"; CONSTANT asr : qit_vector (3 DOWNTO 0) := "1001"; CONSTANT jsr : qit_vector (2 DOWNTO 0) := "110"; CONSTANT bra : qit_vector (3 DOWNTO 0) := "1111"; CONSTANT indirect : qit := '1'; CONSTANT jmp : qit_vector (2 DOWNTO 0) := "100"; CONSTANT sta : qit_vector (2 DOWNTO 0) := "101"; CONSTANT lda : qit_vector (2 DOWNTO 0) := "000"; CONSTANT ann : qit_vector (2 DOWNTO 0) := "001"; CONSTANT add : qit_vector (2 DOWNTO 0) := "010"; CONSTANT sbb : qit_vector (2 DOWNTO 0) := "011"; CONSTANT jsr_or_bra : qit_vector (1 DOWNTO 0) := "11"; END par_parameters;

• Declaration of par_parameters Package of par_library • Assign appropriate names to opcodes • par_parameters is used for readability



LIBRARY cmos; USE cmos.basic_utilities.ALL; -- LIBRARY par_library; USE par_library.par_utilities.ALL; USE par_library.par_parameters.ALL; -- ENTITY par_central_processing_unit IS GENERIC (read_high_time, read_low_time, write_high_time, write_low_time : TIME := 2 US; cycle_time : TIME := 4 US); PORT (clk : IN qit; interrupt : IN qit; read_mem, write_mem : OUT qit; databus : INOUT wired_byte BUS := "ZZZZZZZZ"; adbus : OUT twelve ); END par_central_processing_unit;

• Interface description of Parwan



ARCHITECTURE behavioral OF par_central_processing_unit IS BEGIN PROCESS Declare necessary variables; Figure 10.16. BEGIN IF interrupt = '1' THEN Handle interrupt; Figure 10.17. ELSE -- no interrupt Read first byte into byte1, increment pc; Figure 10.18. IF byte1 (7 DOWNTO 4) = single_byte_instructions THEN Execute single-byte instructions; Figure 10.19. ELSE -- two-byte instructions Read second byte into byte2, increment pc; Figure 10.20. IF byte1 (7 DOWNTO 5) = jsr THEN Execute jsr instruction, byte2 has address; Figure 10.21. ELSIF byte1 (7 DOWNTO 4) = bra THEN Execute bra instructions, address in byte2; Figure 10.22. ELSE -- all other two-byte instructions IF byte1 (4) = indirect THEN Use byte1 and byte2 to get address; Figure 10.23. END IF; -- ends indirect IF byte1 (7 DOWNTO 5) = jmp THEN Execute jmp instruction; Figure 10.24; ELSIF byte1 (7 DOWNTO 5) = sta THEN Execute sta instruction, write ac; Figure 10.25. ELSE -- read operand for lda, and, add, sub Read memory onto databus; Figure 10.26, top.

Execute lda, and, add, and sub; Figure 10.26, middle. Remove memory from databus; Figure 10.26, bottom.

END IF; -- jmp / sta / lda, and, add, sub END IF; -- jsr / bra / other double-byte instructions END IF; -- single-byte / double-byte END IF; -- interrupt / otherwise END PROCESS; END behavioral;

• Outline of the Behavioral Description of Parwan

VARIABLE pc : twelve; VARIABLE ac, byte1, byte2 : byte; VARIABLE v, c, z, n : qit; VARIABLE temp : qit_vector (9 DOWNTO 0);

• Variable declarations of Parwan behavioral model

pc := zero_12; WAIT FOR cycle_time;

• Interrupt handling of Parwan behavioral model

adbus <= pc; read_mem <= '1'; WAIT FOR read_high_time; byte1 := byte (databus); read_mem <= '0'; WAIT FOR read_low_time; pc := inc (pc);

• Reading the first byte from the memory, part of Parwan behavioral model

• Filling the outline of the behavioral description of Parwan • Declarations, Interrupt handling, Reading the first byte



CASE byte1 (3 DOWNTO 0) IS WHEN cla => ac := zero_8; WHEN cma => ac := NOT ac; IF ac = zero_8 THEN z := '1'; END IF; n := ac (7); WHEN cmc => c := NOT c; WHEN asl => c := ac (7); ac := ac (6 DOWNTO 0) & '0'; IF ac = zero_8 THEN z := ‘1’; END IF; n := ac (7); IF c /= n THEN v := '1'; END IF; WHEN asr => ac := ac (7) & ac (7 DOWNTO 1); IF ac = zero_8 THEN z := '1'; END IF; n := ac (7); WHEN OTHERS => NULL; END CASE;

• Executing single-byte instructions in the behavioral model of Parwan

• Using the least significant nibble for decoding instructions • Decoding instructions, cla, cma, cmc, asl, asr

adbus <= pc; read_mem <= '1'; WAIT FOR read_high_time; byte2 := byte (databus); read_mem <= '0'; WAIT FOR read_low_time; pc := inc (pc);

• Reading the second byte from the memory, part of Parwan behavioral model

databus <= wired_byte (pc (7 DOWNTO 0) ); adbus (7 DOWNTO 0) <= byte2; write_mem <= '1'; WAIT FOR write_high_time; write_mem <= '0'; WAIT FOR write_low_time; databus <= "ZZZZZZZZ"; pc (7 DOWNTO 0) := inc (byte2);

• Execution of the jsr instruction in the behavioral model of Parwan

• Filling the outline of the behavioral description of Parwan • Reading the second byte, Executing jsr

IF ( byte1 (3) = '1' AND v = '1' ) OR ( byte1 (2) = '1' AND c = '1' ) OR ( byte1 (1) = '1' AND z = '1' ) OR ( byte1 (0) = '1' AND n = '1' ) THEN pc (7 DOWNTO 0) := byte2; END IF;

• Execution of branch instructions in the behavioral model of Parwan

adbus (11 DOWNTO 8) <= byte1 (3 DOWNTO 0); adbus (7 DOWNTO 0) <= byte2; read_mem <= '1'; WAIT FOR read_high_time; byte2 := byte (databus); read_mem <= '0'; WAIT FOR read_low_time;

• Handling indirect addressing by the behavioral model of Parwan

• Filling the outline of the behavioral description of Parwan • Branch instruction, Handling indirect addressing

pc := byte1 (3 DOWNTO 0) & byte2;

• Execution of jmp instruction in the behavioral model of Parwan

adbus <= byte1 (3 DOWNTO 0) & byte2; databus <= wired_byte (ac); write_mem <= '1'; WAIT FOR write_high_time; write_mem <= '0'; WAIT FOR write_low_time; databus <= "ZZZZZZZZ";

• Execution of sta instruction in the behavioral model of Parwan

• Filling the outline of the behavioral description of Parwan • Handling jmp and sta instructions

BEHAVIORAL DESCRIPTION OF PARWAN adbus (11 DOWNTO 8) <= byte1 (3 DOWNTO 0); adbus (7 DOWNTO 0) <= byte2; read_mem <= '1'; WAIT FOR read_high_time; CASE byte1 (7 DOWNTO 5) IS WHEN lda => ac := byte (databus); WHEN ann => ac := ac AND byte (databus); WHEN add => temp := add_cv (ac, byte (databus), c); ac := temp (7 DOWNTO 0); c := temp (8); v := temp (9); WHEN sbb => temp := sub_cv (ac, byte (databus), c); ac := temp (7 DOWNTO 0); c := temp (8); v := temp (9); WHEN OTHERS => NULL; END CASE; IF ac = zero_8 THEN z := '1'; END IF; n := ac (7); read_mem <= '0'; WAIT FOR read_low_time;

• Execution of lda, and, add, and sub instructions in the behavioral model of Parwan


PARWAN BUSSING STRUCTURE

CONTROLLER

IR

ir_out

interruptwrite_mem

read_mem4

8

8DBUSobus_on_dbus

PC_PAGE PC_OFFSET

MAR_PAGE MAR_OFFSET

pc_out

mar_inp

mar_out

84

48

DATABUS

dbus_on_databus

databus_on_dbus 4096 byte memory

ADBUS 12

AC

8

alu_out

alu_flags 4

SR

4

SHU

8

ac_out

ALU

a_side b_side

8OBUS

mar_page_bus mar_offset_bus

. . .

ADBUS

• Bussing structure of Parwan



Component Type Bits AC Register 8 IR Register 8 PC Loadable Up Counter 12 MAR Register 12 SR Register 4 ALU Arithmetic Unit 8 SHU Shifter Logic 8

• Machine has 7 components • Behavioral description helps partitioning the circuit • Circuit components will be identified • Bussing specifies interconnection of these components


PARWAN BUSSING STRUCTURE LDA Instruction:

Cycle 1 Begin Fetch Pc_on_mar_page_bus, Pc_om_mar_offset_bus Load_mar_page Load_mar_offset Increment_pc

Cycle 2 Mar_on_adbus Read_memory Databus_on_adbus Alu_a_side_on_alu_output No_shift Load_ir

Cycle 3 Get Address Pc_on_mar_page_bus Pc_on_mar_offset_bus Load_mar_page Load_mar_offset Increment_pc

Cycle 4 Mar_on_adbus Read_memory Databus_on_dbus Dbus_on_mat_offset_bus Page_from_in_on_mar_page_bus Load_mar_page_bus Load_mar_offset_bus

Cycle 5 Get Operand, Load AC Mar_on_adbus Read_memory Databus_on_adbus Alu_a_side_on_alu_output No_shift Load_ac

Cycle 6 Next Fetch . . .

• Steps for execution of lda



CONTROLSECTION

DATA SECTION

Data Components and Buses

Data Signals

Control Signals

• Data and control sections of Parwan CPU • 31 control signals from the controller to the data unit


DATAFLOW DESCRIPTION OF PARWAN

• Inputs and outputs of Parwan control section • Signals for flow of data and data clocking

Applies

To

Category

Signal Name

Functionality

AC Register Control load_ac,

zero_ac

Loads ac

Resets ac

IR Register Control load_ir Loads ir

PC Register Control increment_pc,

load_page_pc,

load_offset_pc,

reset_pc

Increments pc

Loads page part of pc

Loads offset part of pc

Resets pc

MAR Register Control load_page_mar,

load_offset_mar

Loads page part of mar

Loads offset part of mar

SR Register Control load_sr,

cm_carry_sr

Loads sr

Complements carry flag of sr

MAR_BUS Bus Control pc_on_mar_page_bus,

ir_on_mar_page_bus,

pc_on_mar_offset_bus,

dbus_on_mar_offset_bus

Puts page part of pc on mar page bus

Puts 4 bits of ir on mar page bus

Puts offset part of pc on mar offset bus

Puts dbus on mar offset bus

DBUS Bus Control pc_offset_on_dbus,

obus_on_dbus,

databus_on_dbus

Puts offset part of pc on dbus

Puts obus on dbus

Puts external databus on internal dbus

ADBUS Bus Control mar_on_adbus Puts all of mar on adbus

DATABUS Bus Control dbus_on_databus Puts internal dbus on external databus

SHU Logic Units arith_shift_left,

arith_shift_right

Shifter shifts its input one place to the left

Shifter shifts its input one place to the right

ALU Logic Units alu_and,

alu_not,

alu_a,

alu_add,

alu_b,

alu_sub

Output of alu becomes and of its two inputs

Output of alu becomes complement of its b input

Output of alu becomes the same as its a input

alu perfporms add operation on its two inputs

Output of alu becomes the same as its b input

alu perfporms subtraction of its two inputs

Others I/O read_mem,

write_mem,

interrupt

Starts a memory read operation

Starts a memory write operation

Interrupts CPU



System Clock

Control Signal 1

Control Signal 2

Control signals remain asserted for a complete clock cycle

Allows logic unit propagation

Clock data and control at the same time

Clock data while control signals are still valid

• Timing of control signals • Assume falling edge trigger data and control



Id Opcode line Operation Flags 0 alu_and a AND b zn 1 alu_not NOT b zn 2 alu_a a zn 3 alu_add b PLUS a vczn 4 alu_b b zn 5 alu_sub b MINUS a vczn

• Operations and flags of alu • A control signal for each operation

Individual data components will be described in VHDL. Will also show hardware.



AB [0]

[1]

[2]

[3]

[4]

[5]

[6]

[7]

AB

AB

AB

AB

ABAB

AB

ALU0

2

VICIZINI

(3, 5) VO(3, 5) CO

(0, 1, 2, 3, 4, 5) ZO(0, 1, 2, 3, 4, 5) NO

1

345

-

+

a bi ialu_and

alu_not

alu_a

alu_add

alu_b

alu_sub

• Parwan alu • Logic symbol • One bit gate level hardware



LIBRARY cmos; USE cmos.basic_utilities.ALL; -- PACKAGE alu_operations IS CONSTANT a_and_b : qit_vector (5 DOWNTO 0) := "000001"; CONSTANT b_compl : qit_vector (5 DOWNTO 0) := "000010"; CONSTANT a_input : qit_vector (5 DOWNTO 0) := "000100"; CONSTANT a_add_b : qit_vector (5 DOWNTO 0) := "001000"; CONSTANT b_input : qit_vector (5 DOWNTO 0) := "010000"; CONSTANT a_sub_b : qit_vector (5 DOWNTO 0) := "100000"; END alu_operations;

• Package declaration for the alu_operations package • Simplify code and add readability

ENTITY arithmetic_logic_unit IS PORT (a_side, b_side : IN byte; alu_and, alu_not, alu_a, alu_add, alu_b, alu_sub : IN qit; in_flags : IN nibble; z_out : OUT byte; out_flags : OUT nibble); END arithmetic_logic_unit; -- ARCHITECTURE behavioral OF arithmetic_logic_unit IS BEGIN coding: PROCESS (a_side, b_side, alu_and, alu_not, alu_a, alu_add, alu_b, alu_sub) VARIABLE t : qit_vector (9 DOWNTO 0); VARIABLE v, c, z, n : qit; ALIAS n_flag_in : qit IS in_flags(0); ALIAS z_flag_in : qit IS in_flags(1); ALIAS c_flag_in : qit IS in_flags(2); ALIAS v_flag_in : qit IS in_flags(3); BEGIN CASE qit_vector (5 DOWNTO 0)’ (alu_sub, alu_b, alu_add, alu_a, alu_not, alu_and) IS WHEN a_add_b => t := add_cv (b_side, a_side, c_flag_in); c := t(8); v := t(9); -- other flags are set at the end WHEN a_sub_b => t := sub_cv (b_side, a_side, c_flag_in); c := t(8); v := t(9); WHEN a_and_b => t (7 DOWNTO 0) := a_side AND b_side; c := c_flag_in; v := v_flag_in; WHEN a_input => t (7 DOWNTO 0) := a_side; c := c_flag_in; v := v_flag_in; WHEN b_input => t (7 DOWNTO 0) := b_side; c := c_flag_in; v := v_flag_in; WHEN b_compl => t (7 DOWNTO 0) := NOT b_side; c := c_flag_in; v := v_flag_in; WHEN OTHERS => NULL; END CASE; n := t(7); z := set_if_zero (t (7 DOWNTO 0)); z_out <= t (7 DOWNTO 0); out_flags <= (v, c, z, n); END PROCESS coding; END behavioral;

• Behavioral description of arithmetic logic unit of Parwan



[0]

[1]

[2]

[3]

[4]

[5]

[6]

[7]

SHUL

VICIZINI

( L) VO(L) CO

(L, R) ZO(L, R) NO

R

Input

L R

i

i-1

i

i+1

Output

• Parwan shu • Logic symbol • One bit hardware

ENTITY shifter_unit IS PORT (alu_side : IN byte; arith_shift_left, arith_shift_right : IN qit; in_flags : IN nibble; obus_side : OUT byte; out_flags : OUT nibble); END shifter_unit; -- ARCHITECTURE behavioral OF shifter_unit IS BEGIN coding: PROCESS (alu_side, arith_shift_left, arith_shift_right) VARIABLE t : qit_vector (7 DOWNTO 0); VARIABLE v, c, z, n : qit; ALIAS n_flag_in : qit IS in_flags(0); ALIAS z_flag_in : qit IS in_flags(1); ALIAS c_flag_in : qit IS in_flags(2); ALIAS v_flag_in : qit IS in_flags(3); BEGIN IF arith_shift_right = '0' AND arith_shift_left = '0' THEN t := alu_side (7 DOWNTO 0); (v, c, z, n) := in_flags; ELSIF arith_shift_left = '1' THEN t := alu_side (6 DOWNTO 0) & '0'; n := t (7); z := set_if_zero (t); c := alu_side (7); v := alu_side (6) XOR alu_side (7); ELSIF arith_shift_right = '1' THEN t := alu_side (7) & alu_side (7 DOWNTO 1); n := t (7); z := set_if_zero (t); c := c_flag_in; v := v_flag_in; END IF; obus_side <= t; out_flags <= (v, c, z, n); END PROCESS coding; END behavioral;

• Behavioral Description of the Shifter Unit of Parwan



[0]

[1]

[2]

[3]

SRG1G2

loadcm_carry

N

Z

C

V

1, 3D

1, 3D

1, 3D2, 3D

1, 3D

N

Z

C

V

C3

2D

G1

Q

1C2

cm_carry

load

input c

output c

• The status register • Logic symbol • One bit hardware

ENTITY status_register_unit IS PORT (in_flags : IN nibble; out_status : OUT nibble; load, cm_carry, ck : IN qit ); END status_register_unit; -- ARCHITECTURE behavioral OF status_register_unit IS BEGIN PROCESS (ck) VARIABLE internal_state : nibble := "0000"; ALIAS internal_c : qit IS internal_state (2); BEGIN IF (ck = '0') THEN IF (load = '1') THEN internal_state := in_flags; ELSIF (cm_carry = '1') THEN internal_c := NOT internal_c; END IF; out_status <= internal_state; END IF; END PROCESS; END behavioral;

• Behavioral description of the status register of Parwan



[0]

[1]

[2]

[3]

[4]

[5]

[6]

[7]

G1M2M3

1C4

o0

o1

o2

o3

o4

o5

o6

o7

ACloadzero

2, 4D3, 4D

2, 4D

2, 4D

2, 4D

2, 4D

2, 4D

2, 4D

2, 4D

3, 4D

3, 4D

3, 4D

3, 4D

3, 4D

3, 4D

3, 4D

'0'

'0'

'0'

'0'

'0'

'0'

'0'

'0'

I0

I1

I2

I3

I4

I5

I6

I7

2D

G1

Q

1C2

OiIi

zero

• Parwan accumulator • Logic symbol • One bit hardware

ENTITY accumulator_unit IS PORT (i8 : IN byte; o8 : OUT byte; load, zero, ck : IN qit); END accumulator_unit; -- ARCHITECTURE dataflow OF accumulator_unit IS BEGIN enable : BLOCK (load = '1') BEGIN clocking : BLOCK ( (ck = '0' AND NOT ck'STABLE) AND GUARD ) BEGIN o8 <= GUARDED "00000000" WHEN zero = '1' ELSE i8; END BLOCK clocking; END BLOCK enable; END dataflow;

• Dataflow description of Parwan accumulator



[0]

[1]

[2]

[3]

[4]

[5]

[6]

[7]

IR

CI

1C2

2D

2D

2D

2D

2D

2D

2D

2D

I0

I1

I2

I3

I4

I5

I6

I7

o0

o1

o2

o3

o4

o5

o6

o7

LOAD

2D

G1

Q

1C2

OiIi

load

• The Parwan instruction register • Logic symbol • One bit hardware

ENTITY instruction_register_unit IS PORT (i8 : IN byte; o8 : OUT byte; load, ck : IN qit); END instruction_register_unit; -- ARCHITECTURE dataflow OF instruction_register_unit IS BEGIN enable : BLOCK (load = '1') BEGIN clocking : BLOCK ( (ck = '0' AND NOT ck'STABLE) AND GUARD ) BEGIN o8 <= GUARDED i8; END BLOCK clocking; END BLOCK enable; END dataflow;

• Dataflow description of the instruction register of Parwan



[0]

[1]

[2]

[3]

[4]

[5]

[6]

[7]

PC

C3/4+

2, 3D

2, 3D

2, 3D

2, 3D

2, 3D

2, 3D

2, 3D

2, 3D

I0

I1

I2

I3

I4

I5

I6

I7

o0

o1

o2

o3

o4

o5

o6

o7

[8]

[9]

[10]

[11]

o8

o9

o10

o11

I8

I9

I10

I11

1, 3D

1, 3D

1, 3D

1, 3D

G4

3R

G1

G2

reset

load_pageload_offset

increment

2R

G1

Q

C2

Oi

1T

load_pc_offset

reset

O i-1

clock

• Parwan program counter • Logic symbol • One bit hardware

ENTITY program_counter_unit IS PORT (i12 : IN twelve; o12 : OUT twelve; increment, load_page, load_offset, reset, ck : IN qit); END program_counter_unit; -- ARCHITECTURE behavioral OF program_counter_unit IS BEGIN PROCESS (ck) VARIABLE internal_state : twelve := zero_12; BEGIN IF (ck = '0' ) THEN IF reset = '1' THEN internal_state := zero_12; ELSIF increment = '1' THEN internal_state := inc (internal_state); ELSE IF load_page = '1' THEN internal_state (11 DOWNTO 8) := i12 (11 DOWNTO 8); END IF; IF load_offset = '1' THEN internal_state (7 DOWNTO 0) := i12 (7 DOWNTO 0); END IF; END IF; o12 <= internal_state; END IF; END PROCESS; END behavioral;

• Behavioral description of the program counter of Parwan



[0]

[1]

[2]

[3]

[4]

[5]

[6]

[7]

MAR

C3

2, 3D

2, 3D

2, 3D

2, 3D

2, 3D

2, 3D

2, 3D

2, 3D

I0

I1

I2

I3

I4

I5

I6

I7

o0

o1

o2

o3

o4

o5

o6

o7

[8]

[9]

[10]

[11]

o8

o9

o10

o11

I8

I9

I10

I11

1, 3D

1, 3D

1, 3D

1, 3D

G1

G2

load_page

load_offset

2D

G1

Q

1C2

OiIi

load

• Logic symbol for the memory address register of Parwan

ENTITY memory_address_register_unit IS PORT (i12 : IN twelve; o12 : OUT twelve; load_page, load_offset, ck : IN qit); END memory_address_register_unit; -- ARCHITECTURE behavioral OF memory_address_register_unit IS BEGIN PROCESS (ck) VARIABLE internal_state : twelve := zero_12; BEGIN IF (ck = '0' ) THEN IF load_page = '1' THEN internal_state (11 DOWNTO 8) := i12 (11 DOWNTO 8); END IF; IF load_offset = '1' THEN internal_state (7 DOWNTO 0) := i12 (7 DOWNTO 0); END IF; o12 <= internal_state; END IF; END PROCESS; END behavioral;

• Behavioral description of the memory address register of Parwan



ENTITY par_data_path IS PORT (databus : INOUT wired_byte BUS := "ZZZZZZZZ"; adbus : OUT twelve;

clk : IN qit; -- register controls: load_ac, zero_ac, load_ir, increment_pc, load_page_pc, load_offset_pc, reset_pc, load_page_mar, load_offset_mar, load_sr, cm_carry_sr, -- bus connections: pc_on_mar_page_bus, ir_on_mar_page_bus, pc_on_mar_offset_bus, dbus_on_mar_offset_bus, pc_offset_on_dbus, obus_on_dbus, databus_on_dbus, mar_on_adbus, dbus_on_databus, -- logic unit function control inputs: arith_shift_left, arith_shift_right, alu_and, alu_not, alu_a, alu_add, alu_b, alu_sub : IN qit; -- outputs to the controller: ir_lines : OUT byte; status : OUT nibble ); END par_data_path;

• Entity Declaration of the Data Section of Parwan • Wires all components • Specifies bussing



ARCHITECTURE structural OF par_data_path IS -- COMPONENT ac PORT (i8: IN byte; o8: OUT byte; load, zero, ck: IN qit); END COMPONENT; FOR r1: ac USE ENTITY WORK.accumulator_unit (dataflow); -- COMPONENT ir PORT (i8: IN byte; o8: OUT byte; load, ck: IN qit); END COMPONENT; FOR r2: ir USE ENTITY WORK.instruction_register_unit (dataflow); -- COMPONENT pc PORT (i12 : IN twelve; o12 : OUT twelve; increment, load_page, load_offset, reset, ck : IN qit); END COMPONENT; FOR r3: pc USE ENTITY WORK.program_counter_unit (behavioral); -- COMPONENT mar PORT (i12 : IN twelve; o12 : OUT twelve; load_page, load_offset, ck : IN qit); END COMPONENT; FOR r4: mar USE ENTITY WORK.memory_address_register_unit (behavioral); -- COMPONENT sr PORT (in_flags : IN nibble; out_status : OUT nibble; load, cm_carry, ck : IN qit ); END COMPONENT; FOR r5 : sr USE ENTITY WORK.status_register_unit (behavioral); -- COMPONENT alu PORT (a_side, b_side : IN byte; alu_and, alu_not, alu_a, alu_add, alu_b, alu_sub : IN qit; in_flags : IN nibble; z_out : OUT byte; out_flags : OUT nibble); END COMPONENT; FOR l1 : alu USE ENTITY WORK.arithmetic_logic_unit (behavioral); -- COMPONENT shu PORT (alu_side : IN byte; arith_shift_left, arith_shift_right : IN qit; in_flags : IN nibble; obus_side : OUT byte; out_flags : OUT nibble); END COMPONENT; FOR l2 : shu USE ENTITY WORK.shifter_unit (behavioral); -- SIGNAL ac_out, ir_out, alu_out, obus : byte; SIGNAL alu_a_inp : byte; SIGNAL pc_out, mar_out : twelve; SIGNAL dbus : wired_byte BUS; SIGNAL alu_flags, shu_flags, sr_out : nibble; SIGNAL mar_bus : wired_twelve BUS; SIGNAL mar_inp : twelve;

• Declarative Part of the structural Architecture of par_data_path • Components are declared • Busses and signals are declared

BEGIN -- bus connections -- -- dbus1: alu_a_inp <= qit_vector (dbus); dbus2: BLOCK (dbus_on_mar_offset_bus = '1') BEGIN mar_bus (7 DOWNTO 0) <= GUARDED dbus; END BLOCK dbus2; dbus3: BLOCK (dbus_on_databus = '1') BEGIN databus <= GUARDED dbus; END BLOCK dbus3; -- obus1: BLOCK (obus_on_dbus = '1') BEGIN dbus <= GUARDED wired_qit_vector (obus); END BLOCK obus1; -- databus1: BLOCK (databus_on_dbus = '1') BEGIN dbus <= GUARDED databus; END BLOCK databus1; -- mar_bus1: mar_inp <= qit_vector (mar_bus); -- -- register connections -- -- r1: ac PORT MAP (obus, ac_out, load_ac, zero_ac, clk); -- r2: ir PORT MAP (obus, ir_out, load_ir, clk); ir1: ir_lines <= ir_out; ir2: BLOCK (ir_on_mar_page_bus = '1') BEGIN mar_bus (11 DOWNTO 8) <= GUARDED wired_qit_vector (ir_out (3 DOWNTO 0)); END BLOCK ir2;

• Statement part of the par_data_path structural Architecture • Uses block statements for bussing • Register interconnections follow registers instantiation

r3: pc PORT MAP (mar_out, pc_out, increment_pc, load_page_pc, load_offset_pc, reset_pc, clk); pc1: BLOCK (pc_on_mar_page_bus = '1') BEGIN mar_bus (11 DOWNTO 8) <= GUARDED wired_qit_vector (pc_out (11 DOWNTO 8)); END BLOCK pc1; pc2: BLOCK (pc_on_mar_offset_bus = '1') BEGIN mar_bus (7 DOWNTO 0) <= GUARDED wired_qit_vector (pc_out (7 DOWNTO 0)); END BLOCK pc2; pc3: BLOCK (pc_offset_on_dbus = '1') BEGIN dbus <= GUARDED wired_qit_vector (pc_out (7 DOWNTO 0)); END BLOCK pc3; -- r4: mar PORT MAP (mar_inp, mar_out, load_page_mar, load_offset_mar, clk); mar1: BLOCK (mar_on_adbus = '1') BEGIN adbus <= GUARDED mar_out; END BLOCK mar1; -- r5: sr PORT MAP (shu_flags, sr_out, load_sr, cm_carry_sr, clk); sr1: status <= sr_out; -- -- connection of logical and register structures -- -- l1: alu PORT MAP (alu_a_inp, ac_out, alu_and, alu_not, alu_a, alu_add, alu_b, alu_sub, sr_out, alu_out, alu_flags); l2: shu PORT MAP (alu_out, arith_shift_left, arith_shift_right, alu_flags, obus, shu_flags); END structural;

• Statement part of the par_data_path structural Architecture • Ends with logic unit instantiations



i1D

Q

C1

control FF i

en

logicblock

signals issuingcontrol signals

control signals todata section

To othercontrol FF inputs

External Signals

All SignalsActivating State i

system clock

• Typical hardware surrounding a control flip-flop • The logic block is designated by a bubble • Controller is built using one-hot encoding

For the Parwan controller, style, hardware and coding will be described.



i1D

C1

en

logicblock

clock

j1D

C1

k1D

C1

Q

i

QQ en

logicblock

j

a

b

c

d

e

csx

csy

• Example for the structure of Parwan control section • Showing 3 states in a one-hot implementation



ENTITY par_control_unit IS GENERIC (read_delay, write_delay : TIME := 3 NS); PORT (clk : IN qit; -- register control signals: load_ac, zero_ac, load_ir, increment_pc, load_page_pc, load_offset_pc, reset_pc, load_page_mar, load_offset_mar, load_sr, cm_carry_sr, -- bus connection control signals: pc_on_mar_page_bus, ir_on_mar_page_bus, pc_on_mar_offset_bus, dbus_on_mar_offset_bus, pc_offset_on_dbus, obus_on_dbus, databus_on_dbus, mar_on_adbus, dbus_on_databus, -- logic unit function control outputs: arith_shift_left, arith_shift_right,

alu_and, alu_not, alu_a, alu_add, alu_b, alu_sub : OUT ored_qit BUS; -- inputs from the data section: ir_lines : IN byte; status : IN nibble; -- memory control and other external signals: read_mem, write_mem : OUT ored_qit BUS; interrupt : IN qit ); END par_control_unit;

------------------------------------------------------------------------------------------------- ARCHITECTURE dataflow OF par_control_unit IS SIGNAL s : ored_qit_vector (9 DOWNTO 1) REGISTER := “000000001”; BEGIN

• Entity declaration of Parwan control section • Showing signals for the data unit • Declaring states of the machine is shown • Declarative part of the par_control_unit dataflow architecture



par_control_unit

assignments tocontrol_signal_1control_signal_1

control_signal_2

control_signal_3

oring_qittype signals

• Assigning signals with implied oring, par_control_unit outputs

s1: BLOCK (s(1) = '1') BEGIN -- start of fetch -- pc to mar pc_on_mar_page_bus <= GUARDED '1'; pc_on_mar_offset_bus <= GUARDED '1'; load_page_mar <= GUARDED '1'; load_offset_mar <= GUARDED '1'; -- reset pc if interrupt reset_pc <= GUARDED '1' WHEN interrupt = '1' ELSE '0'; -- goto 2 if interrupt is off ck: BLOCK ( (clk = '0' AND NOT clk'STABLE) AND GUARD ) BEGIN s(1) <= GUARDED '1' WHEN interrupt = '1' ELSE '0'; s(2) <= GUARDED '1' WHEN interrupt /= '1' ELSE '0'; END BLOCK ck; END BLOCK s1;

1D

C1

1

pc_on_mar_page_bus

pc_on_mar_offset_bus

load_page_mar

load_offset_mar

reset_pc

interrupt

2

• State 1: starting a fetch • VHDL code • Gate level hardware

s2: BLOCK (s(2) = '1') BEGIN -- fetching continues -- read memory into ir mar_on_adbus <= GUARDED '1'; read_mem <= GUARDED '1' AFTER read_delay; databus_on_dbus <= GUARDED '1'; alu_a <= GUARDED ‘1’; load_ir <= GUARDED '1'; -- increment pc increment_pc <= GUARDED '1'; -- goto 3 ck: BLOCK ( (clk = '0' AND NOT clk'STABLE) AND GUARD ) BEGIN s(3) <= GUARDED '1'; END BLOCK ck; END BLOCK s2;

1D

C1

2

3

mar_on_adbus

read_mem

databus_on_dbus

alu_a

load_ir

increment_pc

• State 2: completing a fetch • VHDL code • Gate level hardware

s3: BLOCK (s(3) = '1') BEGIN -- pc to mar, for next read pc_on_mar_page_bus <= GUARDED '1'; pc_on_mar_offset_bus <= GUARDED '1'; load_page_mar <= GUARDED '1'; load_offset_mar <= GUARDED '1'; -- goto 4 if not single byte instruction ck: BLOCK ( (clk = '0' AND NOT clk'STABLE) AND GUARD ) BEGIN s(4) <= GUARDED '1' WHEN ir_lines (7 DOWNTO 4) /= "1110" ELSE '0'; END BLOCK ck; -- perform single byte instructions sb: BLOCK ( (ir_lines (7 DOWNTO 4) = "1110") AND GUARD) BEGIN (alu_not, alu_b) <= GUARDED qit_vector’(“10”) WHEN ir_lines (1) = ‘1’ ELSE qit_vector’( “01”); arith_shift_left <= GUARDED '1' WHEN ir_lines (3 DOWNTO 0) = "1000" ELSE '0'; arith_shift_right <= GUARDED '1' WHEN ir_lines (3 DOWNTO 0) = "1001" ELSE '0'; load_sr <= GUARDED '1' WHEN ( ir_lines (3) = '1' OR ir_lines (1) = '1' ) ELSE '0'; cm_carry_sr <= GUARDED '1' WHEN ir_lines (2) = '1' ELSE '0'; load_ac <= GUARDED '1' WHEN ( ir_lines (3) = '1' OR ir_lines (1) = '1' ) ELSE '0'; zero_ac <= GUARDED '1' WHEN ( ir_lines (3) = '0' AND ir_lines (0) = '1' ) ELSE '0'; ck: BLOCK ( (clk = '0' AND NOT clk'STABLE) AND GUARD ) BEGIN s(2) <= GUARDED '1'; END BLOCK ck; END BLOCK sb; END BLOCK s3;

• State 3: preparing for address fetch • Execution of single byte instructions • VHDL code



1D

C1

3

pc_on_mar_page_bus

pc_on_mar_offset_bus

load_page_mar

load_offset_mar

4

IR7IR6IR5IR4

2

arith_shift_left

arith_shift_right

alu_not

alu_b

load_sr

cm_carry_sr

load_ac

zero_acIR3

0

IR3

1

IR2

IR3

IR1

IR1

IR1

IR3210

IR3210

• State 3: preparing for address fetch • Execution of single byte instructions • Gate level hardware

s4: BLOCK (s(4) = '1') BEGIN -- page from ir, and offset from next memory makeup 12-bit address -- read memory into mar offset mar_on_adbus <= GUARDED '1'; read_mem <= GUARDED '1' AFTER read_delay; databus_on_dbus <= GUARDED '1'; dbus_on_mar_offset_bus <= GUARDED '1'; load_offset_mar <= GUARDED '1'; -- completed operand (dir/indir) address -- page from ir if not branch or jsr pg: BLOCK ( (ir_lines (7 DOWNTO 6) /= "11") AND GUARD) BEGIN ir_on_mar_page_bus <= GUARDED '1'; load_page_mar <= GUARDED '1'; -- goto 5 for indirect, 6 for direct ck: BLOCK ( (clk = '0' AND NOT clk'STABLE) AND GUARD ) BEGIN s(5) <= GUARDED '1' WHEN ir_lines (4) = '1' ELSE '0'; -- indir s(6) <= GUARDED '1' WHEN ir_lines (4) = '0' ELSE '0'; -- direct END BLOCK ck; END BLOCK pg; -- keep page in mar_page if jms or bra (same-page instructions) sp: BLOCK ( (ir_lines (7 DOWNTO 6) = "11") AND GUARD) BEGIN -- goto 7 for jsr, 9 for bra ck: BLOCK ( (clk = '0' AND NOT clk'STABLE) AND GUARD ) BEGIN s(7) <= GUARDED '1' WHEN ir_lines (5) = '0' ELSE '0'; -- jsr s(9) <= GUARDED '1' WHEN ir_lines (5) = '1' ELSE '0'; -- bra END BLOCK ck; END BLOCK sp; -- increment pc increment_pc <= GUARDED '1'; END BLOCK s4;

• State 4: completing address of full address instructions • Branching for indirect, direct, jsr, and branch • VHDL code • Gate level hardware



4

mar_on_adbus

read_mem

databus_on_dbus

dbus_on_mar_offet_bus

load_offset_mar

increment_pc

IR7

6

IR59

7

6

5

ir_on_mar_page_bus

load_page_mar

IR4C1

1D

• State 4: completing address of full address instructions • Branching for indirect, direct, jsr, and branch • Gate level hardware

s5: BLOCK (s(5) = '1') BEGIN -- indirect addressing -- read actual operand from memory into mar offset mar_on_adbus <= GUARDED '1'; read_mem <= GUARDED '1' AFTER read_delay; databus_on_dbus <= GUARDED '1'; dbus_on_mar_offset_bus <= GUARDED '1'; load_offset_mar <= GUARDED '1'; -- goto 6 ck: BLOCK ( (clk = '0' AND NOT clk'STABLE) AND GUARD ) BEGIN s(6) <= GUARDED '1'; END BLOCK ck; END BLOCK s5;

5

6

mar_on_adbus

read_mem

databus_on_dbus

dbus_on_mar_offset_bus

load_offset_mar

1D

c1

• State 5: taking care of indirect addressing • Actual address will now go in MAR



s6: BLOCK (s(6) = '1') BEGIN jm : BLOCK ( (ir_lines (7 DOWNTO 5) = "100" ) AND GUARD BEGIN . . . END BLOCK jm; st: BLOCK ( (ir_lines (7 DOWNTO 5) = "101") AND GUARD) BEGIN . . . END BLOCK st; rd: BLOCK ( (ir_lines (7) = '0') AND GUARD) BEGIN . . . END BLOCK rd; -- perform lda, and, add, sub END BLOCK s6;

1D

C1

6

2

load_page_pcload_offset_pc

1

mar_on_adbusalu_bobus_on_dbusdbus_on_databuswrite_mem

1

mar_on_adbusread_memdatabus_on_dbusload_srload_ac

alu_a

alu_and

alu_add

alu_sub

ir6 ir5

rd

st

jm

ir765

ir765

ir7

• State 6: reading the actual operand, • Reading and executing jmp, sta, lda, and, add, and sub instructions • Outline of the VHDL code • Outline of the hardware • Three separate blocks for [jmp], [sta], and [lda, and, add, sub]

s6: BLOCK (s(6) = '1') BEGIN jm : BLOCK ( (ir_lines (7 DOWNTO 5) = "100" ) AND GUARD BEGIN load_page_pc <= GUARDED '1'; load_offset_pc <= GUARDED '1'; -- goto 2 ck: BLOCK ( (clk = '0' AND NOT clk'STABLE) AND GUARD ) BEGIN s(2) <= GUARDED '1'; END BLOCK ck; END BLOCK jm; . . . END BLOCK s6;

• State 6: reading the actual operand, • Reading and executing jmp instruction • VHDL code • Two more blocks for [sta], and [lda, and, add, sub]

s6: BLOCK (s(6) = '1') BEGIN . . . st: BLOCK ( (ir_lines (7 DOWNTO 5) = "101") AND GUARD) BEGIN -- mar on adbus, ac on databus, write to memory mar_on_adbus <= GUARDED '1'; alu_b <= GUARDED ‘1’; obus_on_dbus <= GUARDED '1'; dbus_on_databus <= GUARDED '1'; write_mem <= GUARDED '1' AFTER write_delay; -- goto 1 ck: BLOCK ( (clk = '0' AND NOT clk'STABLE) AND GUARD ) BEGIN s(1) <= GUARDED '1'; END BLOCK ck; END BLOCK st; . . . END BLOCK s6;

• State 6: reading the actual operand, • Reading and executing sta instruction • Partial VHDL code • Need one more block for handling [lda, and, add, sub]

s6: BLOCK (s(6) = '1') BEGIN . . . rd: BLOCK ( (ir_lines (7) = '0') AND GUARD) BEGIN -- mar on adbus, read memory for operand, perform operation mar_on_adbus <= GUARDED '1'; read_mem <= GUARDED '1' AFTER read_delay; databus_on_dbus <= GUARDED '1'; alu_a <= GUARDED ‘1’ WHEN ir_lines (6 DOWNTO 5) = “00” ELSE ‘0’; alu_and <= GUARDED ‘1’ WHEN ir_lines (6 DOWNTO 5) = “01” ELSE ‘0’; alu_add <= GUARDED ‘1’ WHEN ir_lines (6 DOWNTO 5) = “10” ELSE ‘0’; alu_sub <= GUARDED ‘1’ WHEN ir_lines (6 DOWNTO 5) = “11” ELSE ‘0’; load_sr <= GUARDED '1'; load_ac <= GUARDED '1'; -- goto 1 ck: BLOCK ( (clk = '0' AND NOT clk'STABLE) AND GUARD ) BEGIN s(1) <= GUARDED '1'; END BLOCK ck; END BLOCK rd; -- perform lda, and, add, sub END BLOCK s6;

• State 6: reading the actual operand, • Reading and executing jmp, sta, lda, and, add, and sub instructions • Completing the VHDL code • This last block handles [lda, and, add, sub]

s6: BLOCK (s(6) = '1') BEGIN jm : BLOCK ( (ir_lines (7 DOWNTO 5) = "100" ) AND GUARD) BEGIN load_page_pc <= GUARDED '1'; load_offset_pc <= GUARDED '1'; -- goto 2 ck: BLOCK ( (clk = '0' AND NOT clk'STABLE) AND GUARD ) BEGIN s(2) <= GUARDED '1'; END BLOCK ck; END BLOCK jm; st: BLOCK ( (ir_lines (7 DOWNTO 5) = "101") AND GUARD) BEGIN -- mar on adbus, ac on databus, write to memory mar_on_adbus <= GUARDED '1'; alu_b <= GUARDED ‘1’; obus_on_dbus <= GUARDED '1'; dbus_on_databus <= GUARDED '1'; write_mem <= GUARDED '1' AFTER write_delay; -- goto 1 ck: BLOCK ( (clk = '0' AND NOT clk'STABLE) AND GUARD ) BEGIN s(1) <= GUARDED '1'; END BLOCK ck; END BLOCK st; rd: BLOCK ( (ir_lines (7) = '0') AND GUARD) BEGIN -- mar on adbus, read memory for operand, perform operation mar_on_adbus <= GUARDED '1'; read_mem <= GUARDED '1' AFTER read_delay; databus_on_dbus <= GUARDED '1'; alu_a <= GUARDED ‘1’ WHEN ir_lines (6 DOWNTO 5) = “00” ELSE ‘0’; alu_and <= GUARDED ‘1’ WHEN ir_lines (6 DOWNTO 5) = “01” ELSE ‘0’; alu_add <= GUARDED ‘1’ WHEN ir_lines (6 DOWNTO 5) = “10” ELSE ‘0’; alu_sub <= GUARDED ‘1’ WHEN ir_lines (6 DOWNTO 5) = “11” ELSE ‘0’; load_sr <= GUARDED '1'; load_ac <= GUARDED '1'; -- goto 1 ck: BLOCK ( (clk = '0' AND NOT clk'STABLE) AND GUARD ) BEGIN s(1) <= GUARDED '1'; END BLOCK ck; END BLOCK rd; -- perform lda, and, add, sub END BLOCK s6;

• State 6: reading the actual operand, and executing jmp, sta, lda, and, add, and sub instructions

• Complete VHDL code



1D

C1

6

2

load_page_pcload_offset_pc

1

mar_on_adbusalu_bobus_on_dbusdbus_on_databuswrite_mem

1

mar_on_adbusread_memdatabus_on_dbusload_srload_ac

alu_a

alu_and

alu_add

alu_sub

ir6 ir5

rd

st

jm

ir765

ir765

ir7

• State 6: reading the actual operand, and executing jmp, sta, lda, and, add, and sub instructions

• Complete gate level hardware

s7: BLOCK (s(7) = '1') BEGIN -- jsr -- write pc offset to top of subroutine mar_on_adbus <= GUARDED '1'; pc_offset_on_dbus <= GUARDED '1'; dbus_on_databus <= GUARDED '1'; write_mem <= GUARDED '1' AFTER write_delay; -- address of subroutine to pc load_offset_pc <= GUARDED '1'; -- goto 8 ck: BLOCK ( (clk = '0' AND NOT clk'STABLE) AND GUARD ) BEGIN s(8) <= GUARDED '1'; END BLOCK ck; END BLOCK s7;

7

8

mar_on_adbus

pc_offset_on_dbus

dbus_on_databus

write_mem

load_offset_pc

1D

c1

• State 7: writing return address of subroutine • Making pc point to top of subroutine • Complete VHDL code • Hardware

s8: BLOCK (s(8) = '1') BEGIN -- increment pc increment_pc <= GUARDED '1'; -- goto 1 ck: BLOCK ( (clk = '0' AND NOT clk'STABLE) AND GUARD ) BEGIN s(1) <= GUARDED '1'; END BLOCK ck; END BLOCK s8;

8

9

1D

c1

increment_pc

• State 8: incrementing pc to skip location reserved for return address

• VHDL code • Hardware

s9: BLOCK (s(9) = '1') BEGIN load_offset_pc <= GUARDED '1' WHEN (status AND ir_lines (3 DOWNTO 0)) /= "0000" ELSE '0'; -- goto 1 ck: BLOCK ( (clk = '0' AND NOT clk'STABLE) AND GUARD ) BEGIN s(1) <= GUARDED '1'; END BLOCK ck; END BLOCK s9;

1D

C1

9

1

ir3status3

ir2status2

ir1status1

ir0status0

load_offset_pc

• State 9: conditional loading of pc for branch instructions • VHDL code • Gate level hardware

ARCHITECTURE dataflow OF par_control_unit IS SIGNAL s : ored_qit_vector (9 DOWNTO 1) REGISTER := “000000001”; BEGIN

S1: BLOCK (s(1) = '1') BEGIN . . . BEGIN s(next) <= GUARDED '1'; END BLOCK ck; END BLOCK s1; S2: BLOCK (s(2) = '1') BEGIN . . . BEGIN s(next) <= GUARDED '1'; END BLOCK ck; END BLOCK s2; O O O O S8: BLOCK (s(8) = '1') BEGIN . . . BEGIN s(next) <= GUARDED '1'; END BLOCK ck; END BLOCK s8; S9: BLOCK (s(9) = '1') BEGIN . . . BEGIN s(next) <= GUARDED '1'; END BLOCK ck; END BLOCK s9;

ck: BLOCK ( clk = '0' AND NOT clk'STABLE ) BEGIN s (9 DOWNTO 1) <= GUARDED "000000000"; END BLOCK ck; -- State blocks end here END dataflow;

• Ending the dataflow description of the par_control_unit • Controller outline • Need to clock all states • A zero driver is placed on all state,.



11D

C1

enQ

21D

C1

Q

3

C1

Q en

4

C1

Q en

51D

C1

Q

61D

C1

enQ

71D

C1

Q

81D

C1

Q

91D

C1

Q

1D

• Complete control unit • Wire individual control flip-flops • Oring is done at inputs of states when branching is done to them



ENTITY par_central_processing_unit IS PORT (clk : IN qit; interrupt : IN qit; read_mem, write_mem : OUT qit; databus : INOUT wired_byte BUS := "ZZZZZZZZ";

adbus : OUT twelve ); END par_central_processing_unit;

• Entity declaration of the Parwan CPU for its dataflow description • Complete CPU wires data and control



ARCHITECTURE dataflow OF par_central_processing_unit IS COMPONENT par_data_path PORT (databus : INOUT wired_byte; adbus : OUT twelve; clk : IN qit; load_ac, zero_ac, . . . ir_lines : OUT byte; status : OUT nibble ); END COMPONENT; FOR data: par_data_path USE ENTITY WORK.par_data_path (structural); -- COMPONENT par_control_unit PORT (clk : IN qit; load_ac, zero_ac, . . . ir_lines : IN byte; status : IN nibble; read_mem, write_mem : OUT qit; interrupt : IN qit ); END COMPONENT; FOR ctrl: par_control_unit USE ENTITY WORK.par_control_unit (dataflow); -- SIGNAL load_ac, zero_ac, . . . SIGNAL ir_lines : byte; SIGNAL status : nibble; BEGIN data: par_data_path PORT MAP (databus, adbus, clk, load_ac, zero_ac, . . . ir_lines, status ); ctrl: par_control_unit PORT MAP (clk, load_ac, zero_ac, . . . ir_lines, status, read_mem, write_mem, interrupt ); END dataflow;

• The general outline of dataflow architectture of Parwan CPU. • Data and control declarations • Data and control wiring

A TEST BENCH FOR THE PARWAN CPU

ARCHITECTURE input_output OF parwan_tester IS COMPONENT parwan PORT (clk : IN qit; interrupt : IN qit; read_mem, write_mem : OUT qit; databus : INOUT wired_byte BUS; adbus : OUT twelve ); END COMPONENT; SIGNAL clock, interrupt, read, write : qit; SIGNAL data : wired_byte := "ZZZZZZZZ"; SIGNAL address : twelve; TYPE byte_memory IS ARRAY ( INTEGER RANGE <> ) OF byte; BEGIN int : interrupt <= '1', '0' AFTER 4500 NS; clk : clock <= NOT clock AFTER 1 US WHEN NOW <= 140 US ELSE clock; cpu : parwan PORT MAP (clock, interrupt, read, write, data, address); mem : PROCESS VARIABLE memory : byte_memory ( 0 TO 63 ) := ("00000000", "00011000", "10100000", "00011001", --lda 24, sta 25 "00100000", "00011010", "01000000", "00011011", --and 26, add 27 "11100010", "11101001", "01100000", "00011100", --cac, asr, sub 28 "00010000", "00011101", "11000000", "00100100", --lda i 29, jsr 36 "11101000", "11100000", "10000000", "00100000", --asl, nop, jmp 32 "00000000", "00000000", "00000000", "00000000", "01011100", "00000000", "01110000", "00010010", --(24, 25, 26, 27) "00001100", "00011111", "00000000", "01011010", --(28, 29, 30, 31) "10000000", "00010010", "00000000", "00000000", --jmp 18 "00000000", "11100010", "10010000", "00100100", -- , cma, jmp i 36 OTHERS => (OTHERS => ‘0’)); VARIABLE ia : INTEGER; BEGIN WAIT ON read, write; qit2int (address, ia); IF read = '1' THEN IF ia >= 64 THEN data <= "ZZZZZZZZ"; ELSE data <= wired_byte ( memory (ia) ); END IF; WAIT UNTIL read = '0'; data <= "ZZZZZZZZ"; ELSIF write = '1' THEN IF ia < 64 THEN memory (ia) := byte ( data ); END IF; WAIT UNTIL write = '0'; END IF; END PROCESS mem; END input_output;

• A simple test bench for Parwan behavioral and dataflow descriptions.

• A simple testbench • Include CPU instantiation, a short memory, and read/write

handshaking

ARCHITECTURE input_output OF parwan_tester IS . . . SIGNAL clock, interrupt, read, write : qit; SIGNAL data : wired_byte := "ZZZZZZZZ"; SIGNAL address : twelve; TYPE byte_memory IS ARRAY ( INTEGER RANGE <> ) OF byte; BEGIN int : interrupt <= '1', '0' AFTER 4500 NS; clk : clock <= NOT clock AFTER 1 US WHEN NOW <= 140 US ELSE clock; cpu : parwan PORT MAP (clock, interrupt, read, write, data, address); mem : PROCESS VARIABLE memory : byte_memory ( 0 TO 63 ) := ("00000000", "00011000", "10100000", "00011001", --lda 24, sta 25 "00100000", "00011010", "01000000", "00011011", --and 26, add 27 "11100010", "11101001", "01100000", "00011100", --cac, asr, sub 28 "00010000", "00011101", "11000000", "00100100", --lda i 29, jsr 36 "11101000", "11100000", "10000000", "00100000", --asl, nop, jmp 32 "00000000", "00000000", "00000000", "00000000", "01011100", "00000000", "01110000", "00010010", --(24, 25, 26, 27) "00001100", "00011111", "00000000", "01011010", --(28, 29, 30, 31) "10000000", "00010010", "00000000", "00000000", --jmp 18 "00000000", "11100010", "10010000", "00100100", -- , cma, jmp i 36 OTHERS => (OTHERS => ‘0’)); VARIABLE ia : INTEGER; BEGIN . . . END input_output;

• Initializing memory for Parwan instructions

ARCHITECTURE input_output OF parwan_tester IS . . . SIGNAL clock, interrupt, read, write : qit; SIGNAL data : wired_byte := "ZZZZZZZZ"; SIGNAL address : twelve; TYPE byte_memory IS ARRAY ( INTEGER RANGE <> ) OF byte; BEGIN int : interrupt <= '1', '0' AFTER 4500 NS; clk : clock <= NOT clock AFTER 1 US WHEN NOW <= 140 US ELSE clock; cpu : parwan PORT MAP (clock, interrupt, read, write, data, address); mem : PROCESS VARIABLE memory : byte_memory ( 0 TO 63 ) := . . . VARIABLE ia : INTEGER; BEGIN WAIT ON read, write; qit2int (address, ia); IF read = '1' THEN IF ia >= 64 THEN data <= "ZZZZZZZZ"; ELSE data <= wired_byte ( memory (ia) ); END IF; WAIT UNTIL read = '0'; data <= "ZZZZZZZZ"; ELSIF write = '1' THEN IF ia < 64 THEN memory (ia) := byte ( data ); END IF; WAIT UNTIL write = '0'; END IF; END PROCESS mem; END input_output;

• Produce test waveforms on interrupt and clock signals • Testing is done by modeling memory read and write operations • A single process assigns values from memory to databus • Same process handles memory write



CONFIGURATION behavior OF parwan_tester IS FOR input_output FOR cpu : parwan USE ENTITY behavioral.par_central_processing_unit(behavioral); END FOR; END FOR; END behavior; (a) CONFIGURATION dataflow OF parwan_tester IS FOR input_output FOR cpu : parwan USE ENTITY par_dataflow.par_central_processing_unit(dataflow); END FOR; END FOR; END dataflow; (b)

• Parwan tester applies data to Parwan buses • Component is declared, binding will be done by configuration

declaration • Hold data normally at z (High Impedance)

A MORE REALISTIC PARWAN

WHEN instr_fetch => ---------------------------------------2 -- read memory into ir read_mem <= '1'; IF grant = '1' THEN mar_on_adbus <= '1'; IF ready = '1' THEN databus_on_dbus <= '1'; alu_a <= ‘1’; load_ir <= '1'; increment_pc <= '1'; next_state <= do_one_bytes; ELSE next_state <= instr_fetch; END IF; ELSE next_state <= instr_fetch; END IF; WHEN do_one_bytes => --------------------------------------3

. . .

• Memory and bus signaling for fetch state of controller • Signals provide for slower memory handshaking • Buss access signals are included


SUMMARY

This chapter showed how VHDL could be used to describe a

system at the behavioral level before the system is even designed,

and at the dataflow level after major design decisions have been

made. The behavioral description aids designers as they verify

their understanding of the problem, while the dataflow

description can be used to verify the bussing and register

structure of the design. A design carried to the stage where a

dataflow model can be generated is only a few simple steps away

from complete hardware realization. For completing the design

of Parwan, flip-flop and gate interconnections should replace the

component descriptions in the Parwan dataflow model.

We consider the design presented here a manual design. We

used one-to-one hardware correspondence so that no intelligent

tools are required for the generation of hardware. The use of

VHDL as a top-down partitioning and verification tool has

helped us form such a methodology for manual design. The

methodology presented here can be applied to designs of much

larger magnitude.

• End of Chapter 10


CHAPTER 11

INTERFACE DESIGN AND MODELING

11.1 SYSTEM OVERVIEW 11.2 CPU TIMING 11.3 MEMORY SIGNALS 11.4 SHARING SYSTEM BUSES

11.4.1 Arbitration Operation 11.4.2 Wait Operation 11.4.3 Arbiter Model

11.5 DMA DEVICE 11.5.1 Serial Connection 11.5.2 Interface Through Arbiter 11.5.3 Interface to CPU 11.5.4 DMA Controller

11.6 CPU CACHE 11.6.1 Cache Structure 11.6.2 Cache Interface 11.6.3 Cache Structure Modeling 11.6.4 Controller Modeling

11.7 COMPLETE SYSTEM 11.8 SUMMARY


SYSTEM OVERVIEW

• Bussing arrangement and system components.

Memory4096*8

ArbiterDMA Device

SerialTo

Parallel

DMAController

AddressDecoder

serial_in

CPU

cache memory& controller


SYSTEM OVERVIEW

• CPU interface

8-bit CPU (Parwan)

databus

adbus

8 12

halted

readygrant

read_mem

write_mem

interrupt


MEMORY SIGNALS

• CPU read and write requests

clock

read_mem

grant

ready

adbus

databus

valid

valid

(a)


MEMORY SIGNALS

• CPU read and write requests

clock

write_mem

grant

ready

adbus valid

validdatabus

(b)


MEMORY SIGNALS

• Memory interface

Memory4096*8

data

bus

adbu

s

cs

rwbar


MEMORY SIGNALS

• Memory read operation

validdatabus

adbus

rwbar

cs

Memory Wait


SHARING SYSTEM BUSES

• Controlling bus access

Bus Arbiter and Wait Handler

clock

skip_wait

memsel

rwbar

ready

read

_req

uest

writ

e_re

ques

t

gran

t

port 1 port 2 port 3 port 4


SHARING SYSTEM BUSES

• Bus grant for read operation

clock

grant

memsel

read_request i

i

rwbar

ready

wait for bus access

wait for wait state

wait for device to complete

SHARING SYSTEM BUSES ENTITY arbitrator IS GENERIC (wait_states : natural_vector (3 DOWNTO 0) := (OTHERS => 1); clock_period : TIME := 1 US); PORT (read_request, write_request : IN nibble; grant : BUFFER nibble; clock, skip_wait : IN qit; memsel, rwbar, ready : OUT qit); END arbitrator; -- ARCHITECTURE behavioral OF arbitrator IS BEGIN -- Works with consecuitive requests wait_cycle: PROCESS BEGIN IF clock = '0' THEN WAIT FOR 20 NS; FOR i IN read_request'RANGE LOOP IF read_request(i) = '1' OR write_request(i) = '1' THEN grant <= "0000"; grant (i) <= '1'; memsel <= '1'; rwbar <= read_request (i); ready <= '0'; IF wait_states (i) /= 0 THEN wait: FOR j IN 1 TO wait_states (i) LOOP EXIT WHEN skip_wait = '1'; WAIT FOR clock_period; END LOOP wait; END IF; ready <= '1'; EXIT; ELSE grant (i) <= '0'; memsel <= '0'; END IF; END LOOP; END IF; WAIT ON clock; END PROCESS wait_cycle; END behavioral;

• Arbiter VHDL description


DMA DEVICE

• Interface of serial-to-parallel converter

Serial To Parallel

8

serial

rece

ived

data

read

y

fram

_erro

r

over

run

para

llel_

out


DMA DEVICE

• Interface of the DMA controller

DMA Controller

8

dev_data

dev_rdy

dev_rcv

error1error2

4

read_mem

write_mem

grant

ready

sele

ct_r

eg

clk

status_read

status_write

addressbus

databus


DMA DEVICE

• DMA Registers

Least 8 bits of starting address

DMA Registers

Most 4 bits of start

Number of bytes to transfer

done ie er2 er1 ie wr rd go

1111:1111_1100

1111:1111_1101

1111:1111_1110

1111:1111_1111

Address


DMA DEVICE

• Decoding for selecting DMA registers

Address Decoder

adbus

active

4

DMA DEVICE ENTITY quad_adrdcd IS GENERIC (addresses : twelve := "111111111100"); PORT (adbus : IN twelve; active : OUT qit; selects : OUT nibble); END quad_adrdcd; -- ARCHITECTURE behavioral OF quad_adrdcd IS BEGIN PROCESS (adbus) BEGIN IF to_bitvector (addresses AND adbus) = to_bitvector (addresses) THEN active <= '1'; CASE adbus (1 DOWNTO 0) IS WHEN "00" => selects <= "0001"; WHEN "01" => selects <= "0010"; WHEN "10" => selects <= "0100"; WHEN "11" => selects <= "1000"; WHEN OTHERS => selects <= "0000"; END CASE; ELSE active <= '0'; selects <= "0000"; END IF; END PROCESS; END behavioral;

• VHDL description of DMA register address decoder


DMA DEVICE

• DMA device

DMA

dev_data

dev_rdy

dev_rcv

error1error2

4

read_mem

write_mem

grant

ready

sele

ct_r

eg

status_read

status_write

databus

Decoder

adbus

act ive

S2P serial

rece

ived

data

read

y

fram

_erro

r

over

run

8

para

llel_

out

addressbus12

status_sel

selects

8


DMA DEVICE ENTITY dma_controller IS PORT (clk : IN qit; -- memory signals read_mem, write_mem : OUT qit := '0'; databus : INOUT byte := "ZZZZZZZZ"; adbus : INOUT twelve := "ZZZZZZZZZZZZ"; ready, grant : IN qit; -- cpu signals select_reg : IN nibble; status_rd, status_wr : IN qit; --device signals error1, error2, dev_rdy : IN qit; dev_rcv : OUT qit; dev_data : IN byte ); END dma_controller;

• DMA controller entity declaration


DMA DEVICE ARCHITECTURE behavioral of dma_controller IS Declarations (Figure 11.17) BEGIN “get serial, put parallel” process statement (Figure 11.18) -- “direct CPU communications” blocks (Figure 11.19) END behavioral;

• Outline of DMA controller architecture. SIGNAL done : qit := '0'; TYPE r4 IS ARRAY (0 TO 3) OF byte; SIGNAL rfile : r4 REGISTER := (OTHERS => zero_8); ALIAS go : qit IS rfile(3)(0); ALIAS rd : qit IS rfile(3)(1); ALIAS wr : qit IS rfile(3)(2); ALIAS ie : qit IS rfile(3)(3);

• DMA controller declarations.

DMA DEVICE get_put : PROCESS VARIABLE buff : byte := zero_8; VARIABLE pntr : twelve; VARIABLE numb : byte; BEGIN WAIT UNTIL go = '1'; done <= '0'; numb := rfile(2); pntr := rfile(1)(3 DOWNTO 0) & rfile(0); IF wr = '1' THEN writing : WHILE TO_INTEGER(numb) > 0 LOOP numb := numb - 1; -- get data IF dev_rdy /= '1' THEN WAIT UNTIL dev_rdy = '1'; END IF; buff := dev_data; WAIT UNTIL clk = '1'; dev_rcv <= '1'; WAIT UNTIL clk = '0'; dev_rcv <= '0'; -- put to mem write_mem <= '1'; WAIT UNTIL grant = '1'; databus <= buff; adbus <= pntr; pntr := pntr + 1; WAIT UNTIL ready = '1'; databus <= "ZZZZZZZZ"; adbus <= "ZZZZZZZZZZZZ"; write_mem <= '0'; END LOOP writing; done <= '1'; END IF; END PROCESS get_put;

• DMA controller “get serial and put parallel” process

DMA DEVICE cpu_direct : FOR i IN 0 TO 3 GENERATE databus <= rfile(i) WHEN select_reg(i) = '1' AND status_rd = '1' ELSE "ZZZZZZZZ"; r0to3 : BLOCK ((clk'EVENT AND clk = '0') AND select_reg(i) = '1' AND status_wr = '1') BEGIN rfile (i) <= GUARDED databus; END BLOCK; END GENERATE cpu_direct; r3 : BLOCK ((clk'EVENT AND clk = '0') AND done = '1') BEGIN rfile (3)(7 DOWNTO 4) <= GUARDED ('1', ie, error2, error1); END BLOCK;

• DMA controller “direct CPU communications” blocks


DMA DEVICE ENTITY dma_serial_device IS PORT (clk : IN qit; -- memory signals read_mem, write_mem : OUT qit := '0'; databus : INOUT byte := "ZZZZZZZZ"; adbus : INOUT twelve; ready, grant : IN qit; status_rd, status_wr : IN qit; status_sel : OUT qit; serial_in : IN qit); END dma_serial_device; -- ARCHITECTURE structural OF dma_serial_device IS COMPONENT dma IS PORT (clk : IN qit; read_mem, write_mem : OUT qit; databus : INOUT byte := "ZZZZZZZZ"; adbus : INOUT twelve; ready, grant : IN qit; select_reg : IN nibble; status_rd, status_wr : IN qit; error1, error2, dev_rdy : IN qit; dev_rcv : OUT qit; dev_data : IN byte ); END COMPONENT dma; COMPONENT dcd IS GENERIC (addresses : twelve := "1111111111XX"); PORT (adbus : IN twelve; active : OUT qit; selects : OUT nibble); END COMPONENT dcd; COMPONENT s2p IS GENERIC (bps : INTEGER := 9600); PORT (serial, received : IN qit; dataready : BUFFER qit; overrun, frame_error : OUT qit; parallel_out : BUFFER qit_vector (7 DOWNTO 0)); END COMPONENT s2p; SIGNAL s2p_rdy, s2p_rcv, s2p_er1, s2p_er2 : qit; SIGNAL s2p_par : byte; SIGNAL cpu_mem_data : byte; SIGNAL cpu_mem_addr : twelve; SIGNAL select_reg : nibble; BEGIN c1 : dma PORT MAP (clk, read_mem, write_mem, databus, adbus, ready, grant, select_reg, status_rd, status_wr, s2p_er1, s2p_er2, s2p_rdy, s2p_rcv, s2p_par); c2 : dcd PORT MAP (adbus, status_sel, select_reg); c3 : s2p PORT MAP (serial_in, s2p_rcv, s2p_rdy, s2p_er1, s2p_er2, s2p_par); END structural;

• DMA serial device, description for diagram of Figure 11.14


CPU CACHE

• Cache Block Diagram

5To32

DCD

valid tagWay 0

line

Way 1

v=1 &Match

v=1 &Match

0

1

8

adbus

set

5

LSB

MSB

7

tag

Hit

8

8


CPU CACHE

• The lru table

5To32

DCD

adbus

lru

1: If a recent data wasfound in Way 0;0: If a recent data wasfound in Way 1.

7

MSB

LSB

5


CPU CACHE

• Cache Interface

cache

mem_databus

mem_adbus

ready_mem

grant_mem

read_mem

write_mem

clk

data

bus

adbu

s

read

ygr

ant

writ

ere

ad


CPU CACHE ENTITY cache_system IS PORT (clk : IN qit; -- memory signals read_mem, write_mem : OUT qit; grant_mem, ready_mem : IN qit; mem_databus : INOUT byte := "ZZZZZZZZ"; mem_adbus : INOUT twelve := "ZZZZZZZZZZZZ"; -- cpu signals read, write : IN qit; grant, ready : OUT qit; databus : INOUT byte := "ZZZZZZZZ"; adbus : INOUT twelve := "ZZZZZZZZZZZZ" ); END cache_system;

• Cache Entity Declaration


CPU CACHE ARCHITECTURE control_and_memory of cache_system IS structure declarations BEGIN PROCESS local declarations BEGIN wait for request look for data in the cache For read, write If hit: For read, pass data to CPU For write, write data in cache and memory If miss: Find least recently used For write, write data in cache and memory For read, read from memory and pass on to CPU Wait until (read OR write)=’1’; END PROCESS; END control_and_memory;

• Outline of cache VHDL description


CPU CACHE SUBTYPE ways IS INTEGER RANGE 0 TO 1; SUBTYPE sets IS INTEGER RANGE 0 TO 31; TYPE line IS ARRAY (0 TO 0) OF byte; SUBTYPE tags IS qit_vector (6 DOWNTO 0); TYPE lru_type IS ARRAY (sets) OF ways; TYPE entry IS RECORD valid : BOOLEAN; tag : tags; data : line; END RECORD; TYPE each_cache IS ARRAY (sets) OF entry; TYPE cache_type IS ARRAY (ways) OF each_cache; SIGNAL cache : cache_type; SIGNAL lru : lru_type;

• Cache structure declarations VARIABLE s : sets; VARIABLE hit : BOOLEAN; VARIABLE w, free : ways; TYPE ww IS ARRAY(ways) OF ways; CONSTANT nw : ww := (1, 0); ALIAS set_value : qit_vector (4 DOWNTO 0) IS adbus (4 DOWNTO 0); ALIAS tag_value : tags IS adbus (11 DOWNTO 5);

• Controller local declarations

CPU CACHE grant <= '1'; ready <= '0'; WAIT UNTIL clk = '0'; s := TO_INTEGER (set_value); hit := FALSE; FOR i IN ways LOOP IF cache(i)(s).tag = tag_value AND cache(i)(s).valid THEN hit := TRUE; w := i; END IF; END LOOP;

• Controller search in cache IF hit THEN lru (s) <= nw (w); IF read = '1' THEN ready <= '1'; databus <= cache(w)(s).data(0); WAIT UNTIL read = '0'; databus <= "ZZZZZZZZ"; ELSIF write = '1' THEN cache(w)(s).data(0) <= databus; cache(w)(s).valid <= TRUE; write_mem <= '1'; WAIT UNTIL grant_mem = '1'; mem_databus <= databus; mem_adbus <= adbus; WAIT UNTIL ready_mem = '1'; mem_databus <= "ZZZZZZZZ"; mem_adbus <= "ZZZZZZZZZZZZ"; write_mem <= '0'; ready <= '1'; WAIT UNTIL write = '0'; END IF; ready <= '0';

• Controller code for cache hit

CPU CACHE ELSE -- miss free := lru (s); lru (s) <= nw (lru (s)); IF write = '1' THEN cache(free)(s).tag <= tag_value; cache(free)(s).data(0) <= databus; cache(free)(s).valid <= TRUE; write_mem <= '1'; WAIT UNTIL grant_mem = '1'; mem_databus <= databus; mem_adbus <= adbus; WAIT UNTIL ready_mem = '1'; mem_databus <= "ZZZZZZZZ"; mem_adbus <= "ZZZZZZZZZZZZ"; write_mem <= '0'; ready <= '1'; WAIT UNTIL write = '0'; ready <= '0'; ELSIF read = '1' THEN read_mem <= '1'; WAIT UNTIL grant_mem = '1'; mem_adbus <= adbus; WAIT UNTIL ready_mem = '1'; cache(free)(s).tag <= tag_value; cache(free)(s).data(0) <= mem_databus; cache(free)(s).valid <= TRUE; databus <= mem_databus; mem_adbus <= "ZZZZZZZZZZZZ"; read_mem <= '0'; ready <= '1'; WAIT UNTIL read = '0'; ready <= '0'; END IF; END IF;

• Controller code for cache miss


CPU CACHE

• Board level interface

s2p

DMA

Decoder

Arbiter

Mem

Cache

Parwan CPU

CPU CACHE ENTITY parwan_tester IS END parwan_tester; -- ARCHITECTURE system OF parwan_tester IS BEGIN int : interrupt <= '1', '0' AFTER 4500 NS; clk : clock <= NOT clock AFTER duty WHEN halted = '0' ELSE clock; arb : arbitr GENERIC MAP ((OTHERS => 2), period) PORT MAP (rd_req, wr_req, grant_mem, clock, skip_wait, cs, rwbar, ready); dev : serial PORT MAP (clock, rd_req(0), wr_req(0), data, address, ready, grant_mem(0), cpu_read, cpu_write, skip_wait, serial_in); csh : cache PORT MAP (clock, rd_req(1), wr_req(1), grant_mem(1), ready, data, address, cpu_read, cpu_write, csh_grant, csh_ready, cpu_data, cpu_address); cpu : parwan PORT MAP (clock, interrupt, cpu_read, cpu_write, cpu_data, cpu_address, halted, csh_ready, csh_grant); mem : memory PORT MAP (cs, rwbar, data, address); srg : sergen PORT MAP (serial_in); END system;

• Interface board VHDL description


SUMMARY

In this chapter we presented a board level design in VHDL.

We illustrated the use of VHDL in a component level design

environment. Language constructs for behavioral

descriptions and timing and control were emphasized.

Several components with differing handshaking

schemes were independently described. The interface of the

memory component is non-responsive, while other

components such as the CPU and cache controller have two

or three line fully-responsive or partially-responsive

handshaking schemes. We have illustrated how such

handshaking schemes can be described in VHDL, and how

VHDL constructs can be used for handing communication

between various devices.

As opposed to Chapter 10 in which hardware details of

a design were of concern, this chapter presented design at a

higher level of abstraction. VHDL constructs used in this

chapter were primarily at the behavioral level as discussed in

Chapter 9. The examples presented here, show various forms

of using wait statements in describing a design.

• End of Chapter 11

vhdl lecture notes - navabi

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