george mason university ece 448 fpga and asic design with vhdl vhdl refresher lecture 2

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George Mason University ECE 448 – FPGA and ASIC Design with VHDL VHDL Refresher Lecture 2

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3ECE 448 – FPGA and ASIC Design with VHDL Recommended reading Wikipedia – The Free On-line Encyclopedia VHDL - Verilog -

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Page 1: George Mason University ECE 448  FPGA and ASIC Design with VHDL VHDL Refresher Lecture 2

George Mason UniversityECE 448 – FPGA and ASIC Design with VHDL

VHDL Refresher

Lecture 2

Page 2: George Mason University ECE 448  FPGA and ASIC Design with VHDL VHDL Refresher Lecture 2

2ECE 448 – FPGA and ASIC Design with VHDL

Required reading

• P. Chu, FPGA Prototyping by VHDL Examples

Chapter 1, Gate-level combinational circuit

• S. Brown and Z. Vranesic, Fundamentals of Digital Logic with VHDL Design

Chapter 2.10, Introduction to VHDL

Page 3: George Mason University ECE 448  FPGA and ASIC Design with VHDL VHDL Refresher Lecture 2

3ECE 448 – FPGA and ASIC Design with VHDL

Recommended reading

• Wikipedia – The Free On-line Encyclopedia

VHDL - http://en.wikipedia.org/wiki/VHDL Verilog - http://en.wikipedia.org/wiki/Verilog

Page 4: George Mason University ECE 448  FPGA and ASIC Design with VHDL VHDL Refresher Lecture 2

4ECE 448 – FPGA and ASIC Design with VHDL

Recommended reading

• S. Brown and Z. Vranesic, Fundamentals of Digital Logic with VHDL Design Chapter 6, Combinational-circuit building blocks

Required for Lab 1!Opportunity for bonus points during

the next two lectures!

• P. Chu, FPGA Prototyping by VHDL ExamplesChapter 3, RT-level combinational circuit

Page 5: George Mason University ECE 448  FPGA and ASIC Design with VHDL VHDL Refresher Lecture 2

5ECE 448 – FPGA and ASIC Design with VHDL

Brief History of VHDL

Page 6: George Mason University ECE 448  FPGA and ASIC Design with VHDL VHDL Refresher Lecture 2

6ECE 448 – FPGA and ASIC Design with VHDL

VHDL

• VHDL is a language for describing digital hardware used by industry worldwide

• VHDL is an acronym for VHSIC (Very High Speed Integrated Circuit) Hardware Description Language

Page 7: George Mason University ECE 448  FPGA and ASIC Design with VHDL VHDL Refresher Lecture 2

7ECE 448 – FPGA and ASIC Design with VHDL

Genesis of VHDL

• Multiple design entry methods and hardware description languages in use• No or limited portability of designs between CAD tools from different vendors• Objective: shortening the time from a

design concept to implementation from 18 months to 6 months

State of art circa 1980

Page 8: George Mason University ECE 448  FPGA and ASIC Design with VHDL VHDL Refresher Lecture 2

8ECE 448 – FPGA and ASIC Design with VHDL

A Brief History of VHDL

• June 1981: Woods Hole Workshop• July 1983: contract awarded to develop VHDL

• Intermetrics• IBM• Texas Instruments

• August 1985: VHDL Version 7.2 released• December 1987:

VHDL became IEEE Standard 1076-1987 and in 1988 an ANSI standard

Page 9: George Mason University ECE 448  FPGA and ASIC Design with VHDL VHDL Refresher Lecture 2

9ECE 448 – FPGA and ASIC Design with VHDL

Four versions of VHDL

• Four versions of VHDL:• IEEE-1076 1987• IEEE-1076 1993 most commonly supported by CAD tools• IEEE-1076 2000 (minor changes)• IEEE-1076 2002 (minor changes)

Page 10: George Mason University ECE 448  FPGA and ASIC Design with VHDL VHDL Refresher Lecture 2

10ECE 448 – FPGA and ASIC Design with VHDL

Verilog

Page 11: George Mason University ECE 448  FPGA and ASIC Design with VHDL VHDL Refresher Lecture 2

11ECE 448 – FPGA and ASIC Design with VHDL

Verilog• Essentially identical in function to VHDL

• No generate statement• Simpler and syntactically different

• C-like

• Gateway Design Automation Co., 1985• Gateway acquired by Cadence in 1990• IEEE Standard 1364-1995• Early de facto standard for ASIC programming

• Programming language interface to allow connection to non-Verilog code

Page 12: George Mason University ECE 448  FPGA and ASIC Design with VHDL VHDL Refresher Lecture 2

12ECE 448 – FPGA and ASIC Design with VHDL

VHDL vs. Verilog

Government Developed

Commercially Developed

Ada based C based

Strongly Type Cast Mildly Type Cast

Case-insensitive Case-sensitive

Difficult to learn Easier to Learn

More Powerful Less Powerful

Page 13: George Mason University ECE 448  FPGA and ASIC Design with VHDL VHDL Refresher Lecture 2

13ECE 448 – FPGA and ASIC Design with VHDL

How to learn Verilog by yourself ?

Page 14: George Mason University ECE 448  FPGA and ASIC Design with VHDL VHDL Refresher Lecture 2

14ECE 448 – FPGA and ASIC Design with VHDL

Features of VHDL and Verilog

• Technology/vendor independent

• Portable

• Reusable

Page 15: George Mason University ECE 448  FPGA and ASIC Design with VHDL VHDL Refresher Lecture 2

15ECE 448 – FPGA and ASIC Design with VHDL

VHDL Fundamentals

Page 16: George Mason University ECE 448  FPGA and ASIC Design with VHDL VHDL Refresher Lecture 2

16ECE 448 – FPGA and ASIC Design with VHDL

Naming and Labeling (1)

• VHDL is case insensitiveExample:

Names or labelsdatabusDatabusDataBusDATABUS

are all equivalent

Page 17: George Mason University ECE 448  FPGA and ASIC Design with VHDL VHDL Refresher Lecture 2

17ECE 448 – FPGA and ASIC Design with VHDL

Naming and Labeling (2)

General rules of thumb (according to VHDL-87)

1. All names should start with an alphabet character (a-z or A-Z)

2. Use only alphabet characters (a-z or A-Z) digits (0-9) and underscore (_)

3. Do not use any punctuation or reserved characters within a name (!, ?, ., &, +, -, etc.)

4. Do not use two or more consecutive underscore characters (__) within a name (e.g., Sel__A is invalid)

5. All names and labels in a given entity and architecture must be unique

Page 18: George Mason University ECE 448  FPGA and ASIC Design with VHDL VHDL Refresher Lecture 2

18ECE 448 – FPGA and ASIC Design with VHDL

Valid or invalid?

7segment_displayA87372477424Adder/Subtractor/resetAnd_or_gateAND__OR__NOTKogge-Stone-AdderRipple&Carry_AdderMy adder

Page 19: George Mason University ECE 448  FPGA and ASIC Design with VHDL VHDL Refresher Lecture 2

19ECE 448 – FPGA and ASIC Design with VHDL

Free Format

• VHDL is a “free format” language No formatting conventions, such as spacing or

indentation imposed by VHDL compilers. Space and carriage return treated the same way.Example:

if (a=b) thenor

if (a=b) then or

if (a =b) then

are all equivalent

Page 20: George Mason University ECE 448  FPGA and ASIC Design with VHDL VHDL Refresher Lecture 2

20ECE 448 – FPGA and ASIC Design with VHDL

Readability standards & coding style

Adopt readability standards based on one of the the two main textbooks:

Chu or Brown/Vranesic

Use coding style recommended in OpenCores Coding Guidelines

linked from the course web page

Strictly enforced by the lab instructors and myself.Penalty points may be enforced for not following

these recommendations!!!

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21ECE 448 – FPGA and ASIC Design with VHDL

Comments

• Comments in VHDL are indicated with a “double dash”, i.e., “--”

Comment indicator can be placed anywhere in the line

Any text that follows in the same line is treated as a comment Carriage return terminates a comment No method for commenting a block extending over

a couple of linesExamples:-- main subcircuitData_in <= Data_bus; -- reading data from the input FIFO

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22ECE 448 – FPGA and ASIC Design with VHDL

Comments

• Explain Function of Module to Other Designers

• Explanatory, Not Just Restatement of Code• Locate Close to Code Described

• Put near executable code, not just in a header

Page 23: George Mason University ECE 448  FPGA and ASIC Design with VHDL VHDL Refresher Lecture 2

23ECE 448 – FPGA and ASIC Design with VHDL

Design Entity

Page 24: George Mason University ECE 448  FPGA and ASIC Design with VHDL VHDL Refresher Lecture 2

24ECE 448 – FPGA and ASIC Design with VHDL

Example: NAND Gate

a b z0 0 10 1 11 0 11 1 0

a

bz

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25ECE 448 – FPGA and ASIC Design with VHDL

Example VHDL Code• 3 sections to a piece of VHDL code• File extension for a VHDL file is .vhd• Name of the file should be the same as the entity name

(nand_gate.vhd) [OpenCores Coding Guidelines]

LIBRARY DECLARATION

ENTITY DECLARATION

ARCHITECTURE BODY

LIBRARY ieee;USE ieee.std_logic_1164.all;

ENTITY nand_gate ISPORT( a : IN STD_LOGIC;

b : IN STD_LOGIC; z : OUT STD_LOGIC);

END nand_gate;

ARCHITECTURE model OF nand_gate ISBEGIN

z <= a NAND b;END model;

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26ECE 448 – FPGA and ASIC Design with VHDL

Design Entity - most basic building block of a design.

One entity can have many different architectures.

entity declaration

architecture 1

architecture 2

architecture 3

design entity

Design Entity

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27ECE 448 – FPGA and ASIC Design with VHDL

ENTITY nand_gate ISPORT( a : IN STD_LOGIC;

b : IN STD_LOGIC; z : OUT STD_LOGIC

);END nand_gate;

Reserved words

Entity name Port names Port typeSemicolon

No Semicolon after last port

Port modes (data flow directions)

Entity Declaration

• Entity Declaration describes the interface of the component, i.e. input and output ports.

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28ECE 448 – FPGA and ASIC Design with VHDL

ENTITY entity_name IS PORT ( port_name : port_mode signal_type; port_name : port_mode signal_type; …………. port_name : port_mode signal_type);END entity_name;

Entity declaration – simplified syntax

Page 29: George Mason University ECE 448  FPGA and ASIC Design with VHDL VHDL Refresher Lecture 2

29ECE 448 – FPGA and ASIC Design with VHDL

a

EntityPort signal

Driver residesoutside the entity

Port Mode IN

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30ECE 448 – FPGA and ASIC Design with VHDL

Entity

Port signal

Driver residesinside the entity

Output cannot be read within the entity

z

c <= z

c

Port Mode OUT

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31ECE 448 – FPGA and ASIC Design with VHDL

Port signal

Entity

Driver residesinside the entity

Signal x can beread inside the entity

x

c

z

z <= xc <= x

Port Mode OUT (with extra signal)

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32ECE 448 – FPGA and ASIC Design with VHDL

Entity

Port signal

Driver residesinside the entity

Port signal Z can beread inside the entity

c

z

c <= z

Port Mode BUFFER

Not recommended by OpenCores Coding Guidelines.Port of mode buffer can not be connected to other types of ports

so buffer mode will propagate throughout the entire hierarchical design. Problems reported with synthesis of designs using these ports.

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33ECE 448 – FPGA and ASIC Design with VHDL

Signal can beread inside the entity

EntityPort signal

Driver may resideboth inside and outsideof the entity

a

Port Mode INOUT

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34ECE 448 – FPGA and ASIC Design with VHDL

Port Modes - SummaryThe Port Mode of the interface describes the direction in which data travels with respect to the component

• In: Data comes into this port and can only be read within the entity. It can appear only on the right side of a signal or variable assignment.

• Out: The value of an output port can only be updated within the entity. It cannot be read. It can only appear on the left side of a signal assignment.

• Inout: The value of a bi-directional port can be read and updated within the entity model. It can appear on both sides of a signal assignment.

• Buffer: Used for a signal that is an output from an entity. The value of the signal can be used inside the entity, which means that in an assignment statement the signal can appear on the left and right sides of the <= operator. Not recommended to be used in the synthesizable code.

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35ECE 448 – FPGA and ASIC Design with VHDL

Architecture (Architecture body)

• Describes an implementation of a design entity

• Architecture example:

ARCHITECTURE model OF nand_gate ISBEGIN

z <= a NAND b;END model;

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36ECE 448 – FPGA and ASIC Design with VHDL

Architecture – simplified syntax

ARCHITECTURE architecture_name OF entity_name IS [ declarations ]BEGIN codeEND architecture_name;

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37ECE 448 – FPGA and ASIC Design with VHDL

Entity Declaration & Architecture

LIBRARY ieee;USE ieee.std_logic_1164.all;

ENTITY nand_gate ISPORT( a : IN STD_LOGIC;

b : IN STD_LOGIC; z : OUT STD_LOGIC);

END nand_gate;

ARCHITECTURE dataflow OF nand_gate ISBEGIN

z <= a NAND b;END dataflow;

nand_gate.vhd

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38ECE 448 – FPGA and ASIC Design with VHDL

Tips & Hints

Place each entity in a different file.

The name of each file should be exactly the sameas the name of an entity it contains.

These rules are not enforced by all toolsbut are worth following in order to increasereadability and portability of your designs

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39ECE 448 – FPGA and ASIC Design with VHDL

Tips & Hints

Place the declaration of each port, signal, constant, and variable

in a separate line

These rules are not enforced by all toolsbut are worth following in order to increasereadability and portability of your designs

Page 40: George Mason University ECE 448  FPGA and ASIC Design with VHDL VHDL Refresher Lecture 2

40ECE 448 – FPGA and ASIC Design with VHDL

Libraries

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41ECE 448 – FPGA and ASIC Design with VHDL

Library Declarations

Use all definitions from the packagestd_logic_1164

LIBRARY ieee;USE ieee.std_logic_1164.all;

ENTITY nand_gate ISPORT( a : IN STD_LOGIC;

b : IN STD_LOGIC; z : OUT STD_LOGIC);

END nand_gate;

ARCHITECTURE model OF nand_gate ISBEGIN

z <= a NAND b;END model;

Library declaration

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42ECE 448 – FPGA and ASIC Design with VHDL

Library declarations - syntax

LIBRARY library_name;USE library_name.package_name.package_parts;

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43ECE 448 – FPGA and ASIC Design with VHDL

Fundamental parts of a library

LIBRARY

PACKAGE 1 PACKAGE 2

TYPESCONSTANTSFUNCTIONS

PROCEDURESCOMPONENTS

TYPESCONSTANTSFUNCTIONS

PROCEDURESCOMPONENTS

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44ECE 448 – FPGA and ASIC Design with VHDL

Libraries

• ieee

• std

• work

Need to be explicitlydeclared

Visible by default

Specifies multi-level logic system,including STD_LOGIC, and STD_LOGIC_VECTOR data types

Specifies pre-defined data types(BIT, BOOLEAN, INTEGER, REAL, SIGNED, UNSIGNED, etc.), arithmetic operations, basic type conversion functions, basic text i/o functions, etc.

Holds current designs after compilation

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45ECE 448 – FPGA and ASIC Design with VHDL

STD_LOGIC Demystified

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46ECE 448 – FPGA and ASIC Design with VHDL

STD_LOGIC

What is STD_LOGIC you ask?

LIBRARY ieee;USE ieee.std_logic_1164.all;

ENTITY nand_gate ISPORT( a : IN STD_LOGIC;

b : IN STD_LOGIC; z : OUT STD_LOGIC);

END nand_gate;

ARCHITECTURE dataflow OF nand_gate ISBEGIN

z <= a NAND b;END dataflow;

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47ECE 448 – FPGA and ASIC Design with VHDL

BIT versus STD_LOGIC

• BIT type can only have a value of ‘0’ or ‘1’• STD_LOGIC can have eight values

• ‘0’,’1’,’X’,’Z’,’W’,’L’,’H’,’-’• Useful mainly for simulation• ‘0’,’1’, and ‘Z’ are synthesizable (your codes should contain only these three values)

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48ECE 448 – FPGA and ASIC Design with VHDL

STD_LOGIC type demystified

Value Meaning

‘X’ Forcing (Strong driven) Unknown

‘0’ Forcing (Strong driven) 0

‘1’ Forcing (Strong driven) 1

‘Z’ High Impedance

‘W’ Weak (Weakly driven) Unknown

‘L’ Weak (Weakly driven) 0.Models a pull down.

‘H’ Weak (Weakly driven) 1. Models a pull up.

‘-’ Don't Care

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49ECE 448 – FPGA and ASIC Design with VHDL

More on STD_LOGIC Meanings (1)

‘1’

‘0’

‘X’

Contention on the busX

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50ECE 448 – FPGA and ASIC Design with VHDL

More on STD_LOGIC Meanings (2)

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51ECE 448 – FPGA and ASIC Design with VHDL

VDD

‘H’

‘0’

‘1’

‘L’

More on STD_LOGIC Meanings (3)

VDD

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52ECE 448 – FPGA and ASIC Design with VHDL

More on STD_LOGIC Meanings (4)

•Do not care.•Can be assigned to outputs for the case of invalid inputs(may produce significant improvement in resource utilization after synthesis).•Must be used with great caution. For example in VHDL, the comparison ‘1’ = ‘-’ gives FALSE.

‘-’

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53ECE 448 – FPGA and ASIC Design with VHDL

Resolving logic levels

X 0 1 Z W L H -

X X X X X X X X X0 X 0 X 0 0 0 0 X1 X X 1 1 1 1 1 XZ X 0 1 Z W L H XW X 0 1 W W W W XL X 0 1 L W L W XH X 0 1 H W W H X- X X X X X X X X

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54ECE 448 – FPGA and ASIC Design with VHDL

STD_LOGIC Rules

• In ECE 448, use std_logic or std_logic_vector for all entity input or output ports• Do not use integer, unsigned, signed, bit for

ports• You can use them inside of architectures if

desired• You can use them in generics

• Instead use std_logic_vector and a conversion function inside of your architecture

[Consistent with OpenCores Coding Guidelines]

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55ECE 448 – FPGA and ASIC Design with VHDL

Modeling Wires and Buses

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56ECE 448 – FPGA and ASIC Design with VHDL

Signals

SIGNAL a : STD_LOGIC;

SIGNAL b : STD_LOGIC_VECTOR(7 DOWNTO 0);

wire

a

bus

b

1

8

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57ECE 448 – FPGA and ASIC Design with VHDL

Standard Logic Vectors

SIGNAL a: STD_LOGIC;SIGNAL b: STD_LOGIC_VECTOR(3 DOWNTO 0);SIGNAL c: STD_LOGIC_VECTOR(3 DOWNTO 0);SIGNAL d: STD_LOGIC_VECTOR(15 DOWNTO 0);SIGNAL e: STD_LOGIC_VECTOR(8 DOWNTO 0); ……….a <= ‘1’;b <= ”0000”; -- Binary base assumed by defaultc <= B”0000”; -- Binary base explicitly specifiedd <= X”AF67”; -- Hexadecimal basee <= O”723”; -- Octal base

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58ECE 448 – FPGA and ASIC Design with VHDL

Vectors and Concatenation

SIGNAL a: STD_LOGIC_VECTOR(3 DOWNTO 0);SIGNAL b: STD_LOGIC_VECTOR(3 DOWNTO 0);SIGNAL c, d, e: STD_LOGIC_VECTOR(7 DOWNTO 0);

a <= ”0000”; b <= ”1111”; c <= a & b; -- c = ”00001111”

d <= ‘0’ & ”0001111”; -- d <= ”00001111”

e <= ‘0’ & ‘0’ & ‘0’ & ‘0’ & ‘1’ & ‘1’ & ‘1’ & ‘1’; -- e <= ”00001111”

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59ECE 448 – FPGA and ASIC Design with VHDL

Fixed Rotation in VHDL

A(3) A(2) A(1) A(0)

A(2) A(1) A(0) A(3)

A<<<1

SIGNAL A : STD_LOGIC_VECTOR(3 DOWNTO 0);SIGNAL ArotL: STD_LOGIC_VECTOR(3 DOWNTO 0);

ArotL <=

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60ECE 448 – FPGA and ASIC Design with VHDL

Fixed Shift in VHDL

A(3) A(2) A(1) A(0)

‘0’ A(3) A(2) A(1)

A>>1

SIGNAL A : STD_LOGIC_VECTOR(3 DOWNTO 0);SIGNAL AshiftR: STD_LOGIC_VECTOR(3 DOWNTO 0);

AshiftR <=

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61ECE 448 – FPGA and ASIC Design with VHDL

VHDL Design Styles

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62ECE 448 – FPGA and ASIC Design with VHDL

VHDL Design Styles

Components andinterconnects

structural

VHDL Design Styles

dataflow

Concurrent statements

behavioral(sequential)

• Registers• State machines• Decoders

Sequential statements

Subset most suitable for synthesis

• Testbenches

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63ECE 448 – FPGA and ASIC Design with VHDL

xor3 Example

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64ECE 448 – FPGA and ASIC Design with VHDL

Entity xor3_gate

LIBRARY ieee;USE ieee.std_logic_1164.all;

ENTITY xor3_gate IS PORT(

A : IN STD_LOGIC; B : IN STD_LOGIC; C : IN STD_LOGIC; Result : OUT STD_LOGIC

);end xor3_gate;

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65ECE 448 – FPGA and ASIC Design with VHDL

Dataflow Architecture (xor3_gate)

ARCHITECTURE dataflow OF xor3_gate ISSIGNAL U1_OUT: STD_LOGIC;BEGIN

U1_OUT <= A XOR B;Result <= U1_OUT XOR C;

END dataflow;

U1_OUT

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66ECE 448 – FPGA and ASIC Design with VHDL

Dataflow Description • Describes how data moves through the system and the various

processing steps. • Dataflow uses series of concurrent statements to realize logic. • Dataflow is most useful style when series of Boolean equations

can represent a logic used to implement simple combinational logic

• Dataflow code also called “concurrent” code• Concurrent statements are evaluated at the same time; thus, the

order of these statements doesn’t matter• This is not true for sequential/behavioral statements

This order…

U1_out <= A XOR B;

Result <= U1_out XOR C; Is the same as this order…

Result <= U1_out XOR C;

U1_out <= A XOR B;

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67ECE 448 – FPGA and ASIC Design with VHDL

Structural Architecture in VHDL 87ARCHITECTURE structural OF xor3_gate ISSIGNAL U1_OUT: STD_LOGIC;

COMPONENT xor2 PORT(

I1 : IN STD_LOGIC; I2 : IN STD_LOGIC; Y : OUT STD_LOGIC

);END COMPONENT;

BEGINU1: xor2 PORT MAP (I1 => A,

I2 => B, Y => U1_OUT);

U2: xor2 PORT MAP (I1 => U1_OUT,

I2 => C, Y => Result);

END structural;

ABC

Resultxor3_gate

I1I2

Y I1I2

Y

U1_OUT

PORT NAME

LOCAL WIRE NAME

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68ECE 448 – FPGA and ASIC Design with VHDL

xor2

LIBRARY ieee;USE ieee.std_logic_1164.all;

ENTITY xor2 ISPORT( I1 : IN STD_LOGIC;

I2 : IN STD_LOGIC; Y : OUT STD_LOGIC);

END xor2;

ARCHITECTURE dataflow OF xor2 ISBEGIN

Y <= I1 xor I2;END dataflow;

xor2.vhd

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69ECE 448 – FPGA and ASIC Design with VHDL

Structural Architecture in VHDL 93

ARCHITECTURE structural OF xor3_gate ISSIGNAL U1_OUT: STD_LOGIC;

BEGINU1: entity work.xor2(dataflow)

PORT MAP (I1 => A, I2 => B,

Y => U1_OUT);

U2: entity work.xor2(dataflow) PORT MAP (I1 => U1_OUT,

I2 => C, Y => Result);

END structural;

ABC

Resultxor3_gate

I1I2

Y I1I2

Y

U1_OUT

PORT NAME

LOCAL WIRE NAME

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70ECE 448 – FPGA and ASIC Design with VHDL

Structural Description

• Structural design is the simplest to understand. This style is the closest to schematic capture and utilizes simple building blocks to compose logic functions.

• Components are interconnected in a hierarchical manner.

• Structural descriptions may connect simple gates or complex, abstract components.

• Structural style is useful when expressing a design that is naturally composed of sub-blocks.

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71ECE 448 – FPGA and ASIC Design with VHDL

Behavioral Architecture (xor3 gate)

ARCHITECTURE behavioral OF xor3 ISBEGINxor3_behave: PROCESS (A, B, C)BEGIN

IF ((A XOR B XOR C) = '1') THENResult <= '1';

ELSEResult <= '0';

END IF;END PROCESS xor3_behave;END behavioral;

Page 72: George Mason University ECE 448  FPGA and ASIC Design with VHDL VHDL Refresher Lecture 2

72ECE 448 – FPGA and ASIC Design with VHDL

Behavioral Description

• It accurately models what happens on the inputs and outputs of the black box (no matter what is inside and how it works).

• This style uses PROCESS statements in VHDL.

Page 73: George Mason University ECE 448  FPGA and ASIC Design with VHDL VHDL Refresher Lecture 2

73ECE 448 – FPGA and ASIC Design with VHDL

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