vhdl lecture series-i

8/6/2019 VHDL Lecture Series-I

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VERYHIGH SPEED INTEGRATED CIRCUIT

HARDWARE DESCRIPTION LANGUAGE

LECTURE - I

Presented By :Parag Parandkar

Assistant Professor,

Chameli Devi School of Engg., KhandwaRoad, Indore (M.P.), India 452020

Email: [email protected],[email protected]

Contact: +919826139931


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ACKNOWLEDGEMENT

The Presenter would like to thank and

acknowledge the power point presentation

slides of VHDL A Comprehensive tutorial

by anonymous.


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CONTENTS COVERAGE

Introduction System design approach with HDLs

History of VHDL

Why VHDL ?

Simulation Fundamentals

Simulation Cycle

Digital Simulator

Modeling of Hardware Language Basics

Building Blocks in VHDL

Design Units and Libraries


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INTRODUCTION

System Design Approach with HDLs HDL is mostly related to the front end part of the

design flow where a system is described withprogramming language constructs.

A complex system can be easily decomposed intosmaller pieces : improves modularity

Allows a design to be simulated and synthesizedbefore being manufactured.

Eliminates hardware prototyping expenses

Reduces design time

Increases design reliability at lower costs/time

req.


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INTRODUCTION(CONTD.)

Typical Design flowAlgorithm

HDL Description (Behavioral)

Register Transfer Level

simulation and

verification

Synthesizer

Structural Description

Physical Layout

Technology mapping (with ready-made primitives)

+ Floor Planning

Level of

abstraction


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INTRODUCTION(CONTD.)

Why VHDL ?

Public Availability

Developed initiated under Government Contract

Now is an IEEE standard

Design Methodology and Design TechnologySupport

Technology and Process Independent

Wide Range of Descriptive capabilities

Digital System (e.g. box) level to gate level

Capability of mixing descriptions

Design Exchange

Large Scale Design and Design re-use


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SIMULATION FUNDAMENTALS

Purpose of simulation is to verify the behavior ofa system by applying stimulation at the inputsand monitoring the response of the system over aperiod of time.

There are three types of simulators : Purely analog simulator.

A simulator with both digital and analog simulation capabilities.

Purely digital simulator.

In digital simulation only logic level of the

measured quantity is determined; no precisevalue is required.

In analog simulation the precise values of themeasured quantities are determined


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SIMULATION FUNDAMENTALS(CONTD.)

The system is described with a HardwareDescription Language (HDL). The design

contains a number of concurrently operating

blocks connected with each other by signals.

Maintains node values at logic level.

Maintains a time wheel to model propagation of

time.

Evaluates circuit behavior at intervals of time.

The interval is chosen as the smallest unit of time

after which a node can change its state.


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MODELING HARDWARE

The VHDL Language

A language for describing digital and analogsystems.

Makes no assumptions about the technology. Multiple levels of abstraction for modeling

BehavioralStructuralDataflowMixed

Behavioral model, timing model and structuralmodel are integrated. A VHDL process models a block and a VHDL

signal models the connection between different

blocks.


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STRUCTURAL MODEL

Digital circuits consist of components andinterconnection between them.

A component can in turn be composed of sub-

components and their interconnections.

A component interacts with other components

through pins.

Component is modeled as entity.

Component pins are modeled as ports.

Interconnections between components are

modeled as signals.


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BEHAVIORAL MODEL

The behavior of a component is modeled insidean architecture body of the entity

It may be described using a collection ofconcurrently executing statements

A concurrent statement is sensitive to a set ofinput signals and is executed whenever any of itssensitive signal changes its value

A concurrent statement called process statementcan contain one or more sequential statements

A set of sequential statements can be clubbedtogether in a subprogram


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DATAFLOWMODEL

The flow of data through the entity is modelledprimarily using concurrent signal assignmentstatements.

The structure of the entity is not explicitly

specified but it can be implicitly deduced. Architecture MYARCH of MYENT is

begin

SUM


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ASIMPLE EXAMPLE

entity Xor_gate isport (in1, in2 : in bit; Out1 : out bit);

end Xor_gate ;

architecture behavioral of Xor_gate is

begin

process

begin

Out1


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VHDL LIBRARIES DESIGN UNITS

A VHDL library is a host dependent storage facility forintermediate-form representations of analyzed designunits

A design unit is a VHDL construction that can beindependently analyzed and stored in a design library. A

design unit may be a primary or a secondary one. Primary design unit

entity decl, package decl and configuration decl

Secondary design unit

architecture body and package body In a library, there can be only one primary unit of samename but there can be multiple secondary units by samename

A secondary unit can have name same as primary unit


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BUILDING BLOCKS IN VHDL

Entity Declarationgeneric, port, declarations, statements

Architecture Bodydeclarations, statements

Subprogram Declarationparameter - list Subprogram Specificationdeclarations statements

Package Declarationsdeclarations

Package Bodiesdeclarations, subprogram body


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ENTITY

provides a name to the component

contains the port definitions in the interface

list

can contain some generic definitions which

can be used to override default values entity identifieris

generic interface_list;

port interface_list;

declarations

begin

statements

end [entity] [identifier];


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EXAMPLE

entity Adder is

port ( A : in Bit;

B : in Bit;Sum : out Bit;

Cout : out Bit );

end Adder;

Adder

Sum

Cout

A

B


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ARCHITECTURE

encapsulates the behavior and timinginformation

contains a number of concurrent statements

there can be multiple architecture bodies for a

given entity

architecture identifier of entity_name is

declarationsbegin

statements

end [architecture] [identifier];


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EXAMPLE-1

architecture Behavioral_Desc ofAdder is

begin

process (A, B)Sum


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EXAMPLE-2

architecture Struct_Desc ofAdder is

-- declarationscomponent Or_Comp

port ( X: in Bit; Y: in Bit; Out: out Bit);

end component;

componentAnd_Compport ( X: in Bit; Y: in Bit; Out: out Bit);

end component;

begin

-- component instantiationsA1: Or_Comp port_map ( X=> A,y =>B,Out=> SUM);

B1: And_Compport_map ( X=> A,y =>B,Out=> Cout);

end Struct_Desc;

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