lecture 1 - introduction to vhdledaasic/roosta/lecture 1.pdfintroduction to vhdl ee 595 eda / asic...

EE 595

Part IIntroduction to VHDL

EE 595 EDA / ASIC Design Lab

What is VHDL?

VHDL is a programming language that has been designed and optimized for describing the behavior of digital circuits and systems.


What is VHDL? (cont‘d)VHDL (VHSIC (Very High Speed Integrated Circuits) Hardware Description Language) is becoming increasingly popular as a way to capture complex digital electronic circuit for both simulation and synthesis.

Digital circuits captured using VHDL can be easily simulated, and more likely to be synthesized into multiple target technologies, and can be archived for later modification and reuse.

VHDL is a rich and powerful language.


VHDL Language FeaturesVHDL has all the characteristics of a modern “programming” language

Data types: predefined and user definedVariables, Signals, and constantsExpressions: relational, logical, arithmetic, constructionSequential Statements:

If, Case, For loopSubprograms

Concurrent Statements:Signal assignment, Concurrent processes, Component instances

PackagesConfigurationsDynamic memory allocationFile and input/output statements.


Additional Benefits of VHDLAllows for various design methodologiesProvides technology independenceDescribes a wide variety of digital hardwareEases communication through standard languageAllows for better design managementProvides a flexible design languageHas given rise to derivative standards: VITAL, Analog VHDL


Goals of LanguageSimulate-able specification for re-procurementStandard format to exchange designs between companiesMulti-vendor supportSupport for huge designsDetermine behavior


VHDL Versus ProgrammingDesigning in VHDL is like programming in many ways. Compiling and running a VHDL design is similar to compiling and running other programming languages. First, the source design units are read by the compiler, error messages are given by analyzer, and an object module is produced and placed in a special VHDL library. Subsequently, a simulation run is made, in which the object units from a library are selected (configured) and loaded into a simulator. A set of test cases are run, either in batch or interactive mode. The main difference is that a VHDL design is always running in simulated time, and events occur in successive time steps.


DifferencesDifferences

• The notation of delay and the simulation environment• Concurrency, and component netlisting } Not common in

programming languages

VHDL Versus Programming (cont’d)

A real hardware adder runs all the time, a design language needs a way of specifyingconcurrent behavior (to represent the adder running in parallel with other simulatedhardware elements.) VHDL supports concurrency using the concept of concurrentstatements running in a simulation time; while concurrency is getting morecommon, simulation time is a feature found only in simulation languages. In VHDL,there are also sequential statements to describe algorithmic behavior.

Some programming languages provide for design hierarchy by having one mainProgram and separately compiled subprograms. In VHDL, design hierarchy isaccomplished by separately compiled components that are instantiated in a higher-level component. The linking process is done via the compiler, or by a simulatorusing a VHDL library mechanism.

VHDL has a configuration capability for generating design variations.


VHDL HistoryVery High Speed Integrated Circuit (VHSIC) Program

Launched in 1980Aggressive effort to advance state of the artObject was to achieve significant gains in VLSI technologyNeed for common descriptive language$17 Million for direct VHDL development$16 Million for VHDL design tools

Woods Hole WorkshopHeld in June 1981 in MassachusettsDiscussion of VHSIC goalsComprised of members of industry, government, and academia


VHDL History (cont’d)In July 1983, a team of Intermetrics, IBM and Texas Instruments were awarded a contract to develop VHDLIn August 1985, the final version of the language under government contract was released: VHDL Version 7.2In December 1987, VHDL became IEEE Standard 1076-1987 and in 1988 an ANSI standardIn September 1993, VHDL was restandardized to clarify and enhance the languageVHDL has been accepted as a Draft International Standard by the IEEE.


IEEE Standard 1076-1987In 1986, the IEEE was presented with a proposal to standardize thelanguage, which it did in 1987 after substantial enhancements andmodifications were made by a team of commercial, governmentand academic representatives. The resulting standard, IEEE 1076-1987, is the basis for virtually every simulation and synthesisproduct sold today. An enhanced and updated version of language,IEEE 1076-1993, was released in 1994, and VHDL tool vendorshave been responding by adding these new language features toTheir products.


IEEE Standard 1164Although IEEE standard 1076 defines the complete VHDL language, there are aspects of the language that make it difficult to write completely portable design descriptions (descriptions that can be simulated identically using different vendor’s tools).WHY? VHDL supports many abstract data types, but does not directly address the problem of characterizing different signal strengths or commonly used simulation conditions such as unknowns and high-impedance.


IEEE Standard 1164 (cont’d)To get around this problem of non- standard data types, another standard was developed by the committee and adopted by the IEEE. This standard, numbered 1164,defines a standard package (a VHDL feature that allows commonly used declarations to be collected into an external library) containing definitions for a standard nine-valued data type. This standard data type is called standard logic, and the IEEE 1164 package is often referred to as the standard logic package, or sometimes MVL9 (for multi-valued logic, nine values).


VITAL InitiativeThe VITAL initiative (VHDL Initiative Toward ASIC Libraries) effort to enhance VHDL’s abilities for modeling timing in ASIC and FPGA design environments.VITAL borrows liberally from existing methods for timing annotation used in Verilog HDL. Specifically, the VITAL standard (standard 1076.4)Describes a method for annotating delay information using the same underlying tabular format as specified in Verilog.The adoptance of this standard will make it much easier for ASIC and FPGA vendors to create timing-annotationnetlists and detailed behavior of devices.


Top Down Design In Top-Down Design methodology, designer represents a system abstractly at first, and later in more detail. A VHDL description can be written at various levels of abstraction:

AlgorithmicRegister Transfer Level (RTL)Gate Level functional with unit delay(structural)Gate Level with detailed timing


Top Down Design (cont’d)VHDL provides ways of abstracting a design, or “hiding” implementationdetails.

The algorithm can be evaluated in real(floating point), and later can beImplemented in fixed-point integer.(i.e. Designers often choose integers with 16 bits, but theseimplementation decisions can be changed during a VHDL design cycle.)

In the previous example, addition is specified for 8-bit data. In actuality,the + in this example might be a function call to user-written function calledplus (+). VHDL calls this technique operator overloading. Overloading isanother example of information hiding, which is convenient for the readerand allows the design author to describe exactly what kind of operator iswanted (+).


VHDL Design Steps


BehavioralSimulation

RTL LevelSimulation

SynthesizeableRTL

Gate LevelImplementation

Gate LevelSimulation

Regression Test

Experiment with alternate implementations and verify function

Experiment with alternate functionality

Identity requirements -capacity & performance

Design Descriptionin VHDL

SimulationA design description or model, written in VHDL, is usually run through a VHDL simulator to demonstrate the behavior of the modeled system. Simulating a VHDL design model requires simulated stimulus, a way of observing the model during simulation, and capturing the results of simulation for later inspection. Designer usually creates a set of test cases, for inputs and expected results, to verify the function of the design. This file is called Testbench. For the previous ADDER example, we would provide a set of functional test vectors as:

The simulator would run to cover at least 5 ns of simulation time, and we could observe the output on the A bus:


at simulated time 0: B= “0000 0010”C= “0000 0010”

at simulated time 0: B= “0000 0010”C= “0000 0010”

A = “0000 0100” A = “0000 0100”

Simulation (cont’d)Logic simulator systems need to represent undefined or “unknown” valuesfor circuits with unresolved electrical values or states, which might be theoutput of this circuit model during the first 4 ns of simulation time. Accordingly, VHDL supports a variety of data types useful to the hardwaremodeler for both simulation, and synthesis, as well as bits, booleans, andnumbers, which are defined in the Package STANDARD.

During simulation, the ADDER example is modeled on a computersystem, where the values on the busses are stored in the computer’smemory. Hence, A, B, and C are similar to variables in programminglanguages that change value over the time, and can be observed while theprogram is running.


Logic SynthesisSome parts of VHDL can be used with logic synthesis tools for producing aphysical design. In particular, many VLSI gate-array vendors can converta VHDL design description into a gate level netlist from which acustomized integrated circuit component can then be built. Hence theapplication of VHDL is for:

• Documenting a design• Simulating the behavior of a design• Directly synthesizing logic

The ADDER is an abstraction of a real adder circuit, which might havevarying delays that are dependent upon the data, or on whether an outputrises or falls. Although a logic synthesis tool could generate an 8-bit addercircuit, it could not produce an ideal adder with exactly 5.0 ns delay for allcases. Only the addition function (not the delay specification) of thestatement in the example could be synthesized into a physical device. (Delays and time specifications are ignored in Logic Synthesis.)


lecture 1 - introduction to vhdledaasic/roosta/lecture 1.pdfintroduction to vhdl ee 595 eda / asic...

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