VHDL Lecture

CP323L1Advanced Logic Circuit

Engr. Rommel A. Manalo,CpE DepartmentVHDL LectureIntroduction to VHDLVHDL is a language for describing digital hardware used by industry worldwideVHDL is an acronym for VHSIC (Very High Speed Integrated Circuit) Hardware Description Language

A VHDL description of a digital system can be transformed into a gate level implementation. This process is know as synthesis.A Brief History of VHDLJune 1981: Woods Hole WorkshopJuly 1983: contract awarded to develop VHDLIntermetricsIBMTexas InstrumentsAugust 1985: VHDL Version 7.2 releasedDecember 1987: VHDL became IEEE Standard 1076-1987 and in 1988 an ANSI standardFour versions of VHDL:IEEE-1076 1987IEEE-1076 1993 most commonly supported by CAD toolsIEEE-1076 2000 (minor changes)IEEE-1076 2002 (minor changes)VerilogEssentially identical in function to VHDLNo generate statementSimpler and syntactically differentC-likeGateway Design Automation Co., 1983Early de facto standard for ASIC programmingOpen Verilog International StandardVHDL vs. Verilog

Example Code:

VHDL Design Flows

ASIC versus FPGA

What is an FPGA Chip ?

VHDL Design StylesComponents andinterconnectsstructuralVHDL Design StylesdataflowConcurrent statementsbehavioral(sequential) Registers State machines Instruction decodersSequential statements TestbenchesLevels of VHDL Design

Levels of Design Description

Register Transfer Logic (RTL) Design Description

VHDL Fundamentals

Fundamental parts of a LIBRARY

VHDL - Basic TerminologyVHDL is a hardware description language that can be used to model a digital system Entity: A hardware abstraction of a digital system Component:An entity used by another entityExample: when an entity X used in another entity Y, then X become a component for the entity Y. Design units: VHDL provides five different types of primary constructs to describe an entity1. Entity declaration2. Architecture body3. Configuration declaration4. Package declaration5. Package bodyVHDL - Basic TerminologyEntity declaration: describes the external view of the entity.Example: input and output signal names Architecture body: contains the internal description of the entityExample: a set of interconnected components that represents the structure of the entity or a set of concurrent or sequential statements that represents the behavior of the entityEach architecture body can be represented by - one style or- mixed style of representationCase SensitivityVHDL is not case sensitiveExample:Names or labelsdatabusDatabusDataBusDATABUSare all equivalentNaming and LabelingGeneral rules of thumb (according to VHDL-87)1. All names should start with an alphabet character (a-z or A-Z)2. Use only alphabet characters (a-z or A-Z) digits (0-9) and underscore (_)3. Do not use any punctuation or reserved characters within a name (!, ?, ., &, +, -, etc.)4. Do not use two or more consecutive underscore characters (__) within a name (e.g., Sel__A is invalid)5. All names and labels in a given entity and architecture must be uniqueIdentifiersBasic identifiers are made up of alphabetic, numeric and/or underscore characters.The first character must be a letter.The last character can not be an underscore.Two underscores in succession are not allowed.VHDL reserved words such as entity, is, architecture should not be used as identifiers.Upper and lower case letters are equivalent when used in identifiers. The following are equivalent:Clk, clk, CLK, clKReserved Keywords:

Examples:Identify the legal identifiers_tx_clk?No. must start with a letter.Tx_clk?Yes. A legal identifier.6A15X?No. can not start with a number.Big#buffer?No. Can not have # in identifier.Examples:Select?No. Reserved word.tx_clk_?No. The last character can not be an underscore.ABC_456?Yes. A legal identifier.Tx__clkNo. Two underscores in succession not allowed.

VHDL is a Free FormatVHDL is a free format languageNo formatting conventions, such as spacing or indentation imposed by VHDL compilers. Space and carriage return treated the same way.Example:if (a=b) thenorif (a=b) thenorif (a =b) then

are all equivalentVHDL CommentsComments in VHDL are indicated with a double dash, i.e., --Comment indicator can be placed anywhere in the lineAny text that follows in the same line is treated as a commentCarriage return terminates a commentNo method for commenting a block extending over a couple of linesExamples:-- main subcircuitData_in