non-idealities of switched capacitor filter design

7/29/2019 Non-Idealities of Switched Capacitor Filter Design

1/19

Non-Ideal Effects in Switched-Capacitor Filter

Hari Prasath

March 11, 2009
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2/19

Non-Ideal Switch

Charge Injection and Clock-Feedthrough

Switch-Performance

Opamp Offset Voltage

Finite Gain,BandwidthFinite Bandwidth

Slew Rate

CDS

CLS
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3/19

VinRon Ron

Ron Ron

C

VinC

1

2 1

1

1

2

2

2

+

C

+

C

Figure: Switch Model

H(z) = (1 eT

4RonC )2Z1

1 Z1

Reference:

Analog MOS Integrated Circuits for Signal Processing- Roubik Gregorian and Gabor C. Temes.
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4/19

Vin Vin

Vin Vin

Vdd

Vdd

Cboot

C

C

CC

C

1

1

1

1

1

1

11b 1b

1b

1b

1b

1b1b

1b

Vin

Sampling Switch

Figure: Different Sampling Switches
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5/19

Switch - Performance

A single tone at3

64 fs. 64-point DFT was performed at theoutput of each switch.Switch 2nd(dB) 3rd(dB) 4rd (dB) 5th(dB)

NMOS + Dummy -47.2 -58.23 -70.432 -81.7Trans + Dummy -65.2 -86.5 -94.6 -94.8

Bootstrap + Dummy -86.08 -109.7 -118.8 -114.1

Vinj,error =15L2fc

= 0.825mV

Overlap capacitance estimate is 0.43 fF. For a 600 fF capacitorClock-Feedthrough 1 mV.
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6/19

Transient Response of Switches

2.36 2.37 2.38 2.39 2.4 2.41 2.42

x 107

0.946

0.948

0.95

0.952

0.954

0.956

0.958

0.96

Time in second(s)

Voltage(V)

Sample and Hold Output and Charge Injection

Input

Tx + Dummy

TxGate

NMOS

Bootstrap +Dummy

Bootstrap

NMOS +Dummy
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7/19

+

++

+Voff

Voff

Vin

Vo1Vo2

1 1

1

1

1

22

2

2

2 2

1

1C1

5C2

4C1

6C23C2

C1C2

Figure: Low Q Structure

VoffK1 + (Vo1 Voff)K4C1 = 0VoffK5 + (Vo1 Voff)K6 = Vo2K5

Reference: Analog MOS Integrated Circuits for Signal Processing

- Roubik Gregorian and Gabor C. Temes.


8/19

Filter Offset Voltage

Similar Calculation. Start from first opamp and move towards thefilter output.

Vo1 = (1 +C2

C3)Voff = 3mV

Vo2 = Voff = 1mV

Vo3 = VoffK1,2

K4,2(Vo1 Voff) = 0.254mV

Vo4 = (Vo5 Voff)K6,3

K5,3 Voff = 0.05mV

Vo5 = Voff K1,3K4,3

= 2.04mV

Ki,j represents the coefficient i in the section j.Reference: Analog MOS Integrated Circuits for Signal Processing

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9/19

Simulation Result

0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 2

x 106

4

3

2

1

0

1

2

3x 10

3

Time in second(s)

Voltage(V)

Steady State Filter Response with Opamp Offset

Vo1

Vo2

Vo3

Vo4

V05

2.95 mV

2.2 mV

0.254 mV

0.05 mV

1 mV

Figure: Individual Stage Offset Voltage


10/19

Effect of Finite Gain

+

C1

C2

1

1

2

2

-V/A

Vin

V

C1 C2

1

2

Vin[n-1]C1 V[n-1](1+1/A)

C1

C2

V[n-1/2](1/A) V[n-1/2](1+1/A)C2

1 2 1 22

Figure: Finite Gain
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11/19

Finite Gain Effect continued..

Making an approximation Z 1 + sT, we get

H(s) =

C1C2T

s+ C1C2AT

s s+

Pre-Distort Poles to compensate for the gain error.DC-Gain of1000, 5 MHz passband and 100 MHz sampling rate gives anapproximate =

20000.

Pole Ideal Pre-Distorted

1,2 -0.0168

0.1650i -0.0160

0.1650i3,4 -0.0575 0.1151i -0.0570 0.1151i

5 -0.0848 -0.0840

Reference: Analog MOS Integrated Circuits for Signal Processing

http://find/


12/19

0.05 0.1 0.15 0.2 0.25 0.3

1.4

1.2

1

0.8

0.6

0.4

0.2

0

0.2

0.4

Normalized frequency rad/s

MagnitudeindB

Predistorted and Ideal Response

Figure: Predistorted and Ideal Response - Passband
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13/19

Effect of Finite Gain on Pole-Q

The effect of finite DC-gain changes s to s+. The Denominatorin the biquadratic transfer function changes to

s2 + (0Q

+ 1 + 2)s+ (2 +

01Q

+ 12)

Variation in Passband ripple due to variation in Q is

1 2 1

A0

Rp = 1 + 2QA0
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14/19

Finite Gain Effect Continued...

1 1.5 2 2.5 3 3.5 4 4.5

x 106

0.3

0.25

0.2

0.15

0.1

0.05

0

0.05

0.1

Frequency in Hertz

MagnitudeindB

Effect of Finite Gain

Increasing Adc
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15/19

Finite Bandwidth EffectFinite Gain and bandwidth effect is modelled for an Integrator.Single-pole amplifier is assumed with finite DC Gain.

Finite Bandwidth causes signal dependant settling error.

Vo(Z)

Vi(Z)=

1

1 Z1

Vo(Z)

Vi(Z)=

1

1 (1 1Adc)Z1

Where = (1 k(1 e0T/2))e0T/2,k=feedback factor. 0 -unity gain bandwidth.

0T

2 1

Reference: Finite Amplifier Gain and Bandwidth Effects inSwitched-Capacitor Filters. Gabor C. Temes. JSSC, Vol. SC-15,No :3, June-1980.
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16/19

Figure: Effect of Finite Bandwidth

Eff f Sl R
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17/19

Effect of Slew-RateMaximum Slope based Slew-Rate limit

Sr 0.3V/ns

5.1 5.12 5.14 5.16 5.18 5.2

x 107

0.44

0.46

0.48

0.5

0.52

0.54

0.56

0.58

0.6

0.62

Time in second(s)

MagnitudeinVoltage(V)

Effect of Slew Rate

Figure: Effect of Slew-Rate

CDS
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18/19

CDS

+

C2

C3

C1Vin

2

1

1

1

2

1

1

C1 C2 C3

Vin(n-1) +V0(n-1)/A V0(n-1)(1+1/A) V0(n-1)

V0(n-1/2)(1/A)2 V0(n-1)(1+1/A) V0(n-1/2)(1+1/A)

1 Vin(n) +V0(n)/A V0(n)(1+1/A) V0(n)

C

Figure: CDS-Integrator

Reference: Switched-Capacitor Integrators with Low Finite-GainSensitivity. K. Haug, F. Maloberti and Gabor C. Temes.

C l t d L l Shifti I t t
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19/19

Correlated Level Shifting Integrator

+

VinC1

C2

CCLS

Sample

+

C2

CCLSC1

Estimate

+

C2

CCLSC1

Level Shift

non-idealities of switched capacitor filter design

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