ECE 626 Project – Design of Switched Capacitor Low Pass Filter

by Karthikvel Rathinavel

In partial fulfillment of the requirements for the course of ANALOG CMOS INTEGRATED CIRCUIT DESIGN

Winter 2016

Department of Electrical Engineering and Computer Science Oregon State University

Corvallis March, 2016

Introduction: In this report, a technique to design a Switched Capacitor low pass filter is described. The switched-capacitor low pass filter was required to meet certain specifications. These specifications along with the simulated specifications is shown in Table 1. A switched capacitor filter is a replacement of a traditional RC circuit for the discrete domain. Instead of using resistors a pair of switches is placed between a capacitor. Due to the sample and hold nature of the switched capacitor, the transfer function will be in z-domain. The equivalent transfer function in the S domain can be closely modelled by performing bilinear transformation.

Parameter Required Specifications Simulated Specifications Sampling Frequency 60 MHz 60 MHz

DC Gain 0 dB 0 dB Passband 0 – 3.6 MHz 0 – 3.6 MHz

Ripple in passband < 0.2 dB < 0.14 dB Stopband 7.2 - 24 MHz 7.2 - 24 MHz

Gain in Stopband < - 50 dB < - 50 dB Minimum Capacitor Size 0.02 pF 0.02 pF

Table 1: Specifications of the Switch Capacitor Low pass filter 1. Design Approach: Using MATLAB, the poles, zeroes and transfer function of the low pass filter was obtained for the desired specifications. For the initial design we choose for that type of filter, which gave the least order (in this case elliptical). Next the initial design for a fifth order filter was setup in Cadence. It was observed that for ideal op-amps and ideal switches, the passband ripple and stop band attenuation was not met. Thus the design was modified by re-calculating the filter coefficients for a smaller passband ripple and more attenuation in the stop band, such that the response of the filter met all the specifications. Next dynamic range optimization, followed by dynamic range scaling and chip area scaling was done. 1.1 Code used to find the Transfer function and Order of the filter: MATLAB Code used to find the order, transfer function, poles, and plot the zeroes and poles in the Z plane:

Figure 1: MATLAB Code for finding the transfer function, poles and zeroes and looking at the frequency response

The order of different type of filters (Chebyshev1, Chebyshev2, Butterworth, and Elliptical), was observed in MATLAB. Order of different filters for the same specifications: Chebyshev1= 6 Chebyshev2 = 6 Butterworth = 10 Elliptical = 5 It can be seen that Elliptical gave the lowest order (five). The transfer function was also computed in MATLAB for this elliptical filter. This is given as:-

0.003666 0.006399 0.004003 0.0040036 0.006399 0.0036664.226 7.336 6.515 2.956 0.5472

After pairing the poles and zeroes the, transfer function can be simplified as follows:

0.1546680374 10.8036

1.58946 0,999997091.7646 0.0.9160201

1.1564 1.00001.658 0.74336261

Poles and zeroes are shown below:-

Figure 2: The location of poles and zeroes in the z domain

1.2 Frequency Response: The overall frequency response was plotted in MATLAB for the initial design. It was seen that all the specifications for stopband and passband were comfortably met for an ideal case. This plot of the overall transfer function served allowed for ease in debugging any errors in the realization of the filter in Cadence, because it allowed us to compare the filter response against the response in realized filter in Cadence.

Figure 3: MATLAB frequency response of the low pass switched cap filter

Below is the zoomed in passband of the initial filter response in MATLAB. It was observed that the passband ripple was within the range of 0.2 dB. It was also seen that the stopband attenuation was lower than -50dB in the stopband frequency range.

Figure 4: Zoomed in Passband of the frequency response of the low pass switched cap filter

1.3 Pairing of poles and zeroes For grouping of poles and zeroes, we select the dominant pole which has highest Q (closest to unit circle) and group it with the closest zero such it dampens the peaking. We do that for the conjugate pole as well. Thus the dominant pole is paired with the nearest zero, which is seen from the pole zero plot in the Z domain

0.154668037413 1

0.8036 0.1546680374 1.58946 0,99999709

1.7646 0.0.9160201

0.1546680374 1.1564 1.00001.658 0.74336261

1.4 Selecting the order of arrangement of different Stages: Since the bilinear section will filter out the noise, the bilinear section of the entire filter is used as the first stage. Next by design standards the high Q is placed in the middle followed by the low Q section. Thus the order is as shown in figure above (figure 4).

Figure 5: Order of arrangement of different stages

1.4 Macro models of Ideal Components: Each of the macro-models for the ideal op-amps and the switches were based on the below shown schematics Ideal Op-Amp:

Figure 6: Ideal Op-Amp Macro Model with very high gain (80dB) and large bandwidth

1.5 Ideal Switch:

Figure 7: Ideal Switch Macro Model

1.6 Clock Pules: The transient analysis of the clock pules is shown below. These two clock pulses were given with a delay from each other such that there was no overlapping.

Figure 8: Non-Overlapping Clocks

2. Realization of Switched Capacitor Low Pass Filter in Cadence: The figures 9-12 shows the architecture of the filter realization.

Figure 9: Overall Filter

2.1 Bilinear Section:

Figure 10: Bilinear Section

2.2 High Q Biquad:

Figure 11: High Q Stage 2.3 Low Q Biquad:

Figure 12: Low Q Stage

3. Initial Design Capacitance: As found using initial design capacitances from the individual transfer functions. 3.1 Initial Bilinear Section:

Initial Capacitance Values (fF) 192.4689365 384.937873 244.00199 1000

Table 2: Initial Capacitances for Bilinear Section

3.2 Initial High Q Stage

Table 3: Initial Capacitances for High Q Biquad

3.3 Initial Low Q Stage

Table 4: Initial Capacitances for Low Q Biquad Section

Initial Capacitance Values (fF) 163.2028564 0 154.6680374 389.127357 389.127357 215.8159751

1000 1000

Initial Capacitance Values (fF) 517.9680193 0 208.0653981 338.8702841 338.8702841 345.238497

1000 1000

4. Scaling Capacitors: In order to have a high output swing of each stage and reduce the chip area, scaling of all the capacitors in the filter was done in the following order:

Figure 13: Order of the Scaling done for the Filter 4.1 Dynamic Range Optimization: The output of each stages are required to have no gain, such that we get maximum possible output swing. Dynamic Range optimization is done to so that we get maximum possible output swing. Steps to perform dynamic range optimization for a three stage filter: (1) Look at the highest peak gain of first stage, convert that number into absolute value (say that number is K1). (2) Multiply the numerator of the first stage by 1/K1. Such that the peak of the first stage now becomes 1 (0db). (3) Typically multiplying a constant number in any stage causes scaling the input transistors in that stage. (4) Repeat steps 1-3 for the second stage with the updated first stage. Let’s say we multiplied by a constant

number 1/K2 in the second stage. (5) Since the individual cascaded transfer functions are linear blocks, multiplying by 1/K 1/1K2 in the first and

second stage respectively, causes a scaled output factor in the final output. Thus we multiply a factor of K1K2 in the third stage so that the overall output transfer function gain peak is not affected.

Figure 14: Dynamic Range Optimization for Each Stage

Figure 15: Filter Response after Dynamic Range Optimization for Each Stage

4.2 Dynamic Range Scaling

Figure 16: Filter Response after Dynamic Range Scaling of Each Amplifier’s Output

As seen above the peaking of each amplifier’s output is made to be equal to 0 dB, thus the overall output swing is made large. Before any scaling the response of each amplifier is shown below

Figure 17: Response of Each Stage before Dynamic Scaling

4.3 Chip Area Scaling: Capacitors occupy large area when they are laid out on a chip. Therefore in order to lower the area on chip we do chip area scaling. In addition to lowering the area on chip area, impedance level scaling or chip area scaling, also lowers the noise. Chip area scaling is done by finding the smallest capacitance connected to the input node of the op-amp and setting it to the minimum allowable capacitance. Next all the other capacitances connected to the input node (for that stage) are scaled according to the ratio of the scaled factor for the smallest capacitance. This process is repeated for all the stages including the bilinear stage. The output response does not change after performing chip area scaling. It was noticed that multiplying all the capacitances by a scaling factor to the entire stage instead of only multiplying to the input node connected capacitances, had no effect to the overall transfer function as well. Thus this would further decrease area on chip. The output response for each op-amp is shown below.

Figure 18: Response of Each op-amp after Chip Area Scaling

Figure 19: Zoomed in Response of Each op-amp in the passband after Chip Area Scaling

Figure 20: Final Response of overall filter after Chip Area Scaling for Ideal components

5. Final Capacitance values After Scaling: 5.1 Bilinear Section:

Capacitance Dynamic Range Scaling (f F) Chip Area Scaling (f F) 122.028324 20 244.0566481 40 244.0566481 39.99104175 1000 163.8963754

Table 5: Final Capacitances for Bilinear Section 5.2 High Q Stage

Table 6: Final Capacitances for High Q Biquad

Capacitance Dynamic Range Scaling (f F) Chip Area Scaling (f F) 294.1628033 25.01725541 0 0 278.779333 23.70895877 389.17357 33.09750414 424.0199244 36.06103364 235.1679259 20f

1089.66876 92.67154573 1000 85.04561123

5.3 Low Q Stage

Table 7: Final Capacitances for Low Q Biquad 6. Non-Idealities: So far we have been using ideal components such as high gain (80dB) and very high bandwidth (43.84 GHz) for op-amps and ideal switches, no offset etc. This section demonstrates the impact of non-idealities such as finite gain, finite bandwidth, charge injection, parasitic capacitors and slew rate etc. 6.1 Finite gain: After setting the gain to a small number such as 20 dB (or 10 in absolute value) instead of 80 dB, we observe the overall response of the filter. This is shown in the figure below.

Figure 21: Response of filter with finite gain

Capacitance Dynamic Range Scaling (f F) Chip Area Scaling (f F) 274.2959822 49.7889629 0 0 110.1834488 20 338.8702841 61.51019736 188.7158975 34.25485398 192.2623371 34.89858762

556.897156 101.0854465 1000 181.5154655

6.2 Finite Bandwidth and Finite Gain: Finite bandwidth (396 MHz) was used in our op-amps by selecting a larger value for the capacitance shown in the figure below. This will bring the pole (dominant pole) closer and thus reducing the bandwidth of the amplifier.

Figure 22: Finite Gain (40db) and Bandwidth (396 MHz) Op-Amp

Note that the capacitance is 200 pF for this non-ideal op-amp. The overall response of the entire filter for finite bandwidth op-amps is shown in the figure below:

Figure 23: Response of filter using Finite Bandwidth Op-amp Next we replace the macro model with a finite bandwidth amplifier by increasing the capacitance to 1/fs order of magnitude to observe the sole dependence of bandwidth (only) on the performance.

Figure 24: Response of filter for different values of capacitances (100n, 200n, 400n, 800n) for Finite Bandwidth Op-amp 6.3 Offset Voltage: By adding an offset voltage of 2 mV to one inputs of all the op-amps the output voltage will take a longer time to settle. This can be seen by running a transient analysis, as shown below. However the frequency response will not change.

Figure 25: Transient response of filter with offset voltage (2mV)

Figure 26: Transient response of filter with different offset voltages (1mV, 2mV, 3mV, 4mV)

In Figure 26, the different transient responses of the filter for different offset voltages (1mV, 2mV, 3mV, 4mV) is shown. When we do not have an offset voltage in our amplifier, the transient response doesn’t have to settle. This is shown for an ideal case in the figure below.

Figure 27: Transient response of filter without any offset voltage (Ideal Case)

6.4 Slew Rate: The non-ideality, slew rate is caused as a result of the amplifiers’ maximum current output. Slew rate for an op-amp with a sinusoidal input voltage is given by:-

By increasing the maximum current output for the amplifiers’ we can observe the effects of slew rate for a sine wave. In the figure below, the transient response of filters’ output demonstrates the effect of slew rate for a sine wave input to the filter.

Figure 28: Transient response of filter output for Op-amp having Slew Rate

It was seen from the simulations that the sample and hold response had been shifted due to the addition of this type of non-ideality in the amplifier. Slew rate increases with the increase in the maximum current output of the op-amp till a certain point. Another conclusion that could be drawn from our observations, was that even with an ideal macro model there was some clock feed through in our output response. 6.5 Charge Injection: The ideal switch macro model was replaced with a NMOS Switch in order to observe the dependence of widths of the MOSFET switches to the filter response.

Figure 29: Non-Ideal NMOS Switch

Figure 30: Transient Response for different widths of the NMOS Switch

As seen above that with increasing size of the NMOS switch, the clock feed through increases and the there is more charge injection. Next we observe the frequency response of the filter for a non-ideal switch which has some charge injection. The passband ripple, is no longer within 0.2 dB as shown below for a NMOS switch.

Figure 31: Filter Response for NMOS Switch with 5u/240n device size

In order to lower the charge injection non-ideality, we can replace the NMOS Switch with a transmission gate switch. A transmission gate switch consists of a combination of a NMOS and a PMOS, is connected in such a way that when one switch turns on, the other turns off.

7. Self-Designed Op-Amp A fully differential amplifier was made in transistor level with a two stage architecture in order to achieve a high gain. The first stage being a telescopic amplifier and the second stage was a common stage amplifier. We observed that a high gain and non-ideal components led to an excellent response of the filter. Thus by approximating our op-amp such that it mimics the behavior of an ideal op-amp, we can realize the low pass filter.

Figure 32: Schematic for Designed Op-Amp in Transistor Level

Figure 33 Open loop characteristics of open loop Op-amp The amplifier’s open loop characteristics is shown in the figure above. Through the amplifier had a high gain of 72 dB. But due to low bandwidth, it could not be replaced with our ideal macro model to get the same frequency response.

References: [1] Tony Chan Carusone, David A. Johns, Kenneth W. Martin., “Analog Integrated Circuit Design,” 2nd ed.,(2012). [2] Romesh Kumar Nandwana, “Design of 5th Oder Elliptical Switched Capacitor Filter,” University of Illinois Urbana Champaign, Chicago, IL. [3] Hari Prasath Venkatram, “Switched Capacitor Filter Design,” School of Electrical Engineering and Computer Science, Oregon State University, Corvallis, OR. [4] Rishi Gupta, “Spectre Report,” School of Electrical Engineering and Computer Science, Oregon State University, Corvallis, OR. [5] Gabor C. Temes, “CMOS Active Filters,” School of Electrical Engineering and Computer Science, Oregon State University, Corvallis, OR.

Appendix: MATLAB Code: clear all clc fs=60e6; Wstop=7.2e6/(fs/2); Wpass=Wstop/2; Rp=0.14; Rs=52; %Oberserving Different Orders [Nbutt,Wnbutt]=buttord(Wpass,Wstop,Rp,Rs); [Ncheb1,Wncheb1]=cheb1ord(Wpass,Wstop,Rp,Rs); [Ncheb2,Wncheb2]=cheb2ord(Wpass,Wstop,Rp,Rs); %Choosing Elliptical Filter [N,W]=ellipord(Wpass,Wstop,Rp,Rs); [num,den]=ellip(N,Rp,Rs,Wpass); H=tf(num,den,1/fs); %Frequency response of the filter: [H,w]=freqz(num,den); plot(w/(2*pi)*(fs),20*log10(abs(H))); xlabel('Frequecy (Hz)') ylabel('Magnitude (dB)') %Plotting Zeroes and Poles [z,p,k]=tf2zpk(num,den); zplane(num,den); grid on