lecture 09 and 10 new.pdf

7/25/2019 Lecture 09 and 10 new.pdf

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VLSI Technology 1 BUE

15ELEC17HVLSI Technology

Fall 2015

Lecture 09-10: Semiconductor Memories

&ASIC/FPGA Flow

Dr. Hassan Mostafa

.

[email protected]

[Adapted from Rabaeys Digital Integrated Circuits, 2002, J. Rabaey et al.]


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Semiconductor Memory Classification

Read-Write MemoryNon-Volatile

Read-Write

Memory

Read-Only Memory

EPROM

E2PROM

FLASH

Random

Access

Non-Random

Access

SRAM

DRAM

Mask-Programmed

Programmable (PROM)

FIFO

Shift Register

CAM

LIFO


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Memory Architecture: Decoders

Word 0

Word 1

Word 2

Word n-1

Word n-2

Storage

Cell

m bits

S0

S1

S2

S3

Sn-2

Sn-1

Input/Output

n words n select signals

Word 0

Word 1

Word 2

Word n-1

Word n-2

Storage

Cell

m bits

S0

S1

S2

S3

Sn-2

Sn-1

Input/Output

A0

A1

Ak-1

Decoder reduces # of inputs

k = log2 n


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Array-Structured Memory Architecture

A0A1Aj-1

Sense Amplifiers

bit line

word line

storage

(RAM) cell

AjAj+1

Ak-1

Read/Write Circuits

Column Decoder

2k-j

m2j

Input/Output (m bits)

amplifies bit line swing

selects appropriate

word from memory row


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Hierarchical Memory Architecture

Input/Output (m bits)

Advantages:

1. Shorter word and/or bit lines

2. Block addr activates only 1 block saving power


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MOS NOR ROM

WL[0]

GND

BL [0]

WL [1]

WL [2]

WL [3]

VDD

BL [1]

Pull-up devices

BL [2] BL [3]

GND

All word lines LOW by default with exception of selected row


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MOS NAND ROM

All word lines high by default with exception of selected row

WL[0]

WL[1]

WL[2]

WL[3]

VDD

Pull-up devices

BL [3]BL [2]BL [1]BL [0]



Precharged MOS NOR ROM

PMOS precharge device can be made as large as necessary,but clock driver becomes harder to design.

WL[0]

GND

BL [0]

WL[1]

WL[2]

WL[3]

VDD

BL [1]

Precharge devices

BL [2] BL [3]

GND

pref



Read-Write Memories (RAM)

STATIC (SRAM)

DYNAMIC (DRAM)

Data stored as long as supply is applied

Large (6 transistors/cell)

Fast

Differential

Periodic refresh required

Small (1-3 transistors/cell)

Slower

Single Ended



6-transistor CMOS SRAM Cell

WL

BL

VDD

M5M6

M4

M1

M2

M3

BL

QQ



CMOS SRAM Analysis (Read)

WL

BL

VDD

M 5

M 6

M 4

M1 VDDVDD VDD

BL

Q = 1Q = 0

Cbit Cbit



CMOS SRAM Analysis (Read)

00

0.2

0.4

0.6

0.8

1

1.2

0.5

Voltage rise [V]

1 1.2 1.5 2

Cell Ratio (CR)

2.5 3

VoltageRis

e(V)



CMOS SRAM Analysis (Write)

BL = 1 BL = 0

Q = 0

Q = 1

M1

M4

M5

M6

VDD

VDD

WL



CMOS SRAM Analysis (Write)



6T-SRAM Layout

VDD

GND

QQ

WL

BLBL

M1 M3

M4M2

M5 M6



3-Transistor DRAM Cell

M1 M2

M3

X

BL1 BL2

WWL

RWL

X

Vdd-Vt

BL1

Vdd

WWL write

RWL read

BL2 Vdd V

No constraints on device sizes (ratioless)

Reads are non-destructive

Value stored at node X when writing a 1 is VWWL - Vtn

Cs



1-Transistor DRAM Cell

M1 X

BL

WL

X Vdd-Vt

WL write1

BL Vdd

Write: Cs is charged (or discharged) by asserting WL and BLRead: Charge redistribution occurs between CBL and Cs

Cs

read1

Vdd/2 sensing

Read is destructive, so must refresh after read

CBL



DRAM Cell Observations

1T DRAM requires a sense amplifier for each bit line, due to charge redistribution

read-out. DRAM memory cells are single ended in contrast to SRAM cells.

The read-out of the 1T DRAM cell is destructive; read and refresh operations are

necessary for correct operation.

Unlike 3T cell, 1T cell requires presence of an extra capacitance that must be

explicitly included in the design.When writing a 1 into a DRAM cell, a threshold voltage is lost. This charge loss

can be circumvented by bootstrapping the word lines to a higher value than VDD



ASIC/FPGA Design Flows



ASIC Design Flow

ASIC tools are generallydriven by scripts

Post-synthesis static timinganalysis and equivalencychecking are musts for

sign off to foundry

Verification of deep sub-micron effects (second-and third-order effects) is

required for ASICs Internal, deep sub-micron

effects are already verifiedfor Xilinx FPGAs



FPGA Design Flow

FPGA tools are generally

GUI-driven, pushbutton flows FPGA tools also have scripting

capabilities

After the design passes

behavioral simulation and statictiming analysis, verification iscompleted most efficiently byverifying in circuit

Static timing analysis is used to

verify timing of the design

Timing simulation is supported

This is a simplified/typical designflow



ASIC Implementation

Create HDL

Optimized for ASICtechnology and area

Synthesis

Primarily driven by scripts

Synopsys design compile Design for test logic insertion

(BIST, Scan, and JTAG)

Place & route

Foundry tools, Cadence,AVANT

BIST: Built-In Self Test

JTAG: Joint Test Action Group


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FPGA Implementation

Create HDL

Optimized for Xilinx FPGAs andperformance

Synthesis

Synopsys, Mentor

Pushbutton flow withscripting capabilities

Place & route

Completed by the user

Xilinx implementation tools

ISE software

Pushbutton flow, scripting capabilities


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ASIC Verification

Key ASIC verification points

Behavioral simulation*

Post-synthesis static timing analysis

Post-synthesis equivalency checking

Post-place & route static timing analysis*

Post-place & route equivalency checking

Post-place & route timing simulation*

Verification of second- and third-ordereffects

Verify in circuit*

* Applies to both FPGA and ASIC design flows


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FPGA Verification

Three key verification points for

FPGA implementation Behavioral simulation

Post-place & route static timinganalysis

Download and verify in circuit

Post-synthesis gate-levelsimulationand post-place & route timingsimulations can be done for

production sign off Post-place & route timing

simulations are also often doneto verify board- and system-leveltiming


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Deep Sub-Micron Effects

Second- and third-order effects

Silicon-induced design flaws due tothe small wire delays and narrowsilicon of deep sub-micron processes

They include cross talk, interconnectdelays, and Process variations

Xilinx FPGAs inherently havefewer deep sub-micron siliconissues

Pre-engineered standard product

alleviates complex deep sub-microndesign issues

Recovers design innovation time andfacilitates time-to-market


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Design for Test Logic

ASIC test-generation logic is not requiredin a Xilinx FPGA

Because of the capability to test in-circuit,automatic test pattern generation logic isnormally not included

- This reduces the time spent on creating andinserting test logic, and allows more time to be

spenton the bench

testing the design

Xilinx FPGAs already contain JTAG (boundary scan)logic

Xilinx FPGAs have readback capability that is similar to

scan logic Readback can verify the configuration as well as the internal

status of registers and memory


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Firmware Development

Firmware development beginsmuch earlier in the design cyclefor FPGAs

No wait ingtime for prototypes

Hardware and software can developin tandem

ASIC Design Flow


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Design Flow Comparison

ASIC FPGA

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