lab assigmnt1.docx
TRANSCRIPT
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Lab 01
INTRODUCTION TO MODELSIM
SOFTWARE
Course Title : DSD
Course Code : EEE 3
Se!ester : FALL "01#
I$stru%tor : Sir ATI& UR RE'MAN
Stude$t Na!e : S'A'ID ULLA' ('AN
)AFFER A'MAD
MU'AMMAD )AN
Re*+ No+ : FA1",-EE,0#.+
FA1",-EE,0/1+
FA1",-EE,0"+
Date : SE 12 "01#+
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Tools:,
Model sim
ur4ose:,
The main purpose of this lab is to understand the eect of delay of gates in half and full adders.
T5eor6:,
The half adder adds two one-bit binary numbers A and B. It has two
outputs, Sum and Cout . The simplest half-adder design, incorporates an XOR
gate for Sum and an AN gate for Cout . !ith the addition of an OR gate to combine
their carry outputs, two half adders can be combined to ma"e a full adder. A full
adder adds binary numbers and accounts for #alues carried in as well as out. A one-bit
full adder adds three one-bit numbers
TAS( 1: SIMULATION OF 'ALF ADDERFULL ADDER FULL
ADDER USIN7 TWO 'ALF ADDERS WIT'OUT DELA8+
Half adder without delay:
module halfadder(sum,cout,a,b);
input a,b;
output cout,sum;
or !(sum,a,b);
and a!(cout,a,b);
endmodule
module tb"halfadder();
reg a,b;
wire sum,cout;
http://en.wikipedia.org/wiki/XOR_gatehttp://en.wikipedia.org/wiki/XOR_gatehttp://en.wikipedia.org/wiki/AND_gatehttp://en.wikipedia.org/wiki/AND_gatehttp://en.wikipedia.org/wiki/XOR_gatehttp://en.wikipedia.org/wiki/XOR_gate
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halfadder h!(sum,cout,a,b);
initial
begin
a#!$b%;b#!$b%;&';
a#!$b%;b#!$b!;&';
a#!$b!;b#!$b%;&';
a#!$b!;b#!$b!;&';
end
endmodule
ulladder without delay:
module ulladder(sum,cout,a,b,cin);
input a,b,cin;
output cout,sum;
wire w!,w,w*;
or !(w!,a,b);
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or (sum,w!,cin);
and a!(w,w!,cin);
and a(w*,a,b);
or o!(cout,w,w*);
endmodule
module testulladder();
reg a,b,cin;
wire cout,sum;
ulladder f!(sum,cout,a,b,cin);
initial
begin
a#!$b%;b#!$b%;cin#!$b%;&';
a#!$b%;b#!$b%;cin#!$b!;&';
a#!$b%;b#!$b!;cin#!$b%;&';
a#!$b%;b#!$b!;cin#!$b!;&';
a#!$b!;b#!$b%;cin#!$b%;&';
a#!$b!;b#!$b%;cin#!$b!;&';
a#!$b!;b#!$b!;cin#!$b%;&';
a#!$b!;b#!$b!;cin#!$b!;&';
end
endmodule
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ulladder using two halfadders without delay:
module ulladder(sum,cout,a,b,cin);
input a,b,cin;
output cout,sum;
wire w!,w,w*;
halfadder h!(w!,w*,a,b);
halfadder h(sum,w,w!,cin);
or o!(cout,w,w*);
endmodule
module test!ulladder();
reg a,b,cin;
wire cout,sum;
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ulladder f(sum,cout,a,b,cin);
initial
begin
a#!$b%;b#!$b%;cin#!$b%;&';
a#!$b%;b#!$b%;cin#!$b!;&';
a#!$b%;b#!$b!;cin#!$b%;&';
a#!$b%;b#!$b!;cin#!$b!;&';
a#!$b!;b#!$b%;cin#!$b%;&';
a#!$b!;b#!$b%;cin#!$b!;&';
a#!$b!;b#!$b!;cin#!$b%;&';
a#!$b!;b#!$b!;cin#!$b!;&';
end
endmodule
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TAS( ": SIMULATION OF 'ALF ADDERFULL ADDER FULL
ADDER USIN7 TWO 'ALF ADDERS WIT' 1 UNIT DELA8+
Half adder with ! delay:
module halfadder(sum,cout,a,b);
input a,b;
output cout,sum;
or !(sum,a,b);
and a!(cout,a,b);
endmodule
module tb"halfadder();
reg a,b;
wire sum,cout;
halfadder h!(sum,cout,a,b);
initial
begin
a#!$b%;b#!$b%;&';
a#!$b%;b#!$b!;&';
a#!$b!;b#!$b%;&';
a#!$b!;b#!$b!;&';
end
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endmodule
ulladder with ! delay:
module ulladder(sum,cout,a,b,cin);
input a,b,cin;
output cout,sum;
wire w!,w,w*;
or &! !(w!,a,b);
or &! (sum,w!,cin);
and &! a!(w,w!,cin);
and &! a(w*,a,b);
or &! o!(cout,w,w*);
endmodule
module testulladderd!();
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reg a,b,cin;
wire cout,sum;
ulladder fd!(sum,cout,a,b,cin);
initial
begin
a#!$b%;b#!$b%;cin#!$b%;&';
a#!$b%;b#!$b%;cin#!$b!;&';
a#!$b%;b#!$b!;cin#!$b%;&';
a#!$b%;b#!$b!;cin#!$b!;&';
a#!$b!;b#!$b%;cin#!$b%;&';
a#!$b!;b#!$b%;cin#!$b!;&';
a#!$b!;b#!$b!;cin#!$b%;&';
a#!$b!;b#!$b!;cin#!$b!;&';
end
endmodule
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ulladder using two halfadders with ! delay:
module ulladder(sum,cout,a,b,cin);
input a,b,cin;
output cout,sum;
wire w!,w,w*;
halfadder h!(w!,w*,a,b);
halfadder h(sum,w,w!,cin);
or &! o!(cout,w,w*);
endmodule
module test!ulladderd!();
reg a,b,cin;
wire cout,sum;
ulladder fd!(sum,cout,a,b,cin);
initial
begin
a#!$b%;b#!$b%;cin#!$b%;&';
a#!$b%;b#!$b%;cin#!$b!;&';
a#!$b%;b#!$b!;cin#!$b%;&';
a#!$b%;b#!$b!;cin#!$b!;&';
a#!$b!;b#!$b%;cin#!$b%;&';
a#!$b!;b#!$b%;cin#!$b!;&';
a#!$b!;b#!$b!;cin#!$b%;&';
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a#!$b!;b#!$b!;cin#!$b!;&';
end
endmodule
TAS( 3: SIMULATION OF 'ALF ADDERFULL ADDER FULLADDER USIN7 TWO 'ALF ADDERS WIT' 3 UNIT DELA8+
Half adder with * delay:
module halfadder(sum,cout,a,b);
input a,b;
output cout,sum;
or &* !(sum,a,b);
and &* a!(cout,a,b);
endmodule
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module tb"halfadderd*();
reg a,b;
wire sum,cout;
halfadder hd*(sum,cout,a,b);
initial
begin
a#!$b%;b#!$b%;&';
a#!$b%;b#!$b!;&';
a#!$b!;b#!$b%;&';
a#!$b!;b#!$b!;&';
end
endmodule
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ulladder with * delay:
module ulladder(sum,cout,a,b,cin);
input a,b,cin;
output cout,sum;
wire w!,w,w*;
or &* !(w!,a,b);
or &* (sum,w!,cin);
and &* a!(w,w!,cin);
and &* a(w*,a,b);
or &* o!(cout,w,w*);
endmodule
module testulladderd*();
reg a,b,cin;
wire cout,sum;
ulladder fd*(sum,cout,a,b,cin);
initial
begin
a#!$b%;b#!$b%;cin#!$b%;&';
a#!$b%;b#!$b%;cin#!$b!;&';
a#!$b%;b#!$b!;cin#!$b%;&';
a#!$b%;b#!$b!;cin#!$b!;&';
a#!$b!;b#!$b%;cin#!$b%;&';
a#!$b!;b#!$b%;cin#!$b!;&';
a#!$b!;b#!$b!;cin#!$b%;&';
a#!$b!;b#!$b!;cin#!$b!;&';
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end
endmodule
ulladder using two halfadders with * delay:
module ulladder(sum,cout,a,b,cin);
input a,b,cin;
output cout,sum;
wire w!,w,w*;
or &* !(w!,a,b);
or &* (sum,w!,cin);
and &* a!(w,w!,cin);
and &* a(w*,a,b);
or &* o!(cout,w,w*);
endmodule
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module testulladderd*();
reg a,b,cin;
wire cout,sum;
ulladder fd*(sum,cout,a,b,cin);
initial
begin
a#!$b%;b#!$b%;cin#!$b%;&';
a#!$b%;b#!$b%;cin#!$b!;&';
a#!$b%;b#!$b!;cin#!$b%;&';
a#!$b%;b#!$b!;cin#!$b!;&';
a#!$b!;b#!$b%;cin#!$b%;&';
a#!$b!;b#!$b%;cin#!$b!;&';
a#!$b!;b#!$b!;cin#!$b%;&';
a#!$b!;b#!$b!;cin#!$b!;&';
end
endmodule
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&UESTION AND ANSWERS
ANSWER+1
+e use &' in test bench for isuali-e the output.
ANSWER+"
/staintaing an 0isting module is better approch in this speci1c case.
ANSWER+3
+hen we introduce &! in the module the result is changed because the
critical path delay of 2arry#*ns and 3um#ns .4es it is acceptable under
conditions
!. or 35M ( the result will be alid between ns to 'ns and 6ns to !%ns
and so on). or 27884 ( the result will be alid between *ns to 'ns and 9ns to !%ns
and so on)
ANSWER+
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+hen we introduce &* in the module the result is changed because the
critical path delay of 2arry#ns and 3um#ns .4es it is acceptable under
condition when we increase the delay from &' to &!%.