internet engineering dr. jarosław sugier - zsk.iiar.pwr

Project co-financed by European Union within European Social Fund

THE DEVELOPMENT OF THE POTENTIAL AND ACADEMIC PROGRAMMES OF WROCŁAW UNIVERSITY OF TECHNOLOGY

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Internet Engineering

Dr. Jarosław Sugier

Laboratory of Digital Circuits Design:

Design, Implementation and Simulation of Digital

Circuits Using Programmable Devices

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This document presents software packages that are used during laboratory classes for the course

"Digital Circuits Design": ISE Design Suite from Xilinx and ModelSim-SE from Mentor Graphics. The

aim is to help the student to complete successfully all the design steps (schematic and HDL

specification, implementation and behavioural / timing simulation) during the first projects, when

complexity of the environments may seem intimidating to an unexperienced user.

1 The Xilinx ISE Platform

Unified software package "Xilinx ISE Design Suite" integrates all applications that are used during

various steps of digital circuit design prepared for a programmable device. It facilitates project

specification using schematic representation and / or HDL description, project synthesis, its

implementation in specific architecture of a programmable chip (CPLD or FPGA), simulation and,

finally, configuration of the hardware.

The main component of the platform is the Project Navigator which can launch other

applications of the environment in order to edit source files, automatically synthesize & implement

HDL description and configure the target device when it is connected to the computer by the JTAG

cable. The Navigator can be started with a pulpit icon or by a relevant Start menu item.

The main window of the Navigator can be divided into four parts (see Fig. 1):

(a)

(b)

(c)

(d)

Fig. 1 The main window of the Project Navigator in ISE environment: (a) source files of the project, (b) process window, (c) console window, (d) working area.

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(a) the source file tree which represents all source components of the project in a hierarchical

manner;

(b) the process window which shows operations that are available for the source element

currently selected in (a);

(c) the console for text messages generated by processes launched by the Navigator;

(d) the general working area used for editing and visualisation.

In order to see the (a) and (b) windows it may be necessary to select “Design” tab located below the

process window (b). The radio buttons "View:" on the top of the source window (a) selects what kind

of source files is currently shown (not every source file is visible at all times!). There are two options

available: "Implementation" and "Simulation". The implementation view is used during regular work

on the project like source editing, project implementation, device programming etc., while

simulation of the project requires switching to the second view. Additionally, in case of simulation

view its type is selected from the drop-down list located just below the radio buttons: for CPLD

designs it can be either a) the behavioural simulation (0/1 functional test of the project specification

only before its implementation, hence without any timing analysis) or b) the post-fit simulation (the

most accurate, full timing analysis of design as it would operate in the real target device). There are

additional modes of simulation specific for FPGA designs.

The contents of the process window (b) depends on type of source element (schematic, VHDL

module, test vector, etc.) which is currently selected in source window (a). Most of the operations

while working with the Navigator is accomplished first by selecting an appropriate source file in (a)

(which may require switching to a required tab & view) and then by running a process from window

(b).

The simplest way to start a process in window (b) is to double-click it. This causes the Navigator

to start it in "auto-make" mode, i.e. all the preceding steps are run first if needed (decision is made

after comparing dates of source and output files).

Often some of the process options need to be set before running it; this is done in a process

property window (see Fig. 2 for an example) which is open by a command "Properties" from context

menu available after right-clicking the process.

� Command "Rerun All" in the process context menu makes all the preceding steps to be

unconditionally executed before the process run. This is the recommended method of

rebuilding the project after it has been substantially modified because the auto-make

mechanism not always detects such modifications correctly.

� To restore the default window layout in Project Navigator use menu command "Layout →

Load Default Layout" (very useful if arrangement of the windows gets out of control).

� Note that the source (a) and process (b) windows are located in the "Design" tab; launching,

for example, a schematic editor often switches to another tab.

In every application of the ISE package there is a menu item "Help → Software Manuals" that

opens a webpage with access to full PDF documentation of the installed Xilinx environment

(http://www.xilinx.com/support → tab Design Tools → ISE Design Suite). Additionally, information

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regarding specific applications can be accessed in a regular Windows help system available through

menu command "Help → Help Topics".

COMMON PROBLEMS

1) Every source file in the project has so called View Association attribute (Fig. 2) which can be

examined selecting the File tab (next to the Design one, Fig. 1b). For correct operation of the

Navigator each type of the source file should have the following view association:

• schematics and synthesizable VHDL modules – All;

• VHDL files with testbenches – Simulation;

• UCF files with user constraints – Implementation.

Incorrect associations (which, for example, may come from importing external files into the

project) result in a schematic being invisible in the source hierarchy window (when it has

Simulation association) or VHDL testbench being implemented as a topmost source element

(when its association is incorrectly set to All or Implementation).

2) Names of some source files are automatically used as identifiers in VHDL code and as such should

be created according to specific requirements of the language (they must begin with a letter and

can contain only letters, digits and underscores ‘_’). Errors of this kind can be especially difficult to

trace since they are not found by the editors and may cause erroneous behaviour of some tools

used later in the further implementation steps.

3) The path to the folder with the ISE project should not contain any spaces (in particular, do not

locate the project folder on the Windows desktop). Recommended location for student projects is

"C:\XilinxPrj\".

4) If the Project Navigator must be killed due to an internal error, open the Windows Task Manager

and close process _pn.exe manually if it is still running in the background.

2 Schematic specification of the design

This chapter presents the main steps that must be made to implement a project which defines

a digital circuit using schematic representation.

Fig. 2 Different types of source files with proper settings of their view associations.

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2.1 Creating a new project

1º Select menu command "File → New Project…". In the first window "Create New Project" specify

its name, location and the type of the topmost source file "Top-Level Source Type"; in this case

choose "Schematic". The working folder should be the same as project location.

2º In the second window "Project Settings" select product category, family and specific device with

its package and speed grade (depends on the target platform you are working with; e.g., the

CPLD laboratory board uses XC9572XL speed grade -10 device in PC44 package). Other important

parameters:

Synthesis Tool = XST (VHDL/Verilog)

Simulator = ModelSim-SE VHDL

Preferred Language = VHDL

Do not change other options and confirm project parameters in the next window.

� When working with the free Webpack version of the ISE software outside the lab the

ModelSim simulator is not available; one should use built-in ISim simulator in such

circumstances.

2.2 Editing the schematic

Add a new schematic source file to the project: menu command "Project → New Source…", source

type "Schematic", type in the file name, leave "Add to project" option checked, click "Next"

and confirm the procedure on the next window.

After the above steps the Navigator automatically opens the newly created schematic for edition

in the workspace area. To open any existing source element double click it on the source tree (Fig. 1

window (a)). By default, the ECS schematic editor starts as a Navigator’s sub-window, but to edit

large designs it is better to run it in a standalone window (Fig. 3). To switch between these two

window modes use buttons / or a menu command "Window → Float / Dock".

The basic editing activities typically include placing the library elements (logic gates, flip-flops,

functional modules, etc.), drawing connections (wires) and definition of I/O ports.

To place an element from the library first click the button on the vertical toolbar (or choose

menu command "Add → Symbol") and then browse the library that is displayed in the "Symbols" tab

in the left-hand part of the editor window.

To draw a signal connection between symbol ports – a net – select menu command "Add →

Wire" ( ) and draw the connection manually with the mouse. Signal names can be changed with

"Add → Net Name" ( ). Signals that should become I/O ports of the design must be connected to

I/O markers ("Add → I/O Marker"; ).

After double-clicking any element its property window is displayed. For example, properties of

an I/O marker define its name and direction.

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� Descriptions of library elements are included in "Libraries Guides" that are available in help

system of the environment. Description of a specific element currently selected in the library

window of the ECS editor can be invoked with a "Symbol Info" button on the bottom of the

symbols tab.

� Use library elements vcc and gnd as sources of logical constants 1 and 0; the NOT gate

(inverter) is called inv.

� Figure 3 shows an example of a multi-bit wide signal bus: a net becomes a bus if its name

includes an index range (e.g. Data(4:0)). To get access to a specific bus bit the net name

must refer to a valid index (e.g. Data(0)). Index range does not need to be descending nor

end with zero, although this is the standard rule that should be followed. A bus tap ( ) is the

graphical element that represents connection between a single net and a bus.

� The "Options" tab holds various important options of currently selected tool, such as net

selection mode (entire branch / single segment), automatic or manual routing of net

geometry, etc.

� Useful keyboard shortcuts: F8 / F7= Zoom In/Out, F5 = Refresh.

� Port names on the schematic must be valid VHDL identifiers: they must begin with a letter,

cannot be identical to any keywords like "in", "out", etc. These kind of errors are not always

detected by the command "Check Schematic".

Before saving the schematic should be verified with a command "Tools → Check Schematic"

( ); if there are errors reported, any symbols or nets can be found quickly with "Edit → Find

(Ctrl+F)".

� Two nets with the same name, even if visually disjoint on the schematic, are considered to be

connected and this often causes an error. Such a situation often results after deleting just one

Fig. 3 The ECS schematic editor (with an example of multi-bit wide signal bus).

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segment in a large, wide-spread net: the remaining two parts of the net hold the same name

and are electrically connected. Changing the name of just one of them does not solve the

problem in this case as the change is simultaneously applied also to the other part; in such

situation the solution is to use "Edit → Rename (Bus / Net)" command with Rename the

branch option selected.

Further information about the ECS editor can be found in its help system "Help → Help Topics".

2.3 Simulation

To simulate any circuit first a VHDL file with test vectors for its inputs must be created – so called test

bench – and then the ModelSim simulator must be invoked to compute and visualize circuit

responses on the outputs. The VHDL language itself will be presented on the lecture in due time, but

information included in this document, although fragmental, is sufficient for writing simple test

vectors. The Navigator can automatically generate a VHDL test bench template for any schematic

that is selected for simulation (see for an example Fig. 4) and the only user task is to add just a few

lines with signal transitions that should take place on circuit inputs.

Creating the VHDL test bench

1º Choose the command "Project → New Source…", select "VHDL Test Bench" and type in the file

name; in the next window select the schematic source that the test bench should be associated

with.

2º After finishing on the next window a new .vhd file will be created with test entity (ENTITY) and

its architecture (ARCHITECTURE) definitions, as can be seen in Fig. 4. Names generated for the

entity and the architecture are irrelevant and can be left unchanged, but definition of the

architecture between the lines BEGIN … END will have to be customized.

� The test bench will not be created or it will not have the correct contents if the schematic has

errors; always check the schematic with Tools → Check Schematic command before

proceeding to the simulation.

3º Before customizations are made verify the declarative part of the architecture before BEGIN

keyword. It should contain declaration of the simulated unit (COMPONENT...) with I/O ports as

given on the schematic and definitions of the respective signals that will be connected to the

ports (SIGNAL...). Identical signal and port names does not cause any conflict in VHDL; also

upper-/lowercase letters are indistinguishable in identifiers, so these kind of differences are

acceptable.

4º Architecture definition (after BEGIN) should start with an instance of the above-defined

component UUT:(...);. This instance should be left unchanged, but the lines that follows (up

to END line) should be deleted – they will be replaced with new instructions.

5º In place of deleted lines custom stimulus for input ports must be supplied. This can be

accomplished using many various VHDL constructs, but the simplest description uses parallel

signal assignments ‘<=’ which syntax is presented in the following examples:

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we1 <= '0', '1' after 100 ns, '0' after 300 ns;

we2 <= '0', '1' after 200 ns, '0' after 400 ns;

Each and every input port must be assigned in exactly one such instruction. In the above

examples we1 and we2 are the signal names (which were generated after the corresponding port

names on the schematic), '0' and '1' are the assigned values – logical constants, and the after

clauses specify time moments when the assignments will take place (time moments, not time

delays!). The effects of the above assignments can be seen in Fig. 5: both signals are initialized with

logical zero and then ‘1’ pulse appears on both for 200 ns. The 100 ns difference in pulse offsets gives

effect of a 2-bit Gray code.

Clock inputs

Definition of a periodic signal needs a slightly more complex approach. To define a 50% square

wave, first the signal needs to be initialized in the declarative part of the architecture:

SIGNAL Clk : STD_LOGIC := '0'; -- explicite inintial value given

Fig. 4 Automatically generated VHDL template of a test bench with custom stimulus assigned to the input signals:

1÷5 – package declarations, 7÷8 – entity definition, 10÷34 – architecture definition,

12÷16 – declaration of the component under test, 18÷20 – definition of signals

corresponding to the component ports, 24÷28 – an instance of the tested component with

port-signal mapping, 30÷31 – signal assignments of the custom input stimuli.

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and then its assignment in the architecture body should look like:

Clk <= not Clk after 500 ns;

(where the 500 ns gives the desired half-period value).

� Time units in VHDL: fs, ps, ns, us, ms, sec.

Buses

Bus signals (bit vectors) must be assigned with constants surrounded with double quotes "…":

SIGNAL Bus4b : STD_LOGIC_VECTOR( 3 DOWNTO 0 );

(...)

Bus4b <= "0000", "0001" after 100 ns, "0011" after 300 ns;

Additionally, vector constants which length can be divided by 4 can be expressed in hexadecimal

notation:

"0011" = X"3", "11110011" = X"F3", etc. (but "011" ≠ X"3"="0011")

Working with ModelSim simulator

1º Switch to the simulation view in the source window of the Navigator and select the VHDL test

bench file created in the previous step (but do not select UUT element which is located just

below the test bench in the source tree!), then start the process ModelSim Simulator → Simulate

Behavioural Model or ModelSim Simulator → Simulate Post-Fit Model depending on the type of

desired simulation (behavioural or timing); an independent ModelSim application will start.

� In case of "post-fit" simulation the Navigator may need to start synthesis and implementation

processes before launching the ModelSim. These operations may fail and report errors, in

which case the ModelSim will not be launched.

2º The ModelSim is a separate and quite complex environment on its own. Its main window

contains numerous specific sub-windows; a window with time waves (Wave) which visualizes the

simulation results graphically is shown in Fig. 5.

� To switch ModelSim sub-windows to independent/windowed mode use buttons / .

� To analyze time waves begin with zooming the time scale (commands "Wave → Zoom → In /

Out / Full / …", buttons ). To precisely read time delays between signal transitions

use cursors which are controlled with commands "Insert Cursor" , "Find Previous

Transition" , "Find Next Transition" , etc.

� The module under post-fit simulation test should be the top module of the source hierarchy in

the ISE project. To set the hierarchy top module use an appropriate command in the context

menu of a source element in the Navigator application; if the command is inactive, the

module already is on the top of the hierarchy.

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After start, ModelSim runs the simulation over a 1000 ns period by default and then stops.

Additional runs can be incrementally executed with a command

run <time> (e.g. run 10 us)

which should be typed in the "Transcript" window located on the bottom of the main ModelSim

window. Menu command Simulate → Run → Restart (or just restart in transcript window) resets

the simulation time to zero.

In case of behavioural simulation you can also visualize internal signals of the circuit which is

very useful for debugging. By default the Navigator puts only the module ports (I/O) in the wave

window and the internal signals must be added manually. All project signals can be found in

"Objects" sub-window after selecting UUT element in "Sim" sub-window. Upon right-clicking any

signal there is "Add to Wave" command in its context menu, after which the simulation needs to be

restarted since the newly added signal(s) will not have any data (Simulate → Run → Restart +

Simulate → Run → Run -All).

� To help recognize internal signals in the simulator their names should be changed from

default XLXN_xx to something meaningful; this is accomplished by renaming nets in the

schematic editor.

� A transcript command log –r /* turns on registering time waves of all signals during

simulation (and not only of those that are currently displayed in the wave window). This will

instantly show the history of any internal signal added to the wave window without the need

for restarting and re-running the simulation. This command can be typed manually in the

transcript window or can be included in the user script file (filename as VHDL test bench +

extension .udo) in order to be run automatically just after the simulator launch.

Fig. 5 Wave window of the ModelSim simulator.

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2.4 Assigning I/O ports to device pins

To configure the project for operation in specific hardware environment all its ports must be properly

assigned to specific pins of the target device package. This assignment is a part of an important

subject: definition of user constraints which amounts to project specification as significantly as logical

circuit description. In ISE user constraints are stored in a text file with extension .ucf (User Constraint

File) which is presented in the project source hierarchy in the Navigator.

When working with ZL-9572 laboratory board there is a special UCF file ready for download from

WWW page with all pins properly described according to their use on this board. The file should be

downloaded, copied to the project folder and then added to the project with the Navigator

command "Project → Add Source". To use specific pins that are needed in the design their

corresponding lines in the file must be un-commented (a comment character ‘#’ must be removed).

In a general case, to create a new UCF file from scratch use menu command "Project → New

Source → Implementation Constraints File", open it (process "User Constraints → Edit Constraints

(Text)") and type in the location (LOC) directives:

#Format: NET "PortName" LOC = "PinNo";

NET "I1" LOC = "P13";

NET "I2" LOC = "P12";

NET "O1" LOC = "P24";

...

Format of the pin numbers depends on the type of the package. PLCC packages (as the one used in

ZL-9572 board) use linear numbering in the form of "Pn", BGA packages use chessboard notation (A1,

C35 and so on), etc. In any case it should be checked in documentation what kind of the package is

used on the target platform, the pin locations should be chosen appropriately and included as the

LOC directives in the UCF file.

� If there is no UCF file in the project or not all I/O ports are assigned to pin locations the

implementation tool will distribute them among available pins according to its own criteria

and successfully generate programming file without any warning. There are very small

chances that the project will work in hardware, though.

2.5 Configuring the device

1º Start the process "Implement Design → Generate Programming File" for the topmost schematic

source. If succeeds, there will be a .jed file created in the project folder ready to be sent to the

programmable device.

� Implementation of the CPLD projects consists of the "Synthesize", "Translate" and "Fit"

processes. If any one fails the console will show error messages and it will be necessary to

return to schematic or UCF file. Typically, "Synthesize" errors come from schematic or VHDL

code, "Translate" – from UCF file, "Fit" – from problems with pin assignments, insufficient

resources, etc..

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2º Power on the board with the device, connect it to the computer with the JTAG cable (to the

parallel or USB port) and start the iMPACT application by running the "Configure Target Device"

process.

3º Cancel the first "New iMPACT Project" window without creating any project and double click the

"Boundary Scan" option in "iMPACT Flows" sub-window (upper-left part of the main window).

Choose menu command "File → Initialize Chain (Ctrl+I)".

� At this moment the application must automatically detect and properly identify the CPLD

device as shown in Fig. 6. If not, there are some hardware problems: check once again power

supply, programming cable, etc..

4º In the "Adding New Configuration File" window (Fig. 6) find the .jed file generated in the project

folder, then accept default settings on the next "Device Programming Properties" window.

5º The iMPACT application is ready for sending the configuration stream to the device: right click its

symbol and choose "Program…" command; if the JTAG transmission succeeds, a blue

"Programming succeeded" message will be shown. In case of errors test the transmission with

menu command "Debug → IDCODE Looping".

6º After the configuration the device starts operation instantly; verify project operation using

various board components (keys, LEDs, ports…).

Fig. 6 Programmable device properly detected by the iMPACT application.

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3 VHDL description of the project

The VHDL language is the basic specification format in ISE environment and does not need any

external editors. After creating a new project as described in 2.1 add a VHDL module as a new source

element:

1º In the Navigator select "Project → New Source…", choose "VHDL Module", type in a file name

and click "Next".

2º In "Define Module" window (Fig. 7) specify entity and architecture names and module ports. For

each port give its name, direction and, in case of a bus port, index range in MSB / LSB fields.

� Due to synthesis constraints do not use any other port modes than the two basic ones: in and

out.

3º After accepting the parameters a new .vhd file will be added to the project and automatically

open for edition. Initially, the file will contain definition of the entity (with ports defined

previously) and one empty architecture, as in Fig. 8.

4º Fill the empty template with VHDL instructions.

� When defining basic combinational and sequential circuits follow closely the sample examples

included in PDF document "XST User Guide", chapter "XST HDL Coding Techniques". You can

also use the template library which opens in the Navigator menu command "Edit → Language

Templates…" ( ; branch VHLD → Synthesis Constructs → Coding Examples).

5º After preparing a VHDL module it can be used as a "black-box" element on the schematic: create

a symbol running the process "Design Utilities → Create Schematic Symbol" for the module and

then place it on the schematic as any other library element (in symbol browser user-created

symbols are grouped in category which name is derived form project folder). This way a multi-

layer source hierarchy is created with schematic on top and VHDL as sub-modules.

Fig. 7 Window with ports definition while creating a new VHDL module.

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� By default, every new symbol is initially created as a plain rectangle with input ports grouped

on the left edge and output ports grouped on the right edge. After that it can be graphically

edited: in schematic editor a context menu of a user symbols contains "Edit → Symbol"

command.

� The above procedure of symbol creation can be applied also to schematics, thus the source

hierarchy can include schematics as sub-modules too. There is no limit on hierarchy depth nor

on its structure (VHDL vs. schematics).

After creating the topmost element of source hierarchy as a VHDL module further operations

(simulation, pin assignment, implementation and device programming) is accomplished identically as

it was presented in chapter 2 for schematics.

Literature

1) ISE DS Software Manuals – PDF Collection: Libraries Guides, electronic documentation of the ISE

package.

2) ISE DS Software Manuals – PDF Collection: XST User Guide, electronic documentation of the ISE

package.

3) On-line help system of the ISE applications.

4) ISE Quick Start Tutorial, Xilinx Inc. www.xilinx.com.

5) Programmable Logic Design Quick Start Guide (ug500.pdf), Xilinx Inc. www.xilinx.com

Fig. 8 The empty VHDL module template generated for parameters as in Fig. 7.

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