FINFET TECHNOLOGY

CONTENTS

• INTRODUCTION TO VLSI TECHNOLOGY• MOORE’S LAW AND IT’S LIMITATIONS• LIMITATIONS ON MOSFET TECHNOLOGY• SHORT CHANNEL EFFECT IN MOSFET• INTRODUCTION TO FINFET• WHY WE NEED FINFET• STRUCTURE OF FINFET• FABRICATION PROCESS OF FINFET• ADVANTAGES AND DISADVANTAGES OF FINFET• APPLICATIONS OF FINFET• CONCLUSION• REFERENCES

INTRODUCTION TO VLSI

Very-large-scale integration (VLSI) is the process of creating integrated circuits by combining thousands of transistors into a single chip.

VLSI began in the 1970s whencomplex semiconductorand communication technologies were being developed.

3

MOSFET TECHNOLOGY

The growth of digital technologies like the microprocessor has provided the motivation to advance MOSFET technology faster than any other type of silicon-based transistor.

A big advantage of MOSFETs for digital switching is that the oxide layer between the gate and the channel prevents DC current from flowing through the gate, further reducing power consumption and giving a very large input impedance

“”THE NUMBER OF TRANSISTORS INCORPORATED IN A CHIP

WILL APPROXIMATELY DOUBLE EVERY 24 MONTHS.“

—GORDON MOORE

MOORE’S LAW

LIMITATIONS ON MOSFET TECHNOLOGY

• Short channel effects limitingscaling into sub nanometer regime.

• Oxide thickness cannot be scaled down further, problems of tunneling.

• performance and power dissipation need to be improved.

• Need to keep silicon technology

as the base technology when innovating future devices; cost is an important factor

7

Power Consumption Problems

1.Not just a chip and package thermal issue.

2.ICs use a few% of world’s electricity today and• Power per chip is growing.• IC units in use also growing.

3.If power consumption is not reduced, industry future growth is at risk.

Long channel Transistor(MOSFET)

Insulator

Source Drain

Cg

GGaa

tete

COX

Ec

Ev

Source

Channel

Drain

VgEnergy Band Diagram

SHORT CHANNEL EFFECTS IN MOSFET

It is an effect whereby a MOSFET in which the channel length is the same order of magnitude as the depletion layer widths of source & drain junctions, behaves differently from the other MOSFETs.

As the channel length ‘l’ is reduced to increase both the operation speed and the number of components per chip, the so called SCE occurs.

10-11

10-9

10-7

10-5

10-3

Dra

in

Cu

rren

t, I

D S

(A/

m)

GS

Gate Voltage, V(V)

Size shrink

MOSFET becomes “resistor” at very small L –- Drain competes with Gate to control the channel barrier.

Insulator

Source Drain

Cg

Cd

GGaa

tete

Smaller size

orlarger Vd

0.0 0.3 0.60.9

SHORT CHANNEL-PROBLEMS

Reducing EOT is Not Enough

Gate

Source Drain

Leakage Path

Gate cannot control the leakage current paths that are far from the gate.

In planar devices on-current is mostly carried out in a top layer. Body current is a source of leakage when the device is off.

One Way to Better Vt and S

The gate controls a thin body frommore than one side.

Gate

Gate

FinFET body is a thin fin

So

urc

e

Dra

in

Gate Length

Fin Height

Fin Width

Source Drain

INTRODUCTION TO FINFET

The term “FINFET” describes a non-planar, double gate transistor built on an SOI substrate, based on the single gate transistor design.

The important characteristics of FINFET is that the conducting channel is a thin Si “fin”, which forms the body of the device.

The thickness of the fin determines the effective channel length of the device.

HISTORY OF FINFET FINFET is a transistor design first developed by Chenming Hu and his colleagues at the University of California at Berkeley, which tries to overcome the worst types of SCE(Short Channel Effect).

Originally, FINFET was developed for use on Silicon-On-Insulator(SOI).

SOI FINFET with thick oxide on top of fin are called “Double-Gate” and those with thin oxide on top as well as on sides are called “Triple-Gate” FINFETs

WHY WE NEED FINFET ?

Planar does’nt scale beyond gate length of 25nm

And also gate oxide does’nt scale.

If we assume we have a gate dielectric of thickness zero, Then also we cannot control SEC’S.

For the double gate soi mosfet’s, The gates control the energy barrier between source and drain effectively.

FINFET

WHAT DOES FINFET LOOK’S LIKE?

Effective channel width W = Tfin + 2×Hfin

Effective channel length Leff = Lgate + 2×Lext

GENERAL LAYOUT & MODE OF OPERATION

The basic electrical layout and mode of operation of a FINFET does not differ from a traditional FET.

There is one source and one drain contact as well as a gate to control the current flow.

In contrast to planar MOSFET, the channel b/w source and drain is build as 3D bar on top of the Si substrate and are called fin.

“FINS” The fin is used to form the raised channel.

As the channel is very thin the gate has a great control over carriers within it, but, when the device is switched.

The thickness of the fin (measured in the direction from source to drain) determines the effective length of the device.

So

urc

e

Dra

in

Gate Length

Fin Height

Fin Width

“FINS”

The fin is used to form the raised channel.

As the channel is very thin the gate has a great control over carriers within it, but, when the device is switched on, the shape limits the current through it to a low level. The thickness of the fin (measured in the direction from source to drain) determines the effective length of the device.

Fabrication - Process Flow“Easy in concept----Tough to build”

(a) SiN is deposited as a hard mask,SiO2 cap is used to relieve the

stress.

(b) Si fin is patterned

(c) A thin sacrificial SiO2 is grown

(d) The sacrificial oxide is stripped completely to remove etch damage

(e) Gate oxide is grown

(f) Poly-Si gate is formed 10 nm gate length, 12 nm fin width

ADVANTAGES OF FINFET

Higher technological maturity than planar DG

Suppressed Short Channel Effect(SCE)

Better in driving current

More compact

Low cost

DISADVANTAGES OF FINFET

Reduced mobility for electrons Higher source and drain resistances

Poor reliability

APPLICATIONS Low power design in

digital circuit, such as RAM, because of its low off-state current.

Power amplifier or

other application in analog area

which requires good linearity.

CONCLUSION

Double-gate FET can reduce Short Channel Effects and FinFET is the leading DGFET.

Optimization design includes geometry, S-D fin-extensiondoping, dielectric thickness scaling, threshold voltage control….

Fabrication of FinFET is compatible with CMOS process

10 nm gate length, 12 nm fin width device has been fabricated and shows good performance

REFERENCES

[1]Tsu Jae King Liu,“FinFETHistory,Fundamentals and Future”, 2012 ‐Symposium on VLSI Technology .

[2] Jovanović, T. Suligoj, P. Biljanović, L.K. Nanver, “FinFET technology for wide-channel devices with ultra-thin silicon body”.

[3] M.Jurczak, N.Collaert, A.Veloso, T.Hoffmann, S.Biesemans, “Review of FinFET Technology,” IEEE

[4]http://www. techalone.com, Electronic seminar topic .

[5] Vishwas Jaju, “Silicon-on-Insulator Technology,” EE 530, Advances in MOSFETs, spring 20010 pp. 1-12.