seminar report on finfet

8/21/2019 Seminar Report on FinFET

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FinFET 1

1. ABSTRACT

The introduction of FinFET Technology has opened new chapters in Nano-

technology. Simulations show that FinFET structure should be scalable down to 10 nm.

Formation of ultra thin fin enables suppressed short channel effects. It is an attractie

successor to the single gate !"SFET by irtue of its superior electrostatic properties and

comparatie ease of manufacturability. Since the fabrication of !"SFET# the minimum

channel length has been shrin$ing continuously. The motiation behind this decrease has

been an increasing interest in high-speed deices and in ery large-scale integrated circuits.

The sustained scaling of conentional bul$ deice re%uires innoations to circument thebarriers of fundamental physics constraining the conentional !"SFET deice structure.

The limits most often cited are control of the density and location of dopants proiding

high Ion&Ioff ratio and finite sub threshold slope and %uantum-mechanical tunneling of

carriers through thin gate from drain to source and from drain to body.

'ept. "f Electronics (roduction Technology )(T*# *herthala


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FinFET +

2. INTRODUCTION

Since the fabrication of !"SFET# the minimum channel length has been

shrin$ing continuously. The motiation behind this decrease has been an increasing interest

in high speed deices and in ery large scale integrated circuits. The sustained scaling of

conentional bul$ deice re%uires innoations to circument the barriers of fundamental

physics constraining the conentional !"SFET deice structure. The limits most often

cited are control of the density and location of dopants proidinghigh I on &I off ratio and

finite sub threshold slope and %uantum-mechanical tunneling of carriers through thin gate

from drain to source and from drain to body. The channel depletion width must scale with

the channel length to contain the off-state lea$age I off. This leads to high doping

concentration# which degrade the carrier mobility and causes ,unction edge lea$age due to

tunneling. Furthermore# the dopant profile control# in terms of depth and steepness#

becomes much more difficult. The gate oide thic$ness to must also scale with the

channel length to maintain gate control# proper threshold oltage Tand performance. The

thinning of the gate dielectric results in gate tunneling lea$age# degrading the circuit

performance# power and noise margin.

/lternatie deice structures based on silicon-on-insulator (SOI) technology

hae emerged as an effectie means of etending !"S scaling beyond bul$ limits for

mainstream high-performance or low-power applications .Partially d!ltd (PD) SOI

was the first S"I technology introduced for high-performance microprocessor applications.

The ultra-t"in-#ody $ully d!ltd (%D) SOI and the non-!lanar %in%&T deice

structures promise to be the potential future technology&deice choices.

In these deice structures# the short-channel effect is controlled by geometry# and

the off-state lea$age is limited by the thin Si film. For effectie suppression of the off-state

lea$age# the thic$ness of the Si film must be less than one %uarter of the channel length.

The desired T is achieed by manipulating the gate wor$ function# such as the

use of midgap material or poly-Si)e. *oncurrently# material enhancements# such as the use



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FinFET 2

of a3 high-$ gate material and b3 strained Si channel for mobility and current drie

improement# hae been actiely pursued.

/s scaling approaches multiple physical limits and as new deice structures and

materials are introduced# uni%ue and new circuit design issues continue to be presented. In

this article# we reiew the design challenges of these emerging technologies with particular

emphasis on the implications and impacts of indiidual deice scaling elements and uni%ue

deice structures on the circuit design. 4e focus on the planar deice structures# from

continuous scaling of (' S"I to F' S"I# and new materials such as strained-Si channel

and high-$ gate dielectric.



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FinFET 5

'. PARTIA D&P&T&D (PD) SOI

The (' floating-body !"SFET was the first S"I transistor generically adopted

for high-performance applications# primarily due to deice and processing similarities to

bul$ *!"S deice.

The (' S"I deice is largely identical to the bul$ deice# ecept for the addition

of a buried oide 67"83 layer. The actie Si film thic$ness is larger than the channel

depletion width# thus leaing a %uasi-neutral floating body region underneath the

channel. The T of the deice is completely decoupled from the Si film thic$ness# and the

doping profiles can be tailored for any desired T.

The deice offers seeral adantages for performance &power improement9

13 :educed ,unction capacitance#

+3 ;ower aerage threshold due to positie 7S during switching.

23 'ynamic loading effects# in which the load deice tends to be in high T state during

switching


%i*.'.1.Partially depleted (PD)SOI


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FinFET

seminar report on finfet

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