advanced finfet process technology

National Institute of Advanced Industrial Science and Technology

Advanced FinFET Process Technology

M. MasaharaNational Institute of AIST

1


1. Introduction

2. Advanced FinFET Process Technology

3. Summary

• Merits and Issues of FinFET

• Vth Tuning

• Vth Variation

Contents

1. Introduction


3. Summary


• Vth Tuning

• Vth Variation

2


Multi-Gate FinFETs

S

GD

S

GD

1st FinFET Patent in 1980 from AIST

FinFET

Proposed by AIST in 1980 (named “FinFET” by UCB in 1999)

Ultrathin and undoped channel and self-aligned double gate

Extremely high short channel effect (SCE) immunity3


4

DIBL Benchmark

FinFETs show the smallest DIBL (=highest SCE immunity)


5

Issues for Advanced FinFET However, several technological issues still exist…

S

GD

S

GD

Fin Formation

Vth Tuning

Low ResistiveSource/Drain

Stress Eng.

SOI or BulkCompact Model

(110) Channel

Cpara

Variation

I/O, ESD


1. Introduction


3. Summary


• Vth Tuning

• Vth Variation

Contents

6


-0.2

0

0.2

0.4

0.6

0.8

1

4 4.2 4.4 4.6 4.8 5 5.2 5.4

V thD

G(N

MO

S),

-Vth

DG

(PM

OS)

(V)

Gate Workfunction (eV)

n+-S

i (4.

17eV

)

p+-S

i (5.

25eV

)

0.4V(LSTP)

0.2V(LOP)

4.6eV 4.9eV4.75eV

Vth for FinFETs

Vth has a linear relationship with Gate Workfunction For low Vth, dual metal gate (dual WF) is needed

AIST, IEEE TED 2007

7


-1.5 -1 -0.5 0 0.5 1 1.510-1210-1110-1010-910-810-710-610-510-410-3

Gate Voltage, V g [ V ]

Dra

in C

urre

nt, I

d [ A

]

8

-1.5 -1 -0.5 0 0.5 1 1.510-1210-1110-1010-910-810-710-610-510-410-3

Gate Voltage, V g [ V ]D

rain

Cur

rent

, Id [

A ]

Weff =7.5 m

NMOSPMOS|Vd | = 1 V

0.05 V

Almost symmetrical Vth’s (normally off) are obtained thanks to the midgap work function of TiN (4.75 eV)

n+ poly-Si gate TiN-gate

Symmetric VthAsymmetric Vth

Id-Vg for Poly- and TiN-Gate FinFET

NMOSPMOS|Vd | = 1 V

0.05 V

Weff =17 mLg = 21 m

Weff =7.5 mLg = 21 m

Weff =17 m


Dual Metal Gate Integration

TiN nMOSTaCN pMOS

Ref. M.M.Hussain et al., ESSDERC2007, p.207

Integration of TiN and TaCN gate FinFETs

Etching residue

“Deposition and etching”General approach:

“Metal Inter-diffusion”This work :

(No metal etching)

For PMOS Mo(4.95 eV)

For NMOSTa(4.25 eV)/Mo stack Ta Inter-diffusion in Mo

9


10-3

10-2

10-1

100

0 5 10 15

Ta io

n co

unt [

arb.

uni

t]

Depth [nm]

Ta layer Mo layer SiO2

Tadiffusion

Annealed(700oC 1 h)

As depo.

O2+

Ta diffusion in MoBack-side SIMS

Ta diffuses in Mo and piles-up at Mo/SiO2 interface after annealing

Thus WF for NMOS is determined by Ta (4.25eV)10


SiO2 HM etchbackin nMOS region

Ta and SiO2 HM etchbackin pMOS region

Patterning of Mo and Ta/Mo gates

Features of Dual MG FinFETs

No metal residue 11


AIST, IEEE EDL 2008

I-V for Mo and Ta/Mo FinFETs

For NMOS, low Vth can be achieved by Ta diffusion in Mo For PMOS, low Vth can be achieved by Mo Off leakage Negligible

PMOS

Mo(high WF)

Ta(low WF)

low gate WFby Ta diffusion

Mo(high WF)

NMOS

12


Four-Terminal FinFET

G1 G2S

D

G1 G2S

D Vth control gateDrive gate

4T-FinFET = Independent DG FinFET

Ioff Ion

Vg1

Ioff

Ion

Vg1

log

I d

VthDG Vth(G1)

log

I d

-Vg2

+Vg2

DGseparation

S

GD

S

GD

13

Vth for FinFET can be controlled flexibly and individuallyby separating the DG


DG Separation

G

S

D

CMP

G1

S

DG2

CMP Stopper ＳＥＭ Image after CMP

FinFET Formation DG Separation by CMP

Gate1

Gate2

Source Drain

Fin Top

100nmSide Wall

ＳＥＭ Image after LEB

FinFET Formation and Lithography

DG Separation by LEB

Resist

BOX

sub

Fin GateStopper

CMP Process

Local Etch-back Process

14


Vth Tuning by Controlling Vg2

15

-1.2 -1 -0.8 -0.6 -0.4 -0.2 0-1.2

-1-0.8-0.6-0.4-0.2

00.20.40.60.8

050100150200250300350

Vg2 [ V ]

V th [

V ]

S-S

lope

[ m

V/d

ecad

e ]

& Tsi = 8.5-nm, = 0.79& Tsi = 13-nm, = 0.66& Tsi = 23-nm, = 0.42& Tsi = 43-nm, = 0.24

G1 G2S

D

G1 G2S

D

Vth can be tuned from LSTP to HP flexibly by selecting a proper Vg2 (The Second Gate)


1. Introduction


3. Summary


• Vth Tuning

• Vth Variation

Contents

16


Vth Variation for MG FinFETs

G D

S

(1)

(2)

(3)

(5)(4)(2) Fin Thickness (TSi)

(3) Oxide Thickness (Tox)

(4) RDF

(5) Work Function WFV (m)

(1) Gate Length (Lg)

Possible Vth Variation Sources

17

FinFET variability sources were systematically analyzed


18

Main Cause of Vth Variation

Negligible

Dimension Variation sources

0 5 10 15 20 25 30 35

Measured Vth

TFin SourceLG Source

Tox Sourcem Source

LG=6.7 nm (measured)

TFin=2.9 nm (measured)

Tox=0.032 nm (measured)

Vth [mV]

LG= 100 nmTFin= 40 nm<Vth>= 0.42 V

AIST, IEEE EDL 2010

Main Cause

Dimension variation sources are negligible Main cause of the Vth variation is the Workfunction Variation


Rough etched side wall causes randomly aligned metal grain and thus higher WF variation

If side wall is flat, uniformly aligned metal grain and thus lower WF variation can be expected

Workfunction Variation

S

D

RIE Ideal

Randomlyaligned Metal

Higher WF variation

Uniformlyaligned Metal

LowerWF variation

Si 1-MetalSiO2

SiSiO2

G

2-Metal

1-Metal

19


AIST, IEDM 2006

0 5 10 150

1000

2000

3000

4000

5000

Etching time [ min ]

Etch

ing

Dep

th [

nm ]

214 nm/min

2.38% TMAH50oC

(110)

(111)

(100)359 n

m/min

9 nm/min

0 5 10 150

1000

2000

3000

4000

5000

Etching time [ min ]

Etch

ing

Dep

th [

nm ]

214 nm/min

2.38% TMAH50oC

(110)

(111)

(100)359 n

m/min

9 nm/min

Extremely low ER of (111) in TMAH Flat (111) side wall

Etchant：2.38% TMAH (Resist Developer)(Tetramethylammonium hydroxide)

CH3

CH3

CH3

CH3N

+

OH -CH3

CH3

CH3

CH3N

+

OH -

fin-mask Si-fin

TMAH

BOXSOI

Nano-Wet Etching Process

<110>

<111>

20


Source Drain

Si-fin

20 nm Gate

Hfin = 45 nm

TSi = 12 nm

Tox

Min.Lg = 20 nm, TSi = 17.8 nm, HSi = 45 nm Nano-Wet-Etched FinFET Undoped channel Tox(CET) = 2.3 nm by C-V Gate Stack : PVD-TiN/SiO2

AIST, VLSI Symp. 2010SEM and STEM images of FinFET

21


05

10152025303540

0 5 10 15 20 25

Vth [

mV

]

1/(WL)1/2 [ mm-1 ]

PVD-TiN Gate CET = 2. 3 nm

AVt was significantly lowered by flattening the side channel

AIST, VLSI Symp. 2010

Measured Vth for Nano-Wet-Etched FinFET

22


Avt BenchmarkRef. #

Device Structure

Gate Stack Author.Organi-zation

Reference

1 FDSOI Poly/SiO2 A.Cathignol ST ESSDERC2006

2 FDSOI TiN/HfO2C. Fenouillet-Beranger

ST IEDM2007

3FDSOI (SOTB)

NiSi/ Y.Morita Hitachi VLSI2008

4 Bulk-planar Poly/SiON T.Tsunomura Selete VLSI2008

5 Bulk-planar MG/HK F.Arnaud ST IEDM2008

6 Bulk-planar MG/HK S.Hasegawa Toshiba IEDM2008

7 Bulk-planar s-Si/SiON H.Fukutome Fujitsu IEDM2009

8 Bulk-planar HK/MG M.Goto Toshiba VLSI2009

9 FinFET Mo/SiO2 T.Matsukawa AIST VLSI2009

10 Bulk-planar MG/HK F.Arnaud ST IEDM2009

11 Bulk-planar MG/HKL.A.Ragnarsson

IMEC IEDM2009

12 Bulk-planar MG/HKL.A.Ragnarsson

IMEC IEDM2009

13 FDSOI MG/HK K.Cheng IBM IEDM2009

14 FinFET TiN/HfSiO T.Chiarella IMEC ESSDERC2009

15 FinFET TiN/SiO2 Y.Liu AIST VLSI2010

0

1

2

3

4

0 1 2 3 4

Bulk-planarFDSOIFinFET

Avt

= V

t(LW

)1/2

[mV

-um

]

Tox [nm]

1

23

4

56

7

8

91011

12

13

1514

List of reported AVt values

T. Matsukawa, et al., (AIST.) SOI Conf, 2011, 7.1.

23

LSTP15nm

LSTP22nm

Obtained Avt meets 22-nm-node SRAM requirement For 15nm and beyond, Avt should be further reduced


1. Introduction


3. Summary


• Vth Tuning

• Vth Variation

Contents

24


Summary

By introducing Ta/Mo dual metal gate technology, low Vth (±0.2V) can be obtained for CMOS FinFETs.

By separating the DG, Vth can be tuned from 0.2V to 0.4V flexibly.

Flattening of Si-fin sidewall channel is very promising for reducing Vth variations.

This work was supported in part by NEDO25

advanced finfet process technology

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