© 2014 TSMC, Ltd

TSMC Property

Yi-Pin Fang and A. S. Oates

Cell Level Soft Error Rate Simulations

of Planar and FinFET Processes

© 2014 TSMC, Ltd

TSMC Property

1

Accuracy verification for cell level SER simulations

of the FinFET process

Discussion for multiple cell upset (MCU) probability

of the FinFET SRAM

Purpose

© 2014 TSMC, Ltd

TSMC Property Outline

Introduction

TFIT Cell Level SER Simulation Flow

Accuracy Verification for Simulations of Planar and

FinFET Processes

Discussion for MCU Probability of SRAMs of Planar

and FinFET Processes

Conclusion

© 2014 TSMC, Ltd

TSMC Property

3

Why is Cell Level SER Simulation Important?

Difficult to collect cell level SER data from

accelerated SER tests.

Rapid to obtain the results. Only take mins to hours

for a run.

Lower cost for simulation compared to the SER test.

Enable to evaluate vulnerable points in logic cells for

SER hardened cell design.

© 2014 TSMC, Ltd

TSMC Property

4 SER Estimation Working Flow for SoC

Circuits

Cell level SER for memory/logic cells

Within Spec?

Ok

Yes

No

Architecture rearrangement/ECC

implementation

Hardened cell design for SER mitigation

Collected by SER

simulations

Collected by accelerated

tests

Electrical derating, logical derating, and timing derating

analyses

Chip level SER Simulation

© 2014 TSMC, Ltd

TSMC Property

5

A Case of Chip Level SER Simulations

Figure. Block diagram of a infiniband

host channel adapter (HCA)

H. Chapman et al, SELSE, 2010

Memory SER on the HCA before and after ECC

correction

Logic SER on the HCA without any de-rating factor

This case shows that the customer successfully perform cell level

and chip level SER simulations for HCA products.

© 2014 TSMC, Ltd

TSMC Property

6

Cell Level SER Simulation Flow

TFIT simulation

Input files:

Output results: Configuration

parameters like

neutron/alpha

spectra, applied

voltage, and layout

info. …etc.

Technology based

SPICE model

SPICE Netlist

Single event upset (SEU)

FIT

Multiple cell upset (MCU)

FIT &pattern

Cross-section

Single event transient

(SET)

Process Response

model

HSPICE

simulator

Nuclear

database

Response single event transients (SET) collected by

TCAD simulations for a specific technology. Calibration

work is required.

© 2014 TSMC, Ltd

TSMC Property

7

Procedure of Process Response Model

Setup for a Specific Technology

Design of Experiments

(DoEs)

LETs

Operation Voltages

Strike Locations

Collected

Response SETs TCAD Process Related

Inverter Structure

NMOS

PMOS

~400 TCAD DoE runs.

DoEs taken several months for each process response model.

40nm to 16nm planar and FinFET process response models are now

navailable at TSMC.

© 2014 TSMC, Ltd

TSMC Property

The Accuracy Verification for TFIT

Simulations of Planar and FinFET

Processes

© 2014 TSMC, Ltd

TSMC Property Simulation Accuracy for a SRAM of a Planar

Process

Accuracy verified for the SRAM with different Vdd and

test patterns.

Neutron induced MCU(&MBU) distribution can be

simulated accurately.

Y.-P. Fang et al SELSE 2013

Different Voltage Different test pattern

© 2014 TSMC, Ltd

TSMC Property Simulation Accuracy for Logic Cells of a Planar

Process Y.-P. Fang et al, SELSE, 2013

Accurate simulation results are obtained for different

types of sequential logic cells (Flip-Flops).

Capable for cell level SER simulations.

© 2014 TSMC, Ltd

TSMC Property

TFIT Simulation for a 6T-SRAM cell

0

0.2

0.4

0.6

0.8

1

1.2

1.4

Planar FinFET

SE

R p

er

Ce

ll (

A.U

.)

Neutron

Alpha

Simulation Accuracy for the 6T-SRAM of a FinFET

Process

Capable to simulate FinFET SRAM SER for different voltage

~10X neutron and ~15X alpha SER benefit for FinFET SRAM due

to the reduction of drain area and collected charge.

Neutron SER for SRAM

0

0.05

0.1

0.15

0.2

0.25

0.7 0.8 0.9 1

SE

R p

er

ce

ll (

A.U

.) Exp.

Sim.

Nominal Vdd -10% +10%

Alpha SER for SRAM

0

0.02

0.04

0.06

0.08

0.1

0.12

0.14

0.7 0.8 0.9 1

SE

R p

er

Ce

ll (

A.U

.) Exp.

Sim.

Nominal Vdd +10% -10%

Y.-P. Fang et al, TDMR 2011

© 2014 TSMC, Ltd

TSMC Property

12

Simulated Neutron-Induced MCU Distribution

of the FinFET SRAM

SBU (cell # =1) and MCU (cell # >1)

Capable to simulate accurate MCU distributions of the

FinFET SRAM for different test patterns.

SBU&MCU Distribution with CHB pattern

0.0001

0.001

0.01

0.1

1

0 1 2 3 4 5Cell#

Pro

ba

bilit

y

Exp.

Sim.

SBU&MCU Distribution with All1/0 pattern

0.001

0.01

0.1

1

0 1 2 3 4 5Cell#

Pro

ba

bilit

y

Exp.

Sim.

© 2014 TSMC, Ltd

TSMC Property

13

Simulations for a Logic Cell of the FinFET

Process

TFIT Simulation for a D-Flip-Flop cell

0

0.5

1

1.5

2

2.5

3

Planar FinFET

SE

R p

er

Ce

ll (

A.U

.)

Neutron

Alpha

Compared to a planar cell, neutron SER benefit for the

FinFET cell is ~10X.

The Flip-Flop cell is immune to alpha particles due to its

high Qcrit.

Immune to alpha!

© 2014 TSMC, Ltd

TSMC Property

Discussion for MCU Probability of

SRAMs of Planar and FinFET

Processes

© 2014 TSMC, Ltd

TSMC Property

Neutron Induced MCU Probability of Planar

SRAMs in the Literature

The advanced technology with smaller bit-cell has higher

MCU probability.

The MCU trends as a function of cluster size are consistent

across technology nodes.

N. Seifert et al, IRPS, 2008

MCU probability rises!

© 2014 TSMC, Ltd

TSMC Property

16

Comparison for MCU Probabilities of Planar and

FinFET SRAMs in the Literature

N. Seifert et al, TNS, 2012

Total MCU probability rises for the FinFET SRAM.

Geometry change of the FinFET is not benefit to the

reduction of MCU probability.

FinFET

planar

© 2014 TSMC, Ltd

TSMC Property

0.01

0.1

1

A B C DTechnology

MC

U p

rob

ab

ilit

y Exp.

Sim.

MCU Probabilities of SRAMs of Our Processes

The MCU probability trend of SRAMs is opposite to the

literature.

Exp. and sim. results are in good agreement.

FinFET Process

MCU probability lowers down !

Nominal voltage, CHB pattern

© 2014 TSMC, Ltd

TSMC Property

MCU Probabilities as a Function of MCU Cluster

Size

0.00001

0.0001

0.001

0.01

0.1

0 0.5 1 1.5 2MCU Cluster Size (A.U.)

MC

U P

rob

ab

ilit

y

A

B

C

MCU probabilities of SRAMs are process dependent.

D

Exp: Solid

Sim: Open

Nominal voltage, CHB pattern

© 2014 TSMC, Ltd

TSMC Property

19

-1.E-05

0.E+00

1.E-05

2.E-05

3.E-05

4.E-05

1.E-12 1.E-11 1.E-10 1.E-09Time(sec)

Dra

in C

urr

en

t (A

.U.)

A

B

C

D

Simulated Transient Currents of Different

Processes

In the TCAD simulation, an ion strikes to the location away

from the SRAM. Thus charge is collected by diffusion only.

The results show Qcoll of the SRAM decrease with

technology scaling due to different substrate doping levels

of the processes.

Time of the ion

strike

0

1

2

3

4

5

6

7

A B C DTechnology

Co

lle

cte

d c

ha

rge

(A

.U.)

Qcoll comparison Current comparison

FinFET

© 2014 TSMC, Ltd

TSMC Property

20

SER of memory and logic cells can be simulated

accurately by TFIT for planar and FinFET processes.

Neutron SER of FinFETs is ~10X lower than that of

planar devices. Alpha SER is almost immune for

FinFET process.

TFIT cell level simulations are now available for

technologly from 40nm to 16nm.

MCU probability of the SRAM is not influenced by

the FinFET structure.

MCU probability of the SRAM is strongly process

dependent.

Conclusion

© 2014 TSMC, Ltd

TSMC Property

Thank you!