pll (tsmc 0.18 process)
DESCRIPTION
Class presentationTRANSCRIPT
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EE486 Digital VLSI- Final Project
Clock Multiplying DPLL
Chen ZhaiKlipsch School of Electrical and Computer Engineering
New Mexico State [email protected]
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Presentation Outline
o Block Diagram
o Specification
o Loop Filter Parameters
o Sub-blocks
o Simulation
o Comments and Questions
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Block Diagram
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Specification
o TSMC 0.18 Standard CMOS
o Supply Voltage 1.8V
o Input Frequency 150MHz
o Output Frequency 750MHz
o Load 1pF
o Lock Time ~ micro seconds
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Loop Filter
Spec:
Input Frequency
Natural Frequency (~Bandwidth)
Damping Factor
Results:
Design Values: R, C1, C2, Ipump
Performance: Lock time, etc
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Linearized Current-Starved VCO with Output Buffers
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Linearized Current-Starved VCO Tuning Curve
0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 20
200
400
600
800
1000
1200
Vin/V
Fre
quen
cy/M
Hz
Vin_max=1.8VVin_min=Vtn=0.5V
Fmax=1.068GHzFmin=83.26MHz
Kvco=758MHz/V
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Divide by 5 Circuit
Sequence:
000001010011100
Synchronous Reset
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High-speed Phase Frequency Detector
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Charge-pump
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DPLL Schematic
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DPLL Test-bench
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Simulation Result
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Simulation Result
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Simulation Result
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Simulation Result-Locked
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Measurement Result
Output Frequency 750.00MHz
Jitter 10.2ps
Lock time ~0.5 us
Key Parameters of DPLL:
Natural Frequency (Bandwidth)Matching (delay, current of charge-pump)Speed (Divide-by-5)