25 nm omega finfet: three-dimensional process and device

25 nm Omega FinFET:Three-dimensional Process

and Device Simulations

Abstract

This Sentaurus simulation project provides a template setup for three-dimensionalprocess simulation and device simulations of Omega FinFETs. The three-dimensional process simulation is based on a particularly robust approach in whichgeometry-altering and dopant-related processing steps are executed sequentially intwo separate groups.

The Sentaurus Workbench template project also performs 3D quantum transport Id–Vgs simulations using the density gradient model.

The influence of the complex dopant redistribution during the short annealing(RTA) on the electrical characteristics of the final FinFET is discussed. In addition,the influence of quantum effects on this nanoscale device is investigated.

Version Information

This application note has been designed and verified using TCAD SentaurusVersion Z-2007.03.

Running it with previous or future versions may possibly require minor adjustments.

Synopsys and the Synopsys logo are registered trademarks of Synopsys, Inc.

Copyright © 2007 Synopsys, Inc. All rights reserved.

Introduction

Shrinking feature sizes and novel device designs increasethe need for three-dimensional process and devicesimulations. TCAD Sentaurus offers a unique approach torobust 3D process simulation, which is relevant to manymodern applications.

This approach is based on the observation that the optimalstructure representation for the simulation of geometry-altering processing steps (patterning, etching, deposition,fill, chemical-mechanical polishing (CMP)) and dopant-related processing steps (implantation, annealing) is verydifferent. While for geometry-altering steps, it is sufficientto represent the structure as a set of boundaries, for dopant-related steps, the entire volume of the structure must berepresented by a finite-element mesh. For many moderntechnologies, it is advantageous to separate these two kindsof processing step. The advantages of this approach isconsiderable gain in simulation speed as well as animprovement in robustness. This approach requires the(time-consuming) generation of a finite-element mesh onlyonce, after all geometry-altering processing steps aremodeled, instead of after each geometry-altering processingstep.

This approach to 3D process simulation is illustrated herefor the example of a 25 nm NMOS Omega FinFET.

FinFETs are interesting candidates for scaling CMOSdevices into the nanoscale regime. However, thesenonplanar devices are inherently three-dimensional innature. Therefore, for FinFETs, any meaningful TCADprocess or device simulation must be performed in threedimensions.

Within this approach, first the geometric process modelingtool (here, Sentaurus Structure Editor in process emulationmode) executes all geometry-altering processing steps andsaves all intermediate device structures before dopant-related processing steps. In a second pass, SentaurusProcess automatically recreates the intermediate devicestructures and performs all implant and anneal steps [1].

A Sentaurus Workbench split has been added that allowsusers to select between using Sentaurus Process to simulatethe implantation and annealing steps, or to skip this step anduse analytic profiles. This split can be used for quick tests.

After the process simulation, the Id–Vgs curves for a low-drain bias and high-drain bias are simulated and relevantelectrical parameters, such as threshold voltages and draincurrent levels, are extracted.

It is assumed that the user is familiar with the Sentaurus toolsuite, in particular, with Sentaurus Workbench, SentaurusProcess, Sentaurus Structure Editor, Sentaurus Device, and

Inspect. For an introduction and tutorials, refer to theSentaurus training material.

The focus of this project is to provide a setup that can beused as is or adapted to specific needs. The documentationfocuses on aspects of the setups. For details about tool usesand specific tool syntax, refer to the respective manuals.

Process flow

The process flow used here is similar to the flow presentedby F.-L. Yang et al. [2][3]. Figure 1 to Figure 9 show thedevice structure at various stages of the process flow.Exploiting the symmetry of the structure, only the drain-halfof the FinFET is modeled. The process flow consists of thefollowing steps.

The starting material is an SOI wafer with a top silicon layerthickness of 50 nm. The top silicon layer has initially auniform boron concentration of 5 x 1018 cm–3. Alllithographic patterning is based on a line width of 45 nm.

1. Fin Mask Definition

1.1 Deposit a protective hard mask

1.2 Define an intermediate mask

1.3 Isotropic deposition of nitride (25 nm)

1.4 Anisotropic etching of nitride

1.5 Strip intermediate mask

This sequence of processing steps results in a 25 nm widemask, which is well below the assumed lithographiccapabilities (45 nm).

Figure 1 Device structure after Step 1.3. Region colors correspond tomaterials as follows: pink=silicon, magenta=polysilicon,brown=oxide, gold=nitride, green=hard mask.

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Copyright © 2007 Synopsys, Inc. All rights reserved. 3

2. Source/Drain Mask Definition

2.1 Define an intermediate source/drain mask

2.2 Anisotropic deposition of a new nitride layer

2.3 Etch source/drain mask, lift-off of nitride layer

Figure 2 Device structure after Step 2.3.

To define the mask for the source/drain area, the lift-offtechnique is used. First, a mask in defined, which covers thechannel fin. Then, another nitride layer is depositedanisotropically, such that the part of the newly creatednitride layer, which covers the source/drain, is not in contactwith the part that is on top of the resist layer. Next, the resistis removed by an isotropic (wet) etch process. Then, theunsupported nitride layer, which used to be on top of theresist, is flushed way with the solvent. This process ismodeled with Sentaurus Structure Editor by deleting theresist region as well as the part of the nitride that was on topof the resist.

3. Fin and Source/Drain Area Creation

3.1 Etch protective hard mask and silicon layer

3.2 Strip intermediate nitride mask

This sequence of processing steps cuts out the dog bone–shaped silicon patch, which will form the channel fin aswell as the source and drain areas.

4. Omega Creation

4.1 Isotropic etching of buried oxide (7 nm)

4.2 Strip protective hard mask

To obtain an even better control of the gate over the channel,the buried oxide is etched isotropically and, therefore, isslightly undercut. This makes room for the gate material towrap around the channel fin.

5. Gate Definition

5.1 Deposit gate oxide (2 nm)

5.2 Fill with polysilicon and CMP

5.3 Define gate mask

5.4 Etch polysilicon using isotropic underetch (gatetrim)

5.5 Strip gate mask

Figure 3 Device structure after Step 5.1. The view focuses on the underetchburied oxide, which allows the polysilicon gate to penetrate underthe fin.

After depositing the gate oxide, the entire structure is filledwith polysilicon. The gate mask is created using thelithographic line width of 45 nm. However, during thepolysilicon etch, a mix of anisotropic (95%) and isotropic(5%) etching is applied, resulting is a gate length of 25 nm,that is, much shorter than the lithographic line width.

6. Extension Spacer Formation

6.1 Isotropic oxide deposition (2 nm)

6.2 Isotropic nitride deposition (5 nm)

6.3 Anisotropic nitride etching


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4 Copyright © 2007 Synopsys, Inc. All rights reserved.


An extension spacer is defined to prevent the penetration ofthe extension implants under the gate due to the inherentlateral straggle.

7. Extension Implantation (Dose=2.5 x 1013 cm–3, Energy=7.5 keV)

7.1 First arsenic implantation (Tilt=45o, Rotation=270o)

7.2 Second arsenic implantation (Tilt=45o, Rotation=90o)

The extension implantation is performed by SentaurusProcess. To obtain a more uniform doping profile at the leftand right sides of the fin, the implantation is performed intwo steps. The implantation directions are shown inFigure 6, which also shows the as-implanted profile afterthe first implantation.

Figure 6 As-implanted arsenic profile after Step 7.1. Arrows indicate thedirection of the implantation ion beams for the first (solid) andsecond (dashed) extension implant. For better viewing, only the(transparent) silicon layer as well as three arsenic isosurfaces areshown.

8. Source/Drain Spacer Formation

8.1 Isotropic nitride deposition (40 nm)

8.2 Anisotropic nitride etching


The source and drain spacer is created using the sametechnique as used for the extension implant, but this spaceris much thicker.

9. Source/Drain Implantation

9.1 Phosphorus (Dose=4 x 1014 cm–3, Energy=15 keV)

To ensure a relatively uniform doping in the source/drainarea, phosphorus is used. It penetrates deeper than arsenicand diffuses faster during activation/annealing. Figure 8shows the as-implanted phosphorus profile.

Figure 8 As-implanted phosphorus profile after Step 9. Arrow indicates thedirection of the implantation ion beam. For better viewing, only the(transparent) silicon layer and four phosphorus isosurfaces areshown.

10. Rapid Thermal Anneal (1 s at 1025 K, with a 3 s ramp-up and a 2 s ramp-down)

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Figure 9 Final net dopant distribution after Step 10. For better viewing, onlythe silicon layer is shown.

The activation/annealing is simulated by Sentaurus Processusing the pair diffusion model. The silicon layer is assumedto have initially a uniform boron concentration of5 x 1018 cm–3. However, due to the complex interaction ofall dopants (arsenic, phosphorus, and boron) with pointdefects as well as among themselves via the electric field ofthe charge impurities, the boron distribution is nonuniformafter the activation/annealing.

Figure 10 Final phosphorus distribution along the xz plane at the center ofthe device structure (y=0).

Figure 10 shows the final phosphorus distribution along thexz plane at the center of the device structure (y=0).Figure 11 shows the final arsenic distribution along the xyplane at a z-coordinate, which corresponds to 75% of thesilicon layer height. Figure 12 shows the final borondistribution along the same plane as in Figure 11.

It can be seen clearly that during the annealing process,boron is redistributed in a complex fashion: The arsenicextension implant introduces a large amount of interstitials,which during the annealing diffuse quickly to the surfacewhere they recombine. As boron diffuses only as boron–interstitial pairs, boron is transferred to the surface in thisprocess. Due to a small volume in the channel fin, a limitedamount of boron is available and, therefore, the boronpileup at the surface in the extension area is accompanied by

a corresponding depletion of boron in the center of thechannel fin in the extension area.

Near the p-n junction, the electric field from the arsenic ionsslightly depletes the boron concentration on the p-side and,further at the channel–gate interface, boron segregationincreases the surface concentration by approximately 7%.

Figure 11 Final arsenic distribution along the xy plane at a z-coordinate,which corresponds to 75% of the silicon layer height.

Figure 12 Final boron distribution along the same plane as in Figure 11.

11. Contact Formation

Finally, the contact areas are etched free from the screeningoxide (deposited in Steps 5.1 and 6.1) and electricalcontacts are defined for use in the device simulation.

General simulation setup

This section describes the tool flow of the SentaurusWorkbench project. For each tool, the associated SentaurusWorkbench input parameters and the extracted parametersare discussed.

Sentaurus Structure Editor

The tool sequence for this project starts with SentaurusStructure Editor (in process emulation mode), whichgenerates the geometry of the Omega FinFET devices.

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During the process flow execution, intermediate structuresare saved for subsequent use by Sentaurus Process.

Sentaurus Process

Sentaurus Process loads the intermediate geometriesgenerated by Sentaurus Structure Editor and performs theimplantation and diffusion steps associated with eachintermediate structure. Alternatively, all process simulationscan be omitted by setting the following SentaurusWorkbench parameter:

■ Implant_Diffuse = simulated|analyticdefines whether implantation and diffusion steps aresimulated with Sentaurus Process or if analytic profilesare defined in Sentaurus Process.


The subsequent instance of Sentaurus Structure Editorfinalizes the device structure for simulation with SentaurusDevice. Contacts are assigned and the structure is remeshedwith Noffset3D.

Sentaurus Device

Sentaurus Device simulates Id–Vgs curves for a low-drainbias and high-drain bias. The simulation can be performedusing quantum or classical transport. The specificsimulation is selected by setting the following SentaurusWorkbench parameters:

■ Models = Quantum|Classic selects if quantumor classical transport simulations are performed.

■ Vdd [V] defines the supply voltage. Here, it is set to1.0.

■ Vds [V] defines the drain bias for the Id–Vgs sweep.Here, it is set to 0.05 and 1.0.

■ IdVg = 0|1 is a logical flag. The Id–Vgs sweep isperformed only if the flag is 1.

Inspect

Inspect plots the Id–Vgs characteristics and extracts:

■ Vtgm [V]: Threshold voltage defined as theintersection of the tangent at the maximum gm with theVgs axis.

■ Vti [V]: Threshold voltage defined as Vgs at whichId = 100 nA.

■ Imax [A]: Id at Vds = Vds and Vgs = Vdd.

■ I0 [A]: Id at Vds = Vds and Vgs = 10 mV.

■ SS [mV/decade]: Subthreshold swing.

■ gm [S]: Maximum transconductance.

■ Ion [A/ μm]: Imax/50 nm.

■ Ioff [A/ μm]: I0/50 nm.

Tool-specific setups


Process emulation mode

All geometry-altering process steps (that is, Steps 1–6, 8,and 10) are modeled by Sentaurus Structure Editor inprocess emulation mode. In this mode, the input commandsare given in a process-oriented language. For example, thecommand that executes the gate oxide deposition (Step 5.1)is:

(sdepe:depo "material" "Oxide" "thickness" (* 2 nm))

and the commands that execute the gate definition(Steps 5.3 and 5.5) are:

(sdepe:generate-mask "POL" (list(list 0 (* -72 nm) (* 22.5 nm) (* 120 nm))))

(sdepe:pattern "mask" "POL" "polarity" "light" "material" "Resist" "thickness" (* 50 nm))

(sdepe:etch-material "material" "PolySi" "depth" (* 66 nm) "overetch" (* 10 nm) "type" "iso" "algorithm" "lopx")

Sentaurus Structure Editor is built around the powerfulACIS solid geometry modeling kernel, which is used inmany professional CAD applications for various industries.The tremendous advantage in using ACIS solid modeling tomodel geometry-altering processing steps in 3D is thatACIS provides an optimized data structure for representingcomplex geometries. For example, curved boundaries aredescribed as continuous analytic surfaces rather thandiscretized polyhedral surfaces.

Sentaurus Structure Editor also allows users to take verydetailed control of the geometry. For example, the roundingof the fin edges can be set explicitly.

The motivation for this is: During real processing, shapecorners tend to be rounded off (see, for example, the TEMgraphs in the literature [2][3]). These rounding effects havea considerable influence on the electrical characteristics ofthe final device, because they alter the electrical fielddistribution and strength in the corner regions, which formparasitic edge transistors (see Results and discussion onpage 10). The influence of these rounded edges can bestudied precisely by explicitly selecting the rounding radiusof the channel fin edges and using the fillet-edgesoperation of Sentaurus Structure Editor. Here, a radius of20% of the channel width is used.


‘Paint-by-numbers’ scheme

The key element of the automated interface betweenSentaurus Structure Editor and Sentaurus Process is the‘paint-by-numbers’ scheme, which for this example worksas follows.

Sentaurus Structure Editor saves snapshots of the devicestructure during the execution of the process flow forSentaurus Process to perform the dopant-related processingsteps. For the example discussed here, after the creation ofthe extension spacer (Step 6), a snapshot labeled ‘EXT’ ofthe structure is saved. After the creation of the source/drainspacer (Step 8), a second snapshot labeled ‘SDI’ is saved.For example, the Sentaurus Structure Editor commands forsaving the EXT snapshot are:

(sdepe:fill-device "material" "Gas" "height" Zgas)(part:save "n@node@_EXT.sat")(sdepe:strip-material "Gas")

The first command adds a gas region, which is required forSentaurus Process. The second command saves thesnapshot, and the final command removes the gas region forfurther processing within Sentaurus Structure Editor.

At the end of the flow, Sentaurus Structure Editor takes bothsnapshots and creates a ‘union structure,’ which contains theunion of all regions in both structures. The union structure iscreated with the commands:

(sdesp:begin)(sdesp:define-step "EXT" "n@node@_EXT.sat")(sdesp:define-step "SDI" "n@node@_SDI.sat")(sdeio:save-dfise-bnd (get-body-list)"n@node@_msh.bnd")

(sdesp:finalize "n@node@_sprocess_sde.tcl")

The first four commands generate the union structure andthe last command creates the ‘paint-by-numbers’ table,which lists all regions in the union structure, includingintermediate regions resulting from the overlaying of thetwo snapshots. The ‘paint-by-numbers’ table lists, for eachsnapshot, which material properties are to be assigned toeach region in order to recover the device structure of therespective snapshot. For example, to recover the EXTsnapshot, the region corresponding to the source/drainspacer region is assigned the material property ‘Gas,’ that is,it is transparent for the purpose of the extension implant.

Sentaurus Process loads the union structure as well as the‘paint-by-numbers’ table using:

source n@previous@_sprocess_sde.tclinit bnd=n@previous@_msh info=2

It then discretizes the union structure and creates a finite-element mesh for the simulation of implantation anddiffusion, using the internal meshing engine MGOALS.Figure 13 on page 9 shows the mesh created by MGOALS.

Sentaurus Process recreates the device structure after thecreation of the extension spacer by applying the materialsettings specified in the ‘paint-by-numbers’ table for theEXT snapshot. This is performed with a single, concisecommand:

recreate_step EXT

Similarly, the device structure is switched to geometry afterthe formation of the source/drain spacer by applying thematerial settings specified in the ‘paint-by-numbers’ tablefor the SDI snapshot:

recreate_step SDI

Another advantage of this approach is that the 3D mesh iscreated only once during the entire process. This iseconomical because it avoids the necessity to create theCPU-intensive 3D mesh repeatedly after each geometry-altering processing step. It also improves accuracy becauseit avoids inherent interpolation errors when mapping dopingprofiles from one mesh to the next. For example, here, themesh remains unchanged when switching from the EXT tothe SDI snapshot.

Note that Sentaurus Structure Editor is extremely efficientin modeling the geometry-altering processing steps. Themodeling of the 3D geometry through the entire processflow as described in Process flow on page 3 takes less than2 minutes on a standard desktop running under Linux. Thecreation of a single 3D mesh for a complex device structurecan take considerably longer than that. For example, for theFinFET discussed here, MGOALS needed approximately5 minutes to create a high-quality finite-element mesh.

Common parameterization variables

In the Sentaurus Workbench project, the process flow isexecuted by a sequence of three tool instances (SentaurusStructure Editor—Sentaurus Process—Sentaurus StructureEditor). All three tool instances share the definitions ofparameterization variables. To access the definitions ofthese variables, select in the tool row of the Family Treeview the icon of the first instance of Sentaurus StructureEditor, and right-click. From the shortcut menu, select EditInput > Parameter. The text editor opens with the contentof the file sde.par. The structure of the parameter file is:

<name> <value> <unit> [<comment>]

where <name> is the name of a parameter variable and<value> is the numeric value that is assigned to it.<unit> can be one of the following: micrometer (um),nanometer (nm), ångström (A), unitless, or all other units(1). Comments are optional. Lines that start with asemicolon (;) are considered comment lines. Blank linesare permissible. As an example, a subset of the parameterdefinitions used in Sentaurus Workbench is given here:

; Layer ThicknessesTsub 80 nm Substrate


Tbox 80 nm Burried OxideTsi 50 nm Si layerTox 20 A Gate Oxide

; Litho patametersLW 45 nm Lithographic Linewidth

; Simulation DomainXmax 0.12 umYmax 0.12 um

;- Omega rounding radius factor (fraction of Tnim)Rtop 0.2 1Rbot 0.2 1

The parameter settings are loaded into Sentaurus StructureEditor with:

(load "GEO_lib.scm")(sdemp:SetUnit "nm")

; Load Geometrical Parameters(define ParList (read-sp-par-file "pp@node@_dvs.par"))

(map sde:define-parameter (car ParList) (cadr ParList))

The macro library GEO_lib.scm provides the support forunits as well as the parameter reader read-sp-par-file. The last Scheme command map sde:define-parameter activates the parameters on the local namespace.

For Sentaurus Process, the corresponding procedure is:

set Unit "um"set INPUTpar "pp@previous@_dvs.par"source readinput.tcl

NOTE It is not necessary to declare the parametersexplicitly in the Sentaurus Structure Editor or SentaurusProcess input files. In addition, this feature relies on thelocal files gtooldb.tcl, GEO_lib.scm,readinput.tcl, and sde.par.

Sentaurus Process

Sentaurus Process is designed as a simulator that worksindependently of the dimensionality of the structures to besimulated. Therefore, model and parameter settings, as wellas the processing-step definitions, are the same for 1D, 2D,and 3D simulations. For the 3D Omega FinFET simulatedhere, the analytic implantation model is used. For the pointdefects, the ‘plus one’ model is activated. For the activation,the solid solubility model is used. To capture the influenceof the nonequilibrium point-defect concentrations on thediffusivity of the dopants (here, phosphorus, arsenic, andboron), the advanced pair-diffusion model is used.

The MGOALS-generated mesh, shown in Figure 13, hasapproximately 30000 nodes. The 3D implantation stepsrequire about 30 minutes and the final RTA simulation is

completed in approximately 1.5 hours on a 2.2 GHz AMDOpteron machine under Linux, using the iterative solverILS.

Figure 13 Device structure with MGOALS mesh used by Sentaurus Process;the mesh has approximately 30000 nodes.

Device generation using Sentaurus Structure Editor and Noffset3D

In modern, deep submicron, MOS-type device structures,the channel–gate oxide interface must be resolved to a veryhigh level of accuracy. The finite-element mesh mustresolve the very steep gradients of the inversion layer. Inaddition, for the accurate modeling of quantization effects,it is necessary to resolve the silicon–oxide interface on thesilicon side with a mesh spacing in the normal direction ofthe order of 1 Å or 2 Å. (With the latest implementation ofthe density gradient model, it is no longer necessary to havea fine mesh on the oxide side of the interface in order toobtain accurate size quantization results.) Ideally, the meshelements at the interface should be aligned with theboundary, that is, the element faces should be parallel ororthogonal to the boundary. For nonplanar, curvedinterfaces, this is not a trivial task. However, the Sentaurusmeshing engine Noffset3D can generate such meshes.Noffset3D is used to remesh the Omega FinFET for thedevice simulations. Figure 14 shows the mesh created byNoffset3D.

Figure 14 Detail of the Noffset3D mesh used by Sentaurus Device. The meshhas approximately 26000 nodes. The slice shows the boundary-conforming mesh along the center plane of the device (x=0).

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Noffset3D is called from within Sentaurus Structure Editorwith:

(system:command "noffset3d -F tdr n@node@_msh")

It must be noted that only half of the FinFET structure iscreated by Sentaurus Structure Editor and meshed withMesh. It is subsequently reflected about the vertical axis toobtain the full device. The reflection is performed inSentaurus Structure Editor by a system call to the utilitySentaurus Data Explorer (tdx):

(system:command "tdx -mtt -x -ren drain=sourcen@node@_msh_pof n@node@_msh")

The option -x instructs Sentaurus Data Explorer to reflectthe device along an axis defined by . The givenhalf-structure has three contacts (drain, gate, andsubstrate) that are defined in sde_dvs.cmd. Of these,the gate and substrate contacts touch the axis ofreflection and, upon reflection, are extended and therebypreserve their names. However, the drain contact in thereflected half is named drainmirrored by default. Thiscontact is explicitly renamed source with the command-line option -ren of Sentaurus Data Explorer.

Device simulation using Sentaurus Device

Sentaurus Device is well known for its robustness, androbustness is particularly important when simulatingmodern, deep submicron, MOS-type devices, where a veryadvanced set of transport models must be used. Forexample, for the Omega FinFET structure considered here,the body may not be fully depleted. Therefore, thecontinuity equations for both electrons and holes must besolved simultaneously. The very short gate length of 25 nmmandates the use of the hydrodynamic transport model.Further, the thin oxide thickness (2 nm) and relatively highbody doping level (~5 x 1018 cm–3) require theconsideration of quantization effects. Here, the advancedquantization model (density gradient model) is used. Unlikeother approaches to model quantization effects such as 1DPoisson–Schrödinger and the modified local-densityapproximation (MLDA), the density gradient model is alsoapplicable to nonplanar 3D structures.

Within the density gradient model, an additional partialdifferential equation is solved to determine the effectivequantum potential. For the 3D FinFET, Sentaurus Devicesolves self-consistently five partial differential equations(Poisson equation, electron and hole continuity equations,electron energy balance equation, and the quantum potentialequation). Yet for the structure with approximately 26000nodes, the run-time for an Id–Vgs sweep remains reasonable(2 hours for the low-drain bias sweep and 3 hours for thehigh-drain bias sweep on a 2.2 GHz AMD Opteron machineunder Linux, using the iterative solver ILS).

Extraction and visualization with Inspect

In the Sentaurus Workbench tool flow, Sentaurus Device isfollowed by the visualization tool Inspect, which plots thecorresponding I–V characteristics and extracts relevantelectrical parameters as discussed in Inspect on page 7.

The extraction setup used here is similar to the onediscussed in Sentaurus Technology Template: CMOSCharacterization. Refer to the documentation for thatproject for details about visualization and parameterextraction.

Results and discussion

Figure 15 shows the electron concentration at four crosssections of the fin for the bias point Vgs = Vds = 1 V. It canbe seen that the carrier concentration is not uniform alongthe perimeter of the fin (channel). The highestconcentrations are found near the four corners of the fin. Forthis reason, an accurate control of the shape of the fincorners is important for the accurate modeling of OmegaFinFETs. The slice at the drain side (12.5 nm) shows areduced electron concentration due to the pinch-off.

Figure 15 Electron concentration at four cross sections of the fin for the biaspoint Vgs = Vds = 1 V. Slices are taken at the middle of the channel(0 nm), at the edges of the gate ( 12.5 nm), and inside theextension area ( 25 nm).

Figure 16 on page 11 shows a two-dimensional cut of theelectron distribution at the center of the device from sourceto drain at the bias point Vgs = Vds = 1 V. The top graphicshows the results of a quantum transport simulation (that is,with the density gradient model), while the lower graphicshows the corresponding classical results. It can be seenclearly that the peak of the electron distribution for thequantum transport simulation occurs approximately 7 Åaway from the silicon–oxide interface, while for theclassical simulation, the peak is at the interface. This is theresult of the quantum-mechanical size quantization in thehigh transversal field of the channel.

x xmin=

1.5e+191.1e+197.7e+184.0e+18

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0 nm-12.5 nm

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Figure 16 Electron concentration in the FinFET for the bias point Vgs = Vds =1 V for a cut along the center plane (y=0) from source to drain;(top) quantum transport and (bottom) classical transport.

Figure 17 shows the low-drain and high-drain bias Id–Vgs assimulated with Sentaurus Device. The resulting keyelectrical parameters are mostly similar to the experimentalvalues reported in the literature [2]:

■ Threshold voltage Vt = 318 mV

■ Ion = 995 μA/μm

■ Ioff = 5 nA/μm

■ DIBL = 66 mV/V

■ Subthreshold swing = 71 mV/decade

(Following [2], the drain currents were scaled with thesilicon layer thickness of 50 nm and not with the fincircumference.)

The dashed lines in Figure 17 show the correspondingresults of a classical transport simulation (that is, omittingthe density gradient model). It is clear that quantum effectslead to a threshold voltage shift of 60 mV. For this device,this corresponds to 20% of the threshold voltage,underscoring the importance of quantum transportsimulations for modern CMOS devices.

When using analytic doping profiles, the threshold voltageis 20% lower compared to runs based on simulated profiles,because the effects of boron redistribution as discussed atthe end of Process flow on page 3 are neglected.

Figure 17 Drain current as function of gate voltage for a drain bias of 50 mV(blue) and 1 V (red). Solid lines are quantum transport (includingthe density gradient model) and dashed lines are classicaltransport.

References[1] The process flow considered does not contain an oxidation

step. See “Sentaurus Suite of TCAD Products in VersionX-2005.10,” TCAD News, October 2005, for a discussion onsimulation of 3D oxidation with Sentaurus Process.

[2] F.-L. Yang et al., “25 nm CMOS Omega FETs,” in IEDMTechnical Digest, San Francisco, CA, USA, pp. 255–258,December 2002.

[3] F.-L. Yang et al., “35nm CMOS FinFETs,” in Symposium onVLSI Technology, Honolulu, HI, USA, pp. 104–105, June2002.

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10-8

10-9

10-10

0 0.2 0.4 0.6 0.8 1Gate Voltage [V]

Dra

in C

urre

nt [A

]

QT 50 mVQT 1 VCl 50 mVCl 1 V


25 nm omega finfet: three-dimensional process and device

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