2011-8 finfet and the concept behind it

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    FinFET 3D Transistor &the Concept Behind It

    Chenming Hu, August 20111

    Chenming HuUniv. of Calif. Berkeley

    http://www.eecs.berkeley.edu/~hu/

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    Intel will use 3D FinFET at 22nm

    Most radical change in decades

    There is a competing SOItechnology

    May 4 2011 NY Times Front Page

    Chenming Hu, August 20112

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    New MOSFET Structures

    Chenming Hu, August 2011

    Cylindrical FET

    Ultra Thin Body SOI

    3

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    Vt, S, Ioff are bad &sensitive to Lg

    Dopant fluctuations.

    Requiring higher Vt, Vdd, and

    power consumption higher design cost

    Good Old MOSFET Nearing Limits

    Finally painful enough for change.Chenming Hu, August 2011

    4

    0.0 0.3 0.6 0.910 -11

    10 -9

    10 -7

    10 -5

    10 -3

    D r a

    i n C u r r e n

    t , I D

    S ( A /

    m )

    Gate Voltage, VGS (V)

    Sizeshrink

    Smallersize

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    Why V t Variation & Swing are So BadL

    GateOxide

    Source Drain

    Cg

    Cd

    Gate

    Chenming Hu, August 20115

    0.0 0.3 0.6 0.910 -11

    10-9

    10 -7

    10 -5

    10 -3

    D r a

    i n C u r r e n

    t , I D

    S ( A / m

    )

    Gate Voltage, V GS (V)

    Size

    shrink

    Smallersize

    MOSFET becomes resistor at verysmall L Drain competes with Gate tocontrol the channel barrier.

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    Making Oxide Thin is Not Enough

    Gate cannot control theleakage current paths

    that are far from the gate .

    Gate

    Source Drain

    Leakage Path

    Chenming Hu, August 20116

    C.Hu,Modern Semicon. Devices for ICs 2010, Pearson

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    FinFET- 1999Undoped Body. 30nm etched thin fin.Vt set with gate work-function.

    X. Huang et al., IEDM, p. 67, 1999

    -0.6

    -0.4

    -0.2

    0.0

    0.2

    0.4

    0.6

    0 10 20 30 40 50Lg [nm]

    V t [ V ]

    Vt at 100 nA/m, Vd = 0.05 V

    Fin width: 20 nm

    Chenming Hu, August 20118

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    FinFET Leakage Path

    S D

    C.Hu,Modern Semicon. Devices for ICs 2010, Pearson

    Body thickness is the new scaling parameter.

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    Two Improvements to FinFET

    Chenming Hu, August 201112

    Original FinFET had thick oxide on fin top& used SOI for process simplicity.

    2002 FinFET with thin oxide on fin top.F.L.Yang et al. (TSMC) 2002 IEDM, p. 225.

    2003 FinFET on bulk substrate.

    T. Park et al. (Samsung) 2003 VLSI Symp.p. 135.

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    STI

    Gate

    SiSTISTI

    Gate

    SiSTI

    State-of-the-Art FinFET

    20nm Hi Perf C.C. Wu et al.,2010 IEDM

    Chenming Hu, August 201113

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    2nd Way to Eliminate Si far from GateUltra-thin-body SOI (UTB-SOI)

    No leakage path far from the gate.

    1.E-12

    1.E-10

    1.E-08

    1.E-06

    1.E-04

    1.E-02

    0 0.2 0.4 0.6 0.8 1

    Gate Voltage [V]

    D r a

    i n C u r r e n

    t [ A / u m

    ]

    Tsi =8nmTsi =6nmTsi =4nm

    Y-K. Choi, IEEE EDL, p. 254, 2000

    Gate

    Source DrainUTBSiO2

    Si

    Chenming Hu, August 201114

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    Y-K. Choi et al, VLSI Tech. Symposium, p. 19, 2001

    3nm Silicon Body, Raised S/DUTB-SOI

    Chenming Hu, August 201117

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    State-of-the-Art 5nmThin-Body SOI

    ETSOI, IBMK. Cheng et al, IEDM, 2009

    Chenming Hu, August 201118

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    Both Thin-Body Transistors Provide

    Better swing.S & Vt less sensitive to Lg and Vd.No random dopant fluctuation.

    No impurity scattering.Less surface scattering (lower Eeff).

    Higher on-current and lower leakageLower Vdd and power consumptionFurther scaling and lower cost

    Chenming Hu, August 201119

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    Similarities between FinFET & UTBSOIDevice Physics

    Superior S, scalability and device variations-use body thickness as a new scaling parameter-can use undoped body for high and no RDF

    History 1996: UC Berkeley proposed both to DARPAas 25nm Transistors. 1999: demonstrated FinFET

    2000: demonstrated UTB-SOI Since 2001: ITRShighlights FinFETand UTBSOI

    Chenming Hu, August 201120

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    Main Differences FinFETbody thickness ~Lg. Investment by fab.

    UTBSOIthickness ~1/3 Lg . Investment by Soitec. FinFEThas clearer long term scalability.UTBSOImay be ready sooner than FinFET for

    some companies. FinFEThas larger Ion.UTBSOIhas a good back-gate bias option.

    STI

    STI

    Si

    Gate 1 Gate 2UTBSOI

    FinFETChenming Hu, August 2011 21

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    What May Happen

    FinFETwill be used at 22nm by Intel andlater by more firms to

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    Berkeley S hort-channel IGFET Model 1997: became first industry standard

    MOSFET model for IC simulation

    BSIM3, BSIM4, BSIM-SOI used byhundreds of companies for design of ICs worth half trill ion dollars

    BSIM models of FinFET and UTBSOIare available free

    BSIM SPICE Models

    Chenming Hu, August 201123

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    Chenming Hu, August 201125

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    Chenming Hu, August 201126

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    Chenming Hu, August 201127

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    FinFET and UTB-SOI allows lower Vt

    and Vdd Lower power. Body thickness is a new scaling

    parameter Better short channel

    effects to and beyond 10nm. Undoped body Better mobility and

    random dopant fluctuation.

    BSIM models of FinFET and UTBSOIare available free

    Summary

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