finfet 3d transistor & the concept behind it

28
FinFET 3D Transistor & the Concept Behind It Chenming Hu, August 2011 1 Chenming Hu Univ. of Calif. Berkeley http://www.eecs.berkeley.edu/~hu/

Upload: doankien

Post on 03-Jan-2017

256 views

Category:

Documents


4 download

TRANSCRIPT

Page 1: FinFET 3D Transistor & the Concept Behind It

FinFET 3D Transistor & the Concept Behind It

Chenming Hu, August 2011 1

Chenming HuUniv. of Calif. Berkeley

http://www.eecs.berkeley.edu/~hu/

Page 2: FinFET 3D Transistor & the Concept Behind It

2

• Intel will use 3D FinFET at 22nm

• Most radical change in decades• There is a competing SOI

technology

May 4 2011 NY Times Front Page

Chenming Hu, August 2011 2

Page 3: FinFET 3D Transistor & the Concept Behind It

3

New MOSFET Structures

Chenming Hu, August 2011

Cylindrical FET

Ultra Thin Body SOI

3

Page 4: FinFET 3D Transistor & the Concept Behind It

4

• Vt, S, Ioff are bad & sensitive to Lg

• Dopant fluctuations.

Requiring• higher Vt, Vdd, and

power consumption• higher design cost

Good Old MOSFET Nearing Limits

Finally painful enough for change.Chenming Hu, August 2011

4

0.0 0.3 0.6 0.910-11

10-9

10-7

10-5

10-3

Dra

in C

urre

nt, I

DS (

A/µ

m)

Gate Voltage, VGS (V)

Size shrink

Smaller size

Page 5: FinFET 3D Transistor & the Concept Behind It

Why Vt Variation & Swing are So BadL

Gate

Oxide

Source Drain

Cg

Cd

Gate

Chenming Hu, August 2011 5

0.0 0.3 0.6 0.910-11

10-9

10-7

10-5

10-3

Drai

n Cu

rren

t, I DS

(A/µ

m)

Gate Voltage, VGS (V)

Size shrink

Smaller size

MOSFET becomes “resistor” at very small L – Drain competes with Gate to control the channel barrier.

Page 6: FinFET 3D Transistor & the Concept Behind It

Making Oxide Thin is Not Enough

Gate cannot control theleakage current paths

that are far from the gate.

Gate

Source Drain

Leakage Path

Chenming Hu, August 2011 6

C.Hu,”Modern Semicon. Devices for ICs” 2010, Pearson

Page 7: FinFET 3D Transistor & the Concept Behind It

One Way to Eliminate Si far from Gate

Gate

Gate

Source Drain

FinFET body is a thin fin N. Lindert et al., DRC paper II.A.6, 2001

Sour

ce

Dra

in

Fin WidthFin Height

Gate Length

Chenming Hu, August 2011 7

A thin body controlled by gate from more than one side.

Page 8: FinFET 3D Transistor & the Concept Behind It

FinFET- 1999Undoped Body. 30nm etched thin fin. Vt set with gate work-function.

X. Huang et al., IEDM, p. 67, 1999

-0.6

-0.4

-0.2

0.0

0.2

0.4

0.6

0 10 20 30 40 50Lg [nm]

ΔV

t [V

]

Vt at 100 nA/μm, Vd = 0.05 V

Fin width: 20 nm

Chenming Hu, August 2011 8

Page 9: FinFET 3D Transistor & the Concept Behind It

Chenming Hu, August 2011 9

Page 10: FinFET 3D Transistor & the Concept Behind It

FinFET is “Easy” to Scale

Leakage is well suppressed if Fin thickness =or< Lg

• Thin fin and gate can be made with the same lithography and etching tools.

Chenming Hu, August 2011

Lg = 5 nm

5nm Lg TSMC2004 VLSI Symp

10nm Lg AMD2002 IEDM

3nm Lg KAIST2006 VLSI Symp

10

Page 11: FinFET 3D Transistor & the Concept Behind It

Chenming Hu, August 2011 11

FinFET Leakage Path

S D

C.Hu,”Modern Semicon. Devices for ICs” 2010, Pearson

Body thickness is the new scaling parameter.

Page 12: FinFET 3D Transistor & the Concept Behind It

Two Improvements to FinFET

Chenming Hu, August 2011 12

Original FinFET had thick oxide on fin top & used SOI for process simplicity.

• 2002 FinFET with thin oxide on fin top.F.L.Yang et al. (TSMC) 2002 IEDM, p. 225.

• 2003 FinFET on bulk substrate.T. Park et al. (Samsung) 2003 VLSI Symp. p. 135.

Page 13: FinFET 3D Transistor & the Concept Behind It

STI

Gate

SiSTISTI

Gate

SiSTI

State-of-the-Art FinFET

20nm Hi PerfC.C. Wu et al., 2010 IEDM

Chenming Hu, August 2011 13

Page 14: FinFET 3D Transistor & the Concept Behind It

2nd Way to Eliminate Si far from GateUltra-thin-body SOI (UTB-SOI)No leakage path far from the gate.

1.E-12

1.E-10

1.E-08

1.E-06

1.E-04

1.E-02

0 0.2 0.4 0.6 0.8 1

Gate Voltage [V]

Dra

in C

urre

nt [A

/um

]Tsi=8nmTsi=6nmTsi=4nm

Y-K. Choi, IEEE EDL, p. 254, 2000

Gate

Source DrainUTBSiO2

Si

Chenming Hu, August 2011 14

Page 15: FinFET 3D Transistor & the Concept Behind It

Most Leakage Flows >5nm Below Surface

Y-K. Choi et al., IEEE Electron Device Letters, p. 254, 2000Chenming Hu, August 2011

15

Page 16: FinFET 3D Transistor & the Concept Behind It

Silicon Body Needs to be <Lg/3For good swing and device variation

Y-K. Choi et al., IEEE Electron Device Letters, p. 254, 2000Chenming Hu, August 2011

16

Page 17: FinFET 3D Transistor & the Concept Behind It

Y-K. Choi et al, VLSI Tech. Symposium, p. 19, 2001

3nm Silicon Body, Raised S/DUTB-SOI

Chenming Hu, August 2011 17

Page 18: FinFET 3D Transistor & the Concept Behind It

State-of-the-Art 5nm Thin-Body SOI

ETSOI, IBM K. Cheng et al, IEDM, 2009

Chenming Hu, August 2011 18

Page 19: FinFET 3D Transistor & the Concept Behind It

Both Thin-Body Transistors Provide

• Better swing. • S & Vt less sensitive to Lg and Vd.• No random dopant fluctuation. • No impurity scattering. • Less surface scattering (lower Eeff).

•Higher on-current and lower leakage•Lower Vdd and power consumption•Further scaling and lower cost

Chenming Hu, August 2011 19

Page 20: FinFET 3D Transistor & the Concept Behind It

Similarities between FinFET & UTBSOIDevice Physics• Superior S, scalability and device variations -use body thickness as a new scaling parameter-can use undoped body for high µ and no RDF

History • 1996: UC Berkeley proposed both to DARPA as “25nm Transistors”. • 1999: demonstrated FinFET

2000: demonstrated UTB-SOI• Since 2001: ITRS highlights FinFET and UTBSOI

Chenming Hu, August 2011 20

Page 21: FinFET 3D Transistor & the Concept Behind It

Main Differences• FinFET body thickness ~Lg. Investment by fab.UTBSOI thickness ~1/3 Lg. Investment by Soitec.• FinFET has clearer long term scalability. UTBSOI may be ready sooner than FinFET for some companies. • FinFET has larger Ion. UTBSOI has a good back-gate bias option.

STISTI

SiGate 1 Gate 2

UTBSOI

FinFETChenming Hu, August 2011

21

Page 22: FinFET 3D Transistor & the Concept Behind It

What May Happen

• FinFET will be used at 22nm by Intel and later by more firms to <10nm.• Some firms may use UTBSOI to gain market from regular CMOS at 20/18/16nm.

If so, competition between FinFET and UTBSOI will bring out the best of both.

Chenming Hu, August 2011 22

Page 23: FinFET 3D Transistor & the Concept Behind It

23

Berkeley Short-channel IGFET Model• 1997: became first industry standard

MOSFET model for IC simulation• BSIM3, BSIM4, BSIM-SOI used by

hundreds of companies for design of ICs worth half trillion dollars

• BSIM models of FinFET and UTBSOI are available – free

BSIM SPICE Models

Chenming Hu, August 2011 23

Page 24: FinFET 3D Transistor & the Concept Behind It

Chenming Hu, August 2011 24

Page 25: FinFET 3D Transistor & the Concept Behind It

Chenming Hu, August 2011 25

Page 26: FinFET 3D Transistor & the Concept Behind It

Chenming Hu, August 2011 26

Page 27: FinFET 3D Transistor & the Concept Behind It

Chenming Hu, August 2011 27

Page 28: FinFET 3D Transistor & the Concept Behind It

28

• FinFET and UTB-SOI allows lower Vtand Vdd Lower power.

• Body thickness is a new scaling parameter Better short channel effects to and beyond 10nm.

• Undoped body Better mobility and random dopant fluctuation.

• BSIM models of FinFET and UTBSOI are available – free

Summary

Chenming Hu, August 2011 28