finfet and other new transistor tech hu

7/28/2019 FinFET and Other New Transistor Tech Hu

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FinFET and other NewTransistor Technologies

Chenming Hu

Univ. of California

Chenming Hu, July 2011


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2

NY Times news article:

Intel will use 3D FinFET for 22nm

Most radical change in decades

There is a competing SOI technology

May 4 2011 NY Times Front Page



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3

TSMC, IBMnew transistors soon

Since 2001 ITRS shows FinFET and

ultra-thin-body UTB-SOI as the twosuccessor MOSFETs

SOITEC UTB-SOI recently available

IBM 2009 5nm UTB SOI paper

Other Background Info



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4

New MOSFET Structures


Cylindrical FET

Ultra Thin Body SOI


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5

Vt, S (swing) and Ioff

are sensitive to Lg &

dopant variations.

high design cost high Vdd, hence

high power usage

Good Old MOSFET Nearing Limits

Finally painful enough for change.



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Power Consumption Problems

1.Not just a chip and package thermal

issue.2.ICs use a few % of worlds electricity

today and

Power per chip is growing.

IC units in use also growing.

3.If power consumption is not reduced,industry future growth is at risk.



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7

Want Low Vt and Low Ioff

Need smaller

S and less

variations of

S and Vt



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MOSFET becomes resistor at very

small L - Drain competes with Gate tocontrol the channel barrier.

0.0 0.3 0.6 0.910

-11

10-9

10-7

10-5

10-3

DrainC

urrent,ID

S(A/m

)

Gate Voltage, VGS

(V)

Size

shrink

How Vt Variation & S Got So Bad

L

Gate

Insulator

Source Drain

Cg

Cd

Gate

or larger Vd

Smaller

size



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Reducing EOT is Not Enough

Gate cannot control the

leakage current pathsthat are far from the gate.

Gate

Source Drain

Leakage Path



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One of Two Ways to Better Vt and S

The gate controls a thin body from

more than one side.

Gate

Gate

Source Drain

FinFET body is a

thin finN. Lindert et al., DRC paper II.A.6, 2001

S

ource

Drain

Fin Width

Fin Height

Gate Length



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FinFET- 1999

Undoped Body. 30nm etched thin fin.Vt set with gate work-function (SiGe).

X. Huang et al., IEDM, p. 67, 1999

-0.6

-0.4

-0.2

0.0

0.2

0.4

0.6

0 10 20 30 40 50

Lg [nm]

Vt[V]

Vt at 100 nA/m, Vd = 0.05 V

Fin width: 20 nm



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STI

Gate

SiSTI

STI

Gate

SiSTI

State-of-the-Art FinFET on Buk Si20nm Hi PerfC.C. Wu et al.,

2010 IEDM

28nm SoC

C.C. Yeh et al.,2010 IEDM



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FinFET is Easy to Scale

because leakage is well suppressed if

Fin thickness =or< LgThin fin can be made with the same Lgpatterning/etching tools.


Lg=5 nm

5nm Lg TSMC2004 VLSI Symp

10nm Lg AMD2002 IEDM

3nm Lg KAIST2006 VLSI Symp


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Second Way to Better Vt and S

Ultra-thin-body SOI (UTB-SOI)No leakage path far from the gate.

1.E-12

1.E-10

1.E-08

1.E-06

1.E-04

1.E-02

0 0.2 0.4 0.6 0.8 1

Gate Voltage [V]

Dra

inCurrent[A/um]

Tsi=8nm

Tsi=6nm

Tsi=4nm

Y-K. Choi, IEEE EDL, p. 254, 2000

Gate

Source DrainUTB

SiO2

Si



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Most Leakage Flows >5nm Below Surface

Y-K. Choi et al., IEEE Electron Device Letters, p. 254, 2000Chenming Hu, July 2011


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Y-K. Choi et al, VLSI Tech. Symposium, p. 19, 2001

3nm Silicon Body, Raised S/DUTB-SOI



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State-of-the-Art 5nm

Thin-Body SOI

ETSOI, IBMK. Cheng et al, IEDM, 2009



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Both Thin-Body Transistors Provide

Better swing.

S & Vt less sensitive to Lg and Vd.

No random dopant fluctuation.

No impurity scattering.Less surface scattering (lower Eeff).

Higher on-current and lower leakageLower Vdd and power consumptionFurther scaling and lower cost



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Back-Gate Bias Option

UTB-SOI FinFET

STI

STI

Si

Gate 1Gate 2



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Similarities1996: UC Berkeley proposed to DARPA two

25nm Transistors. Both of themuse body thickness as a new scaling parametercan use undoped body for high and no RDF1999: demonstrated FinFET2000: demonstrated UTB-SOI (Ultra-Thin Body)

Since 2001: ITRS highlights FinFET and UTBSOI

Now: Intel will use Trigate FinFET.Soitec readies +-0.5nm substrates for UTBSOI

Both FinFET & UTBSOI better than planar bulk!Chenming Hu, July 2011

ff


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Main DifferencesFinFET body thickness ~ Lg. Investment by fabs

UTBSOI thickness ~1/3 Lg. Investment by SoitecFinFET has clear long term scalability. UTBSOImay be ready sooner depending on each firms

readiness with FinFET.FinFET has larger Ion or can use lower Vdd.UTBSOI has a good back-gate bias option.

STI

STI

Si

Gate 1 Gate 2

UTBSOI

FinFETChenming Hu, July 2011

h


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What May Happen

FinFET will be used at 22nm by Intel and later

by more firms through and beyond 10nm.Some firms may use UTBSOI to gain/protectmarket at 20 or 18nm if FinFET is not option.

If so, competition between FinFET and UTBSOIwill bring out the best of both.

If not----- back to first bullet.



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FinFET BSIM Compact Model Verified

FinFET Fabricated at TSMC.

Lg = 30 nm-10um

0.0 0.4 0.8 1.20

25

50

Vd = 1.2V

Vd = 50mV

Lg = 50nm

Dr

ainCurrent(A

)

Gate Voltage (V)

1p

1n

1

1m

0.0 0.4 0.8 1.21p

10p

100p

Vd = 1.2V

Lg = 50nm

Bu

lkCurrent(A)

Gate Voltage (V)

Id-Vd

0.0 0.4 0.8 1.20

25

50

Vg = 1.2 - 0.4V

Lg = 50nm

Dra

inCurrent(A)

Drain Voltage (V)

Id-Vg Ibulk Id-Vd


M. Dunga, 2008 VLSI Tech Sym


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30

Reduce all capacitances.

Reduce C

2

ddVCf



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Vacuum-Sheath Interconnect

Etch Stop layer

Metal

Dielectric Beam

Mutual Capacitance : CM

Total Capacitance : CTOTAL

Load Capacitance : CO

CTOTAL

Delay, CM

Crosstalk Noise

J . Park, Electronics Letters, p. 1294, 2009


Effective k of Vacuum Sheath


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Effective k of Vacuum-SheathInterconnects

No Solution

B

eamD

ielectricConstant

20 30 40 50 60 70 80

Air Percentage (%)

2.25

2.9

3.3

3.6

3.9

1.3

1.41.5

1.6

1.71.8

1.92.02.1

2.22.32.4

2.5

2.6No Solution

J . Park, Electronics Letters, p. 1294, 2009Chenming Hu, July 2011

V S t R d C


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Vacuum Spacer to Reduce CGC

CGCCGOX

Gate

Contacts

CGC

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