study of pattern area reduction with finfet and sgt for lsi … · layout pattern of inverter using...

Contemporary Engineering Sciences, Vol. 6, 2013, no. 4, 177 - 190 HIKARI Ltd, www.m-hikari.com

Study of Pattern Area Reduction

with FinFET and SGT for LSI

Takahiro Kodama

Japan Process Development Co., Ltd. Minato-ku, Kokyo, Japan

Yu Hiroshima

Oi Electric Co., Ltd. Kohoku-ku, Yokohama, Japan

Shigeyoshi Watanabe

Department of Information Science Shonan Institute of Technology, Fujisawa, Japan

[email protected]

Copyright © 2013 Takahiro Kodama et al. This is an open access article distributed under the Creative Commons Attribution License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.

Abstract

The pattern area reduction with SGT and FinFET for LSI, such as inverter, NAND gates, full adder, and row decoder has been newly described. With small channel width of 8F the pattern area of inverter, NAND gates and full adders with SGT can be reduced compared with that with FinFET. This results are useful for designing system LSI for communications. With larger channel width than 8F the pattern area of inverter, NAND gates and full adders with SGT has the tendency to become larger than that with FinFET. This results are useful for designing system LSI for cell library and high end MPU. Furthermore, for designing core circuit, such as row decoder and sense amplifier, smaller pattern area can be realized with SGT compared with that with FinFET. Keywords: FinFET, SGT, pattern area, LSI, full adder, logic circuit

178 Takahiro Kodama et al. 1 Introduction Recently, the scaling of the conventional planar transistor becomes increasingly difficult because of its large short channel effect [1]. In order to overcome this problem FinFET [2][3] which use the 3 planes and SGT (Surrounding Gate Transistor) [4] which use the 4 planes as the channel for reducing the short channel effect has been developed. By using FinFET [5][6] and SGT[7][8] not only reduction the short channel effect but also the reduction of the pattern area compared with those of the conventional planar transistor can be realized. This is because not only the planar region but also the sidewall can be used as the channel for these newly proposed structure. The structure of FinFET is shown in Fig.1 (A). The drain current flows along horizontal direction as the same as conventional planar transistor. Within the small pattern area large total channel width of WP+2WD can be successfully realized. Because of these features Intel firstly produces FinFET on commercial basis as the high end CPU this year [9][10]. The structure of SGT is shown in Fig.1 (B). Four sidewalls can be used as the channel. Assuming that the sidewall channel width is defined as Ws, within the small pattern area large total channel width of 4Ws can be successfully realized. The drain current flows along vertical direction which is perpendicular to the conventional planar transistor and FinFET case. Therefore, by using SGT serial connection of transistor can be easily realized to vertical direction. Because of these features Toshiba and Samsung are planning to introduce SGT in the stacked type non-volatile memory with NAND structured cell on commercial basis [11][12][13][14]. This stacked type non-volatile memory with NAND structured cell using SGT is also adopted to newly proposed MRAM [15][16] as shown in Fig.2. (A) (B)

Figure 1: Newly proposed transistors, (A) FinFET, (B)SGT

Gate

SiO2

Substrate

Gate oxide

Sidewall Gate: WD

Planar Gate: Wp

Substrate

SiO2

Gate

Silicon pillar

Gate oxide

Sidewall channel width :Ws

Study of pattern area reduction 179

WL1

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Vss

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Fixed layer

Free layer

P+ diffusion

N+ diffusion

(A) (B)

(C) Figure 2: Configuration of stacked type MRAM memory cell (A)Equivalent

circuit, (B)Cross-sectional view (C) Top view The research of LSI with FinFET is focused on the operation speed and the power consumption. And also, the research of LSI with SGT is focused on the device technology of memory devices. The research of LSI with FinFET and SGT about the pattern area is very few. These researches are limited to the simple logic circuit such as inverter and NAND gates [17][18][19][20]. In this paper, the study of pattern area reduction with FinFET and SGT for LSI has been newly described. As the LSI various kinds of full adder circuits [21] are investigated. Furthermore, core circuit of memory such as decoder is also studied. This paper is organized as follows. Section 2 describes the design rule and the pattern area reduction of inverter with FinFET and SGT. Section 3 describes the pattern area reduction of full adder with FinFET and SGT. Section 4 presents the reduction of pattern area of row decoder circuit of high density memory with FinFET and SGT. Finally, a conclusion of this work is provided in Section 5. 2 Design rule and pattern area reduction of inverter The design rule for this study is summarized in table 1. F is feature size. In this study it is assumed that the same drain current flows, if the gate length, the channel width, and applied voltage are the same value. The channel width is set to 8F.

180 Takahiro Kodama et al.

Table 1. Design rule Layout pattern of inverter using the conventional planar transistor, SGT, and FinFET is shown in Fig.3. The channel width is 8F. The vertical length of SGT and FinFET can be reduced compared with that of planar transistor. This reduction ratio of SGT is smaller than that of FinFET. This is because design rule of active area to silicon pillar of 0.5F must be considered for designing with SGT. On the other hands, the lateral length of SGT is smaller than that of FinFET and planar transistor. This is because the extra pattern area for gate running to the vertical direction is unnecessary for SGT. This leads to the reduction of lateral length of F compared with that of FinFET and planar transistor. For SGT this reduction is larger than the smaller reduction of vertical length. As a result, the pattern area of SGT becomes smaller than that of FinFET as shown in table 2.

Figure 3: Pattern design of inverter of channel width of 8F, (A)Planar, (B)SGT, (C) FinFET

Planar SGT FinFET

Gate length F F FWiring F F F

Wiring to Wiring F F FWell isolation 3F 3F 3FContact size F×F F×F F×F

Silicon pillar size 2F×2FGate to contact 0.5F

AA to silicon pillar 0.5FSidewall channel width 3.5F

Width of planar gate F

(A) Planar 189F2 (B) SGT 96F2 (C) FinFET 105F2

7F

6F

27F

16F

15F

7F7F

Study of pattern area reduction 181

Table 2: Pattern area comparison of inverter. Pattern area with planar is set to 100. With increasing the number of input to logic circuit such as NAND and NOR gates, this tendency shown in table 2 is enhanced. This is because the difference of lateral length between SGT and FinFET increases with increasing the number of input. Figure 4: Full adder with 3/4 input NAND/NOR gates, (A)Circuit diagram,

(B)Pattern with planar, (C)Pattern with SGT, (D)Pattern with FinFET, (E)Comparison of vertical, lateral length and pattern area.

Planar SGT FinFET

Vertical length 100 59 5686 100

Pattern area 51 56Lateral length 100

100

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(A) Circuit diagram

(B) Planar 5929F2

(C) SGT 3300F2

(D) FinFET 4187F2

(E) Comparison of vertical, lateral length

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(A) Circuit diagram

(B) Planar 5929F2

(C) SGT 3300F2

(D) FinFET 4187F2


182 Takahiro Kodama et al. 3 Pattern area reduction of full adder with FinFET and

SGT Using 4 kinds of full adders the pattern area reduction with FinFET and SGT is newly estimated. 4 kinds of full adders are as follows, (1)Full adder with 3/4 input NAND/NOR gates, (2)Full adder with 2 input NAND/NOR gates, (3)Full adder with Pass transistor logic, (4)Full adder with composite gate. Fig.4 shows the estimated results of full adder with 3/4 input NAND/NOR gates ((A)Circuit diagram, (B)Pattern with planar, (C)Pattern with SGT, (D)Pattern with FinFET, and (E)Comparison of vertical, lateral length and pattern area)). The vertical length of full adder with SGT is a little longer than that with FinFET by the reason described in section 2. However, the reduction rate compared with Fig.2 is small. This is because wide wiring area must be introduced for full adder as shown in Fig.4. The lateral length of full adder with SGT is a smaller than that with FinFET and planar transistor. This is because the extra pattern area for gate running to the vertical direction is unnecessary for SGT as shown in Fig.2. As a result, the pattern area of SGT becomes smaller than that of FinFET as described in section 2. Figure 5: Full adder with 2 input NAND/NOR gates, (A)Circuit diagram,

(B)Pattern with planar, (C)Pattern with SGT, (D)Pattern with FinFET, (E)Comparison of vertical, lateral length and pattern area.

A

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Ci(A) Circuit diagram

(B) Planar 4355F2

(C) SGT 2326.5F2

(D) FinFET 3315F2


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(B) Planar 4355F2

(C) SGT 2326.5F2

(D) FinFET 3315F2


Study of pattern area reduction 183 Figure 6: Full adder with Composite gate, (A)Circuit diagram, (B)Pattern with

planar, (C)Pattern with SGT, (D)Pattern with FinFET, (E)Comparison of vertical, lateral length and pattern area.

Estimation results of other kinds of full adder, (2)-(4) is shown in Fig.5 – Fig.7. The vertical length of full adder with SGT is a little longer than that with FInFET for (2) and (4) as the same as (1). However, for the pass transistor logic case, the vertical length with SGT becomes the same value as with FinFET. This is because the feature of the pass transistor logic with the input to source or drain is compatible with the pattern of SGT. As shown in Fig.7 (C), (D) the wiring indicated by the arrow for FinFET is unnecessary for SGT. The lateral length of (2)-(4) with SGT is smaller than that with FinFET as the same as (1) case. This tendency is enhanced with increasing the average number of input (Pass transistor

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(A) Circuit diagram

(B) Planar 2320.5F2

(C) SGT 1402.25F2

(D) FinFET 1473.25F2


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(C) SGT 1402.25F2


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(A) Circuit diagram

(B) Planar 2320.5F2

(C) SGT 1402.25F2



184 Takahiro Kodama et al. Figure 7: Full adder with Pass transistor logic, (A)Circuit diagram, (B)Pattern

with planar, (C)Pattern with SGT, (D)Pattern with FinFET, (E)Comparison of vertical, lateral length and pattern area.

Logic≒ 1, 2 input NAND/NOR gates and composite gate≒ 2, 3/4 input NAND/NOR gates≒3 ) as shown in Fig.8. In Fig.8 the lateral length of 100 indicates the value for the planar transistor. As a result, the pattern area of (2)-(4) with SGT is smaller than that with FinFET as the same as (1) case. From the described estimation about 4 kinds of full adder the pattern of full adders with SGT become smaller than that with FinFET. This is the same tendency of inverter and NAND/NOR gates described in section 2. For estimating the pattern area relatively small channel width of 8F is adopted. This relatively small channel width is mainly employed to system LSI for communication.

B

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C0 S(A) Circuit diagram

(B) Planar 3785.25F2

(C) SGT 2400.75F2



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C0 S(A) Circuit diagram

(B) Planar 3785.25F2

(C) SGT 2400.75F2



Study of pattern area reduction 185 Figure 8: Relationship between average number of input and lateral length of full

adders. Fig.9 (a) shows the distribution of pattern area of system LSI for communications [22]. With increasing the channel width, the pattern area decreases monotony. This is because smaller power consumption compared with higher speed is important for system LSI for communication. Therefore, the pattern area reduction with SGT can be expected for these kinds of system LSI for communications. Figure 9: Distribution of pattern area vs channel width of the planar transistor for 3 types of system LSIs, (A)System LSI for communications, (B)Buffer circuit for high end MPU, (C)CMOS cell library.

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186 Takahiro Kodama et al. However, the channel width of 8F is small for the high speed operation of system LSI such as high end MPU. For realizing the high speed operation larger channel width must be introduced as shown in Fig.9 (B) [19][24]. Furthermore, various values of channel width are necessary for CMOS cell library [25]. For estimating the pattern area reduction dependence with SGT and FinFET on the channel width, (1)-(4) is used. Pattern area ratio SGT/FinFET is shown in Fig.10.

Figure 10: Pattern area ratio SGT/FinFET vs channel width of full adders.

Figure 11: Pattern design of inverter of channel width of 16F As increasing the channel width pattern area ratio SGT/FinFET increases monotony. Therefore, the channel width exceeds the fixed value, the pattern area with FinFET becomes smaller than that with SGT. This is because with increasing the channel width, the vertical length with SGT increases considerably compared with that with FinFET (Fig.11). With increasing of the channel width of 16F-8F=8F, the vertical length with SGT increases by 3F. On the other hands, the

Pat

tern

are

a ra

tio S

GT/

FinF

ET

+3F

+3F

+2F

+2F

SGT FinFET

+3F

+3F

+3F

+3F

+2F

+2F

+2F

+2F

SGT FinFET

Study of pattern area reduction 187 vertical length with FinFET increases by only 2F. Therefore, the pattern area reduction with FinFET can be expected for these kinds of system LSI for high end MPU and CMOS cell library. 4 Pattern area reduction of row decoder with FinFET and

SGT Low bit cost, fabrication cost per bit, is the most important issue for realizing high density memory. The bit cost is proportional to pattern area. Therefore, for realizing low bit cost small pattern area for memory cell and core circuit, such as row decoder must be realized. The block diagram of memory cell and row decoder is shown in Fig.12. For realizing the smallest pattern area of row decoder the pitch of row decoder must be equal to the lateral length of memory cell (Fig. 12 (B)). For this purpose the lateral length of the transistor within the row decoder must be smaller than the lateral length of memory cell. Figure 12: Block diagram of memory cell and row decoder, (A)Legend about the figure, (B)Pitch of row decoder is equal to lateral length of memory cell, (C) Pitch of row decoder is 2*(lateral length of memory cell). The lateral length of transistor with FinFET is equal to that of planar transistor. Therefore, due to large lateral length with FinFET the transistor can not be laid out within lateral length of memory cell. In this case pitch of row decoder must be

Pitch of row decoderLateral length of row decoder

Vertical length of row decoder

Row decoder

Lateral length of transistor

Vertical length of transistor

Transistor

Memory cell WL and gate running direction

Lateral length of memory cell

Vertical length of memory cell

WL and gate

Pitch of row decoder

Pitch of row decoder

(A) (B)(C)

188 Takahiro Kodama et al. enlarged to 2*(lateral length of memory cell) as shown in Fig.12 (C). This scheme results in the double pattern area of row decoder compared with Fig.12 (B). On the other hands, the lateral length of transistor with SGT is smaller than that with FinFET as described in section 2. Therefore, due to the smaller lateral length with SGT the transistor can be laid out within lateral length of memory cell (Fig. 12 (B)). Therefore, SGT is suitable for realizing small pattern area of row decoder compared with FinFET [26][16]. SGT is useful for designing the other core circuit, such as sense amplifier (S/A) [26]. 5 Conclusion

Figure 13: Summary of this paper The pattern area reduction with SGT and FinFET for LSI, such as inverter, NAND gates, full adder, and row decoder has been newly described. With small channel width of 8F the pattern area of inverter, NAND gates and full adders with SGT can be reduced compared with that with FinFET. This results are useful for designing system LSI for communications. With larger channel width than 8F the pattern area of inverter, NAND gates and full adders with SGT has the tendency to become larger than that with FinFET. This results are useful for designing system LSI for cell library and high end MPU. Furthermore, for designing core circuit, such as row decoder and sense amplifier, smaller pattern area can be realized with SGT compared with that with FinFET. These results are useful for designing future low cost system LSI and high density memories. References [1] International Technology Roadmap of Semiconductor 2003 Edition, 2003

Semiconductor Industry Association. [2 ]K. Hieda et. al., "Effect of a new trench-isolated transistor using side wall

gates”, IEEE Trans. Electron Devices, vol.36, no.９, pp.1615-1619, 1989.

SGT vs FinFET

Stacked type cell

LSI for communicationCore circuit (Dec. S/A)

Cell libraryHigh end MPU

SGT SGT SGT

FinFETFinFET

High density memory

System LSI

Study of pattern area reduction 189 [3] D. Hisamoto et. al., “FinFET a self-aligned double gate MOSFET scarable

beyond 20nm”, IEEE Trans. Electron Devices, vol.47, no.12, pp.2320-2325, 2000.

[4] H. Takato et al., ”Impact of SGT for ultra - high density LSIs”, IEEE Trans.

Electron Devices, vol. 38, pp. 573 - 578, 1991. [5] M. Wada, K. Hieda, and S. Watanabe, “ A folded capacitor cell for future

megabit DRAMs”, IEDM Tech. Dig., pp.244-247, 1984. [6] S. Watanabe, “Design methodology for system LSI with TIS (Trench Isolated-

transistor using sidewall gate)”, IEICE. Trans. on Electronics, vol.J88-C, no.12, pp.1208-1218, 2005.

[7] N. Nitayama et al., “Multi-pillar surrounding gate transistor (M-SGT) for

compact and high-speed circuits,” IEEE Trans. Electron Devices, Volume: 38, Issue: 3, 579-583, 1991.

[8] K. Sunouchi et al., “A surrounding gate transistor (SGT) cell for 64/256Mbit

DRAMs”, IEDM Tech. Dig., pp.23-26, 1989. [9] Intel, Intel 22nm 3-D Tri-Gate Transistor Technology,

http://download.intel.com/newsroom/kits/22nm/pdfs/22nm- Announcement_Presentation.pdf

[10] S. Davnaraju et. al., “A 22nm IA multi-CPU and GPU system on chip”, ISSCC Dig. Tech. Papers, 2012.

[11] T. Tanaka et al., "Bit cost scalable technology with punch and plug process

for ultra high density flash memory,” Symp. on VLSI Technology ,2007. [12] Y. Fukuzumi et.al., "Optimal Integration and Characteristics of Vertical Array

Device for ultra-High Density, Bit-Cost Scalable Flash Memory”, IEDM 2007.

[13] R. Katsumata et al., “Pipe-shaped BiCS flash memory with 16 stacked layers

and multi-level-cell operation for ultra high density storage devices,” Symp. on VLSI Technology, 2009.

[14] J. Jang et al., “Vertical cell array using TCAT (Terabit Cell Array Transistor)

technology for ultra high density NAND flash memory,” Symp. on VLSI Technology, 2009.

[15] S. Tamai and S. Watanabe, “Study for reading method of stacked NAND type

MRAM using spin transistor, ” IEICE Trans. on Electronics, vol.J91-C, no. 11, pp. 666-667, 2008.

[16] S. Tamai and S. Watanabe, “Design method of stacked type MRAM with

NAND structured cell”, Contemporary Engineering Sciences, vol.6, no.2, pp.69-86, 2013.

[17] K. Sakui and T. Endoh, “A compact space and efficient drain current design

for multi pillar vertical MOSFETs,” IEEE Trans. Electron Devices, vol.57, no.8, pp.1768-1773, 2010.

190 Takahiro Kodama et al. [18] K. Sakui and T. Endoh, “A new vertical MOSFET “Vertical Logic Circuit

(VLC) MOSFET” suppressing asymmetric characteristics and realizing an ultra compact and robust logic circuit,” Solid state electronics, vol.54, issue 11, pp.1457-1462, 2010.

[19] S. Watanabe, “New design method of tapered buffer circuit with TIS (Trench

- Isolated - transistor using Side wall gate) and its application to high-density DRAMs,” IEICE, vol.J86-C, no.3, pp.301-306, 2003.

[20] Y. Hiroshima and S. Watanabe, ”New design technology of independent-gate

controlled stacked type 3D transistor for system LSI”, IEICE Trans. on Electronics, vol.J92-C, no.3, pp.94-103, 2009.

[21] J. Rabaey et. al., ”Digital Integrated Circuit (A design perspective)”,

Prentice hall, 2003. [22] H.Ishikuro, M.Hamada, K.Agawa, S.Kousai, H.Kobayashi, D.Nguyen, and

F.Hatori, “A single-chip CMOS bluetooth transceiver with 1.5MHz IF and direct modulation transmitter,” ISSCC Dig. Tech. Papers pp.68-69, 2003.

[23] T. Endoh, K. Shinmei, H. Sakuraba and F. Masuoka., “New

three-dimensional memory array architecture for future ultrahigh-density,” IEEE Journal of Solid-State Circuits, vol.34, no.4, pp.476-483, 1999.

[24] F. Beeftink, Integration the VLSI Journal, vol.29, pp.67-93, 2000. [25] D. Heinbuch, “CMOS3 cell library” Addison-Wesley, 1987. [26] S. Watanabe et al., “A novel circuit technology with surrounding gate

transistors (SGTs) for ultra high density DRAMs”, IEEE J. Solid-State Circuits, vol.30, no.9, pp.960-95-1995.

Received: March 26, 2013

study of pattern area reduction with finfet and sgt for lsi … · layout pattern of inverter using...

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