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LIST OF FIGURESFig 1: Design Methodology.15 Fig 2: Block Diagram of a Simplified RF Receiver.17 Fig 3: The Configurations of Circuit Design...18 Fig 4: Distributed Amplifier19 Fig 5: Steps in Circuit Design..20 Fig 6: ID-VDS Curves (W=200 m)..22 Fig 7: ID-VGS Curves (W=200 m)..22 Fig 8: ID-VDS Curves (W=150 m)..23 Fig 9: ID-VGS Curves (W=150 m)..23 Fig 10: Final Schematic Design...25 Fig 11: Final Design Schematic with Real Components.....32 Fig 12: Two-Port Network.......33 Fig 13a: Input Voltage Reflection Coefficient (S11)...36 Fig 13b: Input Voltage Reflection Coefficient at input to each transmission line..36 Fig 14: Reverse Voltage Gain (S12)....37

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Fig 15: Forward Voltage Gain (S21)...37 Fig 16: Output Voltage Reflection Coefficient (S22)..38 Fig 17: Noise Figure38 Fig 18: Noise Figure Minimum..........39 Fig 19: Stability Plot...39 Fig 20: Rollet Stability Plot.40 Fig 21: Input Referred 1 DB Compression Point....40 Fig 22: Output Referred 1 DB Compression Point..41 Fig 23: Input Third Order Intercept Point (IIP3).41 Fig 24: Output Third Order Intercept Point (OIP3).42 Fig 25: Layout of Final Design44 Fig 26: Post Layout Checks.45 Fig 27: LVS Matched......46 Fig 28: Input Voltage Reflection Coefficient (S11) (PL)47 Fig 29: Reverse Voltage Gain (S12) (PL)48 Fig 30: Forward Voltage Gain (S21) (PL)...48 Fig 31: Output Voltage Reflection Coefficient (S22) (PL)..49 Fig 32: Noise Figure (PL)49

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Fig 33: Noise Figure Minimum (PL)...50 Fig 34: Stability Plot (PL)....50 Fig 35: Rollet Stability Plot (PL).51 Fig 36: Input Referred 1 DB Compression Point (PL)51 Fig 37: Output Referred 1 DB Compression Point (PL)..52 Fig 38: Input Third Order Intercept Point (IIP3) (PL).52 Fig 39: Output Third Order Intercept Point (OIP3) (PL).53

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LIST OF TABLESTable 1: Real Component Specification..26 Table 2: List of Real Components...29 Table 3: Post Layout Results...55 Table 4: Comparison Table of other works in distributed topology........56

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ACRONYMS1 dB-CP DRC DA EDA EMI LNA LVS IIP3 OIP3 PDKs PL SNR S-Parameters 1 dB compression point Design Rule Check Distributed Amplifier Electronic Design Automation Electromagnetic Interference Low Noise Amplifier Layout Versus Schematic Third order input intercept point Third order output intercept point Process Design Kits Post Layout Signal to Noise Ratio Scattering Parameters

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CONTENTSAbstract..1 Acknowledgement.2 List of Figures3 List of Tables.6 Acronym. 7 CHAPTER1: INTRODUCTION 1.1 Background11 1.2 Objective....13 1.3 Challenges..13 1.4 Limitations.13 1.5 Applications...13 1.6 Design Methodology..15 CHAPTER2: LNA DESIGN AND SCHEMATIC 2.1 LNA synopsis.16

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2.2 Circuit Design Configurations...18 2.2.1 Distributed Topology..19 2.3 Steps for Circuit Design...............20 2.3.1 Software Selection..20 2.3.2 Transistor Selection.21 2.3.3 Selection of Appropriate Bias Point....21 2.3.4 Topology Selection....................................24 2.3.5 Schematic Design25 CHAPTER 3: REAL CIRCUIT AND SIMULATIONS 3.1 Specifications of Real Components...26 3.2 List of Real Components29 3.3 Schematic with Real Components.............32 3.4 Simulations.32 3.4.1 S-Parameter Analysis..33 3.4.2 Power Sweep Analysis34 3.4.3 Stability Analysis35 3.5 Real Simulated Results..36

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CHAPTER 4: LAYOUT AND POST LAYOUT VERIFICATION 4.1 Layout Design43 4.2 Post Layout Checks and Simulations.45 4.2.1 Design Rule Check (DRC)..46 4.2.2 Layout versus Schematic (LVS).46 4.2.3 QRC47 4.3 Post Layout Simulations47 CHAPTER 5: SUMMARY 5.1 Summary of Work..54 5.2 Recommendations for Future Work...56 Bibliography...57

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CHAPTER 1INTRODUCTION1.1 BACKGROUND WHY ANALOG? The significance of analog designing can never be denied, however much technological advancement is brought about in the present century or later. This is because analog electronics is the interface between the real world signals and the electronic systems. For instance, the receiver chain of any digital radio receiver employs a pre-amplifier in its first stage called the low noise amplifier. [5] From biological applications to space exploration, an analog circuitry is required so that the real world analog signals may be interfaced with the digital computational equipment. [3]

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Analog circuit design, following a set of desired specifications is a complicated and a difficult task as compared to digital circuit design. Analytical expressions can be derived for determining the relationship between these parameters, which however vary from design to design and so, for accurate results simulators have to be used. Thus, numerous simulations have to be run to achieve a design close to desired parameters. [4] Thus, Analog IC design is challenging and interesting at the same time requiring state-ofthe art knowledge of the latest technologies. WHY LNA? A low noise amplifier is regarded as the first active building block of the receiver chain. it is an integral part of a receiver front-end that is indeed indispensable. Its major task is to enhance the input signal level while introducing as little noise to it as possible. There are a number of performance parameters that have to be achieved, thus making the LNA design appealing as well as demanding. WHY WIDEBAND? With the technological advancements, researchers are now aiming to develop wireless devices that incorporate numerous applications including phone, navigator, digital camera, video game console, web browser etc., in a single device which means that a single device will be used for communication over various standards, so various carrier frequencies may be acceptable to the LNA.[1][7] A few standards that we have aimed for include universal mobile telecommunication system (UMTS) for cellular systems, global system for mobile communication (GSM), IEEE802.11a/b/g/n and HiperLAN2 for LAN access, Bluetooth for short-range communication, and also GPS. [1]

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The integration of multiple standards may also be achieved by using tunable narrowband LNAs. However the solution being power and area inefficient renders it unsuitable for portable and cheaper wireless applications. Thus the best option is to opt for a single wideband LNA. [1] 1.2 OBJECTIVE The objective of our project was to design a Wide band low noise amplifier that would suffice for multiple standards. The design was supposed to fulfill the requirements of moderate gain, low noise figure, input and output matching, high linearity, low power dissipation, appropriate chip area and unconditional stability, to mention a few. 1.3 CHALLENGES

The LNA design presents a considerable challenge because of its simultaneous

requirement for all the above mentioned parameters. Each of these parameters is equally significant with the drawback of being interdependent on each other, which means improving one degrades the other. The design of a wideband amplifier is even more difficult, since suitable parameters

have to be achieved not only for a single frequency but for a range of frequencies. The topology used (distributed topology) is an area of research that has not

frequently been worked on. 1.4 LIMITATIONS This project is an area of study that is very time consuming. Thus, due to lack of time the design needs a little more work after post layout simulations for it to be ready for tape out. 1.5 APPLICATIONS

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The LNAs find applications in:

Cellular Communication Biomedical Engineering ( e.g. pacemakers, nanotechnology probes) Satellite Communication Military (e.g. unmanned aerial vehicles) Space Exploration (e.g. remote metering) Robotics Wireless data networks Instrumentation GPS receivers

...

And so on.

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1.6 DESIGN METHODOLOGY

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Fig 1: Design Methodology

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CHAPTER 2LNA DESIGN AND SCHEMATIC2.1 LNA SYNOPSIS An LNA is undoubtedly regarded as one of the principle components of the receiver chain in any communication system. It is the first active building block in the receiver front-end with the function of boosting the signal level of the received signal without introducing additional noise to it. [1] LNAs have innumerable applications for e.g. they are used in wireless data communication networks, satellites and cellular systems. In fact, an LNA is employed anywhere, wherever a signal is to be received and processed. [1] In wireless communication systems, when a signal travels a distance and reaches the destination, it is severely affected due to a number of different factors including interference, noise or EMI (Electromagnetic interference), dispersion along the path it travels, etc. As a result, the received signal is weak in strength, and contaminated with unwanted signals. Thus the original signal is largely changed. Therefore, to isolate the original signal, a low noise amplifier is employed with the dual task of amplifying the signal level without introducing further noise to it, within a certain

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frequency range which in turn increases the signal to noise ratio (SNR) and hence adjusts the quality of the received signal. [8] Communication systems consist of a transmitter and a receiver and the information is transmitted from the source to the destination. [9] The figure below shows a simplified structure of an RF receiver. LNA performs the first step of signal enhancement. Therefore, the sensitivity and noise parameters of the overall receiver are significantly affected by the performance of the LNA. [2]

Fig 2: Block diagram of a simplified RF receiver where FN is the noise factor of the Nth stage in the cascade and GN is the available power gain of the Nth stage. The importance of an LNA is mainly due to its effect on the overall noise figure of the receiver chain. According to Friiss formula, the overall noise figure of a cascade of stages is as follows:

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where FN is the noise factor of the Nth stage in the cascade, and GN is the available power gain of the Nth stage. [10] From the above formula, it is evident that the first stage is the most dominant one n defining the overall noise figure of the receivers front end. An LNA therefore, has mainly two requirements: Low noise figure, since LNAs noise is inserted directly into the received signal. High gain, the higher the gain, lesser will be the effect of the noise of the

subsequent stages on the received signal. [11] 2.2 CIRCUIT DESIGN CONFIGURATIONS

Fig 3: The Configurations of Circuit Design

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2.2.1 DISTRIBUTED TOPOLOGY

Fig 4: Distributed Amplifier The input signal is applied at the segment of the transmission line that is connected to the input of the first device. The input signal propagates along the input line, each stage responds resulting in the appearance of an amplified signal at the output (drain) of each stage. Collectively, the final output signal is the sum of the signals from each stage since the outputs are in a parallel connection. Thus, DA (Distributed Amplifier) gain is additive in nature. [13] WHY DISTRIBUTED? Design of the LNA is critical in a Wide Band receiver as it requires consideration of several parameters. The distributed amplifier avoids the usual gain bandwidth tradeoff since the transmission lines used, absorb the parasitic capacitances of the transistor (the parasitic capacitances determine the upper-cutoff frequency).

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Theoretically, it is assumed that its gain can be increased indefinitely by increasing the number of stages. However, there is a limitation to the number of stages that can be added due to the area constraints, the diminishing nature of the signal as it moves from one stage to the other through the transmission line and the resulting BW delay trade-off. Researchers are reluctant to use distributed topology in low-noise amplifier applications due to high power consumption and increased noise figure. Also designs involving distributed amplifiers occupy a significant chip area. However, nowadays low power versions of distributed LNA are also available in the market. Its large area problem can be overlooked since it provides high linearity, large bandwidth as well as suitable input and output matching. [14][15][16] 2.3 STEPS FOR CIRCUIT DESIGN

Fig 5: Steps in Circuit Design 2.3.1 SOFTWARE SELECTION We have chosen Cadence to be our design software. This licensed software is a very popular tool throughout the world used by renowned companies for analog as well as

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digital circuit design. Cadence allows designing in CMOS, SiGe and various other technologies, out of which our university has acquired the license for as latest as CMOS, 130nm technology. The university has also had to purchase PDKs (technology files from fabs) supplied by IBM and TSMC, that contain the data representing the IC manufacturing process, needed to be incorporated in the design. 2.3.2 TRANSISTOR SELECTION The transistor available for RF frequency in 130nm CMOS technology is nfet_rf which has been used in our design. It has an effective length of 120nm. 2.3.3 SELECTION OF APPROPRIATE BIAS POINT DC ANALYSIS In order to select a suitable bias point, the DC analysis was performed. Plots of VDS and ID were obtained along with VGS sweep for various values of transistor width which helped us obtain a suitable values of VDD and VG giving the desired VDS and ID. With the graphs we also determined the limiting values, such as the pinch-off and punch-through points. As our design evolved, the bias points of various transistors were slightly altered. Our final design has five transistors with widths 200m and a single transistor with width 150m.

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FOR W=200m

Fig 6: ID-VDS Curves

Fig 7: ID-VGS Curves

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FOR W=150m

Fig 8: ID-VDS Curves

Fig 9: ID-VGS Curves

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2.3.4 TOPOLOGY SELECTION We began our design with the simple and famous common source amplifier, moved onto replacing the design with various other topologies like common gate, common source degenerative. The results were not satisfactory for wide band after which we utilized the distributed topology (Section 2.3.1) The final design includes three staged distributed amplifier with cascode cells having inductive degeneration. CASCODE Better S11 and S22 (output is isolated from input)

Improved stability (reverse isolation) Improved noise performance and linearity (contributed by the CS and CG MOS

respectively CASCODE DEGENERATIVE reduced gain with improved linearity

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2.3.5 SCHEMATIC DESIGN

CASCODE -better S11 and S22 (output is isolated from input) -improved stability (reverse isolation) -improved noise performance and linearity (contributed by the CS and CG MOS respectively - improved gain as compared to CS

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Fig 10: Final Schematic Design

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CHAPTER 3REAL CIRCUIT AND SIMULATIONS3.1 SPECIFICATIONS OF REAL COMPONENTS The next step was the replacement of ideal components with real ones. This replacement was made with the consideration that the real components matched the ideal components as closely as possible. Mimcap

Capacitance is 2.05 fF/ m2 Aspect ratio: 1/3 W/L 3 The maximum area of any single

MIM is limited to 100,000 m2

The total MIM area on any chip may

be no more than 2 x 106 m2 Ground plane options:

The SUB option and NW option.

The Sub option is used when the capacitor is

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placed over p-well Regions The NW option is used when the

capacitor is placed over an nwell Dual mimcap Two-layer MIM Capacitor (dualmimcap)

The capacitance of the dual MIM

device is 4.10 fF/ m2 (in the region where both the HY and QY plates overlap). Ground plane options: The NW and SUB options both are

available. Ind (Planar Spiral) Inds ( Series Inductors)

High-Q Inductor Low Parasitic capacitance BFMOAT or M1 ground plane 0.21-21 nH (DM) 0.13-59 nH (OL) Higher inductance per unit area Inductance 0.5 to 92 nH Supported turns width 5 to 25 m Supported outer diameter 100 to 300

m Rf line

Turn-turn space 5 m

Properties:

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Kxres

100 m Length 1500 m 4 m Width 25 m Sheet Resistance 60 / m2 Sheet resistance tolerance 8 %

Table 1: Real Component Specification

3.2 LIST OF REAL COMPONENTS

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CAPACITORS

SYMBOL CMO CM2 CM4 CM5 CM6 CM7 CM8 CM24 INDUCTORS SYMBOL I0 I4 I5 I8 I11 I16 I17 I19 I20

CELL NAME dualmimcap mimcap mimcap dualmimcap mimcap mimcap mimcap mimcap

VALUE(F) 5.999793p 199.9267f 199.9267f 1.585263p 500.0706f 130.035f 4.999923p 100f

CELL NAME ind inds ind ind ind ind inds inds inds

VALUE(H) 511.00p 2.681n 412p 412p 412p 511p 1.984n 3.832n 672p

TRANSISTORS symbol cell name width of single WIDTH OF ALL

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finger(m) T0,T1,T2,T6,T10 T13 nfet_rf nfet_rf 20 15

FINGERS(m) 200 150

(NO OF FINGERS=10) TRANSMISSION LINES symbol TL3,TL4,TL5,TL12 TL7 TL8 TL9 cell name Rfline Rfline Rfline Rfline width (m) 4 10 10 5 LENGTH(m) 300 250 100.4 200

RESISTORS symbol R0 R1 R2 R6 cell name kxres_inh kxres_inh kxres_inh kxres_inh VALUE() 39.98 39.98 2.473K 900.9

Table 2: List of Real Components

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3.3 SCHEMATIC WITH REAL COMPONENTS

Fig 11: Final Design Schematic with Real Components

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Once the circuit is designed, it is immensely important for the system designers to authenticate their designs using simulating software. This is because the process of IC fabrication is time consuming and difficult, the designers have to be extremely sure of their circuit performance before the final IC is ready. 3.4 SIMULATIONS Cadence software offers a number of different simulations that help verification of various parameters of the design. A few of these are:

3.4.1 S-PARAMETER ANALYSIS S-parameters are widely used for the network operating at RF and microwave frequency. S parameters provide us the tool by which we can evaluate a two port network in terms of reflected (or scattered) and incident power.

Fig 12: Two-Port Network Port 1 is the input port and port 2 is the output port. Label a is indicating entering power waves and label b is indicating power waves leaving the port.

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S11=input port voltage reflection coefficient S11=b1/a1a2=0 S12=reverse voltage gain S12=b1/a2a1=0 S21=forward voltage gain S21=b2/a1a2=0 S22=output port voltage reflection coefficient S22=b2/a2a1=0 Each of these represents various properties of the system. S11 and S22 signify input and output matching; S21 shows the gain while the value of S12 has a significant effect on the stability of the design (a degraded value may cause the amplifier to oscillate). S-parameters vary with the frequency and the values of source and load impedance. Attached are graphs of s-parameters throughout the frequency band of operation. [1][8] 3.4.2 POWER SWEEP ANALYSIS PSS and QPSS analyses are used for determining the IP3 (third order intercept point) and 1 dB-CP (1 dB compression point); two very important measures of linearity. The higher the value, the more linear is the design. The linearity of a circuit actually determines the ability of an LNA of providing comparable responses to different values of the input signal. 1-DB COMPRESSION POINT 1 dB-CP is the input power at which the gain drops by 1 db.

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As the signal amplitude rises, the amplifier becomes saturated as a result of which harmonic components degrade the output signal. The point where these components become so dominant so as to reduce the output power such that the power gain reduces by 1 dB, is called the 1 dB-CP. This point indicates the maximum output power that can be obtained from an LNA when it is operating under linear conditions. 1-db CP is a direct measure of linearity in a sense that it does not need two tones as in IP3, it only needs one tone.

IP3 This is another measure of linearity. The third-order intercept point is a theoretical point where the amplitudes of the intermodulation tones at 21 2 and 22 1 are equal to the amplitudes of the fundamental tones at 1 and 2. This point defines the hypothetical power level of the output, when the non-linear behavior would be so dominant that the power level of the desired output signal would be comparable to the power level of the third- order components.[16][17] 3.4.3 STABILITY ANALYSIS STABILITY At higher frequencies of oscillations, most devices reach a certain level of unstability resulting in the oscillation. Unconditional stability is one of the essential conditions of an

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LNA, in that, it should never be driven into oscillation for any frequency or any combination of source/load impedance. The two measures defining stability are K and B1f (||).

For a device to be unconditionally stable, following conditions must be fulfilled K>1 and B1f