EZ-COURSEWARE State-of-the-Art Teaching Tools From AMS Teaching Tomorrow’s Technology Today

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EZ-COURSEWARE State-of-the-Art Teaching Tools From AMS Teaching Tomorrows Technology Today. 80486 and Pentium. 80486 Microprocessor Family. 80486 Microprocessor Introduced in 1989 High Integration On-chip 8K Code and Data cache Floating Point Unit Paged, Virtual Memory Management - PowerPoint PPT Presentation


<ul><li><p>EZ-COURSEWARE</p><p>State-of-the-Art Teaching ToolsFrom AMSTeaching Tomorrows Technology Today</p><p>www.advancedmsinc.com</p></li><li><p>www.advancedmsinc.com</p></li><li><p>80486 and Pentium</p><p>www.advancedmsinc.com</p></li><li><p>80486 Microprocessor Family80486 MicroprocessorIntroduced in 1989High IntegrationOn-chip 8K Code and Data cacheFloating Point UnitPaged, Virtual Memory Management168-pin PGA packageMultiprocessor SupportMultiprocessor InstructionsCache Consistency Protocols</p><p>www.advancedmsinc.com</p></li><li><p>Internal Architecture of the 80486Complex Reduced-Instruction-Set Computer (CRISC)RISC integer core</p><p>www.advancedmsinc.com</p></li><li><p>Real-Mode Software Model</p><p>the same as that shown for the 80386</p><p>www.advancedmsinc.com</p></li><li><p>Protected-Mode Software ArchitectureAC: Alignment-Check flag When this bit is set, an alignment check is performed during all memory accesses at privilege level 3. If an unaligned access takes place, exception 17 occurs.</p><p>www.advancedmsinc.com</p></li><li><p>Control RegistersAM : alignment mask -- If this is switched to 0, the alignment check is masked out.NE : Numeric ErrorCD : cache disableNW : not write-throughWP : write protect PCD : page-level cache disable PWT : page-level write transparent</p><p>www.advancedmsinc.com</p></li><li><p>System-Control Instruction Set+ a flush bus cycle+ a write-back bus cycle</p><p>www.advancedmsinc.com</p></li><li><p>Page Directory and Page Table Entries</p><p>www.advancedmsinc.com</p></li><li><p>Hardware Architecture of the 80486</p><p>www.advancedmsinc.com</p></li><li><p>Signal InterfacesPseudo-lock</p><p>www.advancedmsinc.com</p></li><li><p>On-Chip Cache of the 80486SX</p><p>www.advancedmsinc.com</p></li><li><p>Pentium ProcessorPentium Processor32-bit Microprocessor32-bit addressing64-bit Data BusSuperscalar architectureTwo pipelined integer unitsCapable of under one clock per instructionPipelined Floating Point UnitSeparate Code and Data Caches8K Code, 8K Write Back Data2-way 32-byte line sizeMESI cache consistency protocolAdvance Design FeaturesBranch Prediction237-pin PGA</p><p>www.advancedmsinc.com</p></li><li><p>Internal Architecture of the Pentium Processors</p><p>www.advancedmsinc.com</p></li><li><p>Pentium ProcessorPipeline and Instruction Flow5 stage pipelinePF : prefetchD1 : Instruction decodeD2 : Address GenerationEX : Execute -ALU and Cache AccessWB : Write Back</p><p>Intel 486Pentium </p><p>www.advancedmsinc.com</p></li><li><p>Pentium ProcessorU, V pipes - pairingU : any instructionV : simple instructions as defined in the Pairing rulesPF : instructions on chip cache or memory -&gt; prefetch buffers prefetch buffers - two independent pairs of line size(32 bytes)D1 : two parallel decodersD2 : address generation for operand fetch EX : ALU operations and data cache accessWB : modify processor state ; complete execution</p><p>www.advancedmsinc.com</p></li><li><p>Branch PredictionBranch PredictionBranch Target BufferThe processor accesses the BTB with the address of the instruction in the D1 stageexample)inner_loop : mov byte ptr flag[edx], al PF D1 D2 EX WB add edx, ecx PF D1 D2 EX WB cmp edx, FALSE PF D1 D2 EX WB jle inner_loop PF486 : 6 clocks Pentium : 2 clocks with branch prediction</p><p>www.advancedmsinc.com</p></li><li><p>EFLAGS</p><p>www.advancedmsinc.com</p></li><li><p>Control Registers of the Pentium Processor</p><p>www.advancedmsinc.com</p></li><li><p>Enhancements to the Instruction Set</p><p>www.advancedmsinc.com</p></li><li><p>Hardware Architecture</p><p>www.advancedmsinc.com</p></li><li><p>Memory Subsystem</p><p>www.advancedmsinc.com</p></li><li><p>Organization of the DRAM Array</p><p>www.advancedmsinc.com</p></li><li><p>RAS/CAS address MUX</p><p>www.advancedmsinc.com</p></li><li><p>Data Bus Transceiver Circuitry</p><p>www.advancedmsinc.com</p></li><li><p>On-Chip Cache</p><p>www.advancedmsinc.com</p></li><li><p>On-chip cache operating mode</p><p>www.advancedmsinc.com</p></li><li><p>www.advancedmsinc.com</p></li></ul>