EZ-COURSEWARE State-of-the-Art Teaching Tools From AMS Teaching Tomorrows Technology Today

Download EZ-COURSEWARE State-of-the-Art Teaching Tools From AMS Teaching Tomorrows Technology Today

Post on 05-Feb-2016

19 views

Category:

Documents

0 download

DESCRIPTION

EZ-COURSEWARE State-of-the-Art Teaching Tools From AMS Teaching Tomorrows Technology Today. 80486 and Pentium. 80486 Microprocessor Family. 80486 Microprocessor Introduced in 1989 High Integration On-chip 8K Code and Data cache Floating Point Unit Paged, Virtual Memory Management - PowerPoint PPT Presentation

TRANSCRIPT

  • EZ-COURSEWARE

    State-of-the-Art Teaching ToolsFrom AMSTeaching Tomorrows Technology Today

    www.advancedmsinc.com

  • www.advancedmsinc.com

  • 80486 and Pentium

    www.advancedmsinc.com

  • 80486 Microprocessor Family80486 MicroprocessorIntroduced in 1989High IntegrationOn-chip 8K Code and Data cacheFloating Point UnitPaged, Virtual Memory Management168-pin PGA packageMultiprocessor SupportMultiprocessor InstructionsCache Consistency Protocols

    www.advancedmsinc.com

  • Internal Architecture of the 80486Complex Reduced-Instruction-Set Computer (CRISC)RISC integer core

    www.advancedmsinc.com

  • Real-Mode Software Model

    the same as that shown for the 80386

    www.advancedmsinc.com

  • Protected-Mode Software ArchitectureAC: Alignment-Check flag When this bit is set, an alignment check is performed during all memory accesses at privilege level 3. If an unaligned access takes place, exception 17 occurs.

    www.advancedmsinc.com

  • Control RegistersAM : alignment mask -- If this is switched to 0, the alignment check is masked out.NE : Numeric ErrorCD : cache disableNW : not write-throughWP : write protect PCD : page-level cache disable PWT : page-level write transparent

    www.advancedmsinc.com

  • System-Control Instruction Set+ a flush bus cycle+ a write-back bus cycle

    www.advancedmsinc.com

  • Page Directory and Page Table Entries

    www.advancedmsinc.com

  • Hardware Architecture of the 80486

    www.advancedmsinc.com

  • Signal InterfacesPseudo-lock

    www.advancedmsinc.com

  • On-Chip Cache of the 80486SX

    www.advancedmsinc.com

  • Pentium ProcessorPentium Processor32-bit Microprocessor32-bit addressing64-bit Data BusSuperscalar architectureTwo pipelined integer unitsCapable of under one clock per instructionPipelined Floating Point UnitSeparate Code and Data Caches8K Code, 8K Write Back Data2-way 32-byte line sizeMESI cache consistency protocolAdvance Design FeaturesBranch Prediction237-pin PGA

    www.advancedmsinc.com

  • Internal Architecture of the Pentium Processors

    www.advancedmsinc.com

  • Pentium ProcessorPipeline and Instruction Flow5 stage pipelinePF : prefetchD1 : Instruction decodeD2 : Address GenerationEX : Execute -ALU and Cache AccessWB : Write Back

    Intel 486Pentium

    www.advancedmsinc.com

  • Pentium ProcessorU, V pipes - pairingU : any instructionV : simple instructions as defined in the Pairing rulesPF : instructions on chip cache or memory -> prefetch buffers prefetch buffers - two independent pairs of line size(32 bytes)D1 : two parallel decodersD2 : address generation for operand fetch EX : ALU operations and data cache accessWB : modify processor state ; complete execution

    www.advancedmsinc.com

  • Branch PredictionBranch PredictionBranch Target BufferThe processor accesses the BTB with the address of the instruction in the D1 stageexample)inner_loop : mov byte ptr flag[edx], al PF D1 D2 EX WB add edx, ecx PF D1 D2 EX WB cmp edx, FALSE PF D1 D2 EX WB jle inner_loop PF486 : 6 clocks Pentium : 2 clocks with branch prediction

    www.advancedmsinc.com

  • EFLAGS

    www.advancedmsinc.com

  • Control Registers of the Pentium Processor

    www.advancedmsinc.com

  • Enhancements to the Instruction Set

    www.advancedmsinc.com

  • Hardware Architecture

    www.advancedmsinc.com

  • Memory Subsystem

    www.advancedmsinc.com

  • Organization of the DRAM Array

    www.advancedmsinc.com

  • RAS/CAS address MUX

    www.advancedmsinc.com

  • Data Bus Transceiver Circuitry

    www.advancedmsinc.com

  • On-Chip Cache

    www.advancedmsinc.com

  • On-chip cache operating mode

    www.advancedmsinc.com

  • www.advancedmsinc.com

Recommended

View more >