EZ-COURSEWARE State-of-the-Art Teaching Tools From AMS Teaching Tomorrow’s Technology Today

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EZ-COURSEWARE State-of-the-Art Teaching Tools From AMS Teaching Tomorrows Technology Today. Cache Memory. Cache Memory. Large main memory system: High-capacity, relatively slow speed dynamic RAMs and EPROMs: 60ns or 70ns - PowerPoint PPT Presentation

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  • EZ-COURSEWARE

    State-of-the-Art Teaching ToolsFrom AMSTeaching Tomorrows Technology Today

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  • Cache Memory

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  • Cache MemoryLarge main memory system: High-capacity, relatively slow speed dynamic RAMs and EPROMs: 60ns or 70nsProcessor speed: requires DRAMs with 30 or 40ns, Latest processors : 10ns 20nsCache memory: small high-speed expensive static RAMsTypically from 16KB to 256KB, xMBHit Ratio and Miss Ratio

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  • Types of cache organizationTypes of cache organizationDirect-mapped cacheN-way set associative cachePosted Write

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  • 82385DX Cache Controller82385 Cache ControllerImproves 386 DX performanceReduce Average CPU wait states to nearly zeroZero wait state posted memory writesHit rates up to 99%SW transparentSynchronous Dual Bus Architecture Maps Full 386 DX address space (4GB)Flexible Cache Mapping PolicesDirect Mapped or 2-way Set AssociativeSupports Non-cacheable memory spaceUnified Cache for Code and Data132-pin PGA packageFig 4.44

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  • 82385DX Cache Controller

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  • Architecture of an 80386DX microcomputer with an 82385-based Cache MemoryArchitecture of an 80386DX microcomputer with an 82385-based Cache Memory386 local bus, 385 local bus, system bus

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  • Signal Interfaces of the 82385DX

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  • Signal Interfaces of the 82385DXConfiguration InputM/S (master/slave select):2W/D (two-way set associative or direct-mapped)385/386 Interface signalsCache Memory Control SignalsCALEN (cache address latch enable)CT/R (cache transmit/receive)CS0-CS3(cache chip select) : four 8K bytes SRAMsCOEA, COEB, CWEA, CWEB(cache output enable, cache write enable)82385 Local bus interface signalsBBE0-BBE3, BADS, BNA, BLOCK, BREADYBus Arbitration signals385 bus data transceiver and address latch control signals

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  • Connection to the 80386

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  • Direct-mapped Cache

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  • Two-way set associative cache

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  • Direct-Mapped Cache Organization

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  • Direct-Mapped Cache Organization386 DX Address Bus Bit Field

    4GB:8K double word(32kB) page X 217page: 1024 sets of 8 double words (8x32 bits)line: 32-bit Double word

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  • Direct-Mapped Cache OrganizationCache Directory Entry17-bit Tag: Tag valid bitLine valid bits

    17-bit tagDirect-mapped cache directory SET entry format

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  • Direct-Mapped Cache OperationRead Hit10-bit set address -- select one of 1024 entries17-bit tag field with the tagif Match and Tag and Line Valid bits are set --> hitdrives the cacheRead MissMem -> cache and 386DXLine miss - update the line valid bit onlyTag Miss - the upper address bits overwrite the previously stored tag the appropriate line valid bit is set, the other seven line valid bits are clearedWrite Hitupdate memory and cachedirectory is unaffected

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  • Direct-Mapped Cache OperationSnoop Hitcache: unaffectedthe affected line: invalidatedCache Flushclear all tag valid bitsWrite Misscache: unaffecteddirectory: unaffected

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  • Two-way Set Associative Cache Organization

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  • Two-way Set Associative Cache Organization 386 DX Address Bus Bit Field

    4GB:Two banks of 4K double word512 sets in each bankline: 32-bit Double wordLRU replacement AlgorithmLRU bitCache Directory Entry

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  • Two-way Set Associative Cache OperationRead HitThe two tags of this set are simultaneously compared with A14- A31Both tag valid bits are checkedAppropriate line valid bits are checkedUpdate LRU bit Read MissCheck LRU bitMem-> the bank that the LRU bit points toUpdate Tag, Tag valid bit, line valid bit

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  • Cache Coherency and Bus Watching

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