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CISC, RISC, and Post- RISC Computers CE 140 A1/A2 4 July 2003

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CISC, RISC, and Post-RISC Computers. CE 140 A1/A2 4 July 2003. Required Reading. RISC vs. CISC: the Post-RISC Era John “Hannibal” Stokes 99/risc-cisc/rvc-1.html. Review: Basic Performance Equation. T = (N x S) / R T – program execution time - PowerPoint PPT Presentation


  • CISC, RISC, and Post-RISC ComputersCE 140 A1/A24 July 2003

  • Required ReadingRISC vs. CISC: the Post-RISC EraJohn Hannibal Stokes 99/risc-cisc/rvc-1.html

  • Review: Basic Performance EquationT = (N x S) / RT program execution timeN number of instructionsS average steps per instructionR clock rate

  • Technological Conditions (Late 70s to Early 80s)Storage and memoryGenerally, expensive and slowCompilersLong compilation time, unoptimized outputVLSIlow transistor densities

  • SolutionStorage and memoryMore compact codeCompilersMake HLLASM translation simplerCode in assembly for optimized programVLSIReduce number of required transistors. How?

  • Software crisisHardware costs were fallingSoftware development costs were rising

  • SolutionShift complexity from software to hardwareBridge semantic gap between machine capabilities and high-level languages

  • Complex Instruction Set ComputerLate 1970s: experimentation with complex instructions made possible by interpreter (microprogrammed control)CISC generally required use of microprogrammed control

  • CISCIncreased use of complex, multistep instructionsLower N, higher SMade the addition of new features to old microprocessors easyExample: 8086 (1978) Pentium (1993) by Intel

  • CISCComplex instructions More stepsLarger and more expensive ICsSometimes lead to reduced performanceLess instructions per program less code

  • CISC Powerful instructions More direct implementation of high-level language operationsAllows more complex addressing modes

  • CISC IssuesLarger instruction set larger control stores larger microprogramsLarger microprograms slower and difficult to testSemantic gap Semantic clash

  • CISC Issues80/20 rule 80% of the instructions use only 20% of the instruction setNeed to maintain backward compatibility increased development cost

  • Reduced Instruction Set ComputerReduced Instruction Set ComputerMid-1970s John Cocke IBM 8011980: Patterson and Squin RISC processor SPARC1981: Hennessy MIPS processor

  • Technological ConditionsCheaper memoryBetter compilers

  • RISCMake the common case fastSpeed up 20% of instruction setSimpler instructionsSimpler addressing modesIncreased performanceHigher N, lower SComplexity is moved from hardware to software

  • RISCEven if a RISC machine takes four or five instructions to do what a CISC machine does in one instruction, if the RISC instructions are 10 times as fast, RISC wins

  • RISCWell-suited to pipelined execution, parallelismCan be used effectively by optimizing compilersHardwired control faster direct executionSimpler hardware Smaller chip area more space for registers and cache

  • RISC and CompilersCompilers play a more prominent roleNeed for intelligent, optimizing compilers

  • RISC Design PrinciplesAll instructions are directly executed by hardwareHardwired ControlMaximize the rate at which instructions are issuedInstructions should be easy to decodeRegular, fixed-length instructions

  • RISC Design PrinciplesOnly Loads and Stores should reference memoryProvide plenty of registers


  • Why arent RISC machines as popular as CISC machines?Not a totally valid questionBig investment in software for Intel-based machines (primarily CISC)CompatibilityIntel-based machines now have a RISC coreCommon instructions Faster Uncommon instructions Slower

  • CISC and RISCNow the term RISC refers to any computer with an ISA and CPU organization that is designed for high performanceSize of instruction set is now considered relatively unimportantFocus on fast instructions, not number of instructions

  • The Post-RISC EraCurrent Technological ConditionsCheap and fast memoryBetter compiler featuresIncreased transistor count

  • The Post-RISC EraPerformance improvementsSuperscalar executionBranch predictionHardware Out-of-order execution (OOO)SIMD and FP unitsAdditional fast, simple instructionsSoftware OOO

  • Post-RISC ProcessorsIntel Pentium 4AMD AthlonCISC instructions translated to RISC instructions (also in the Pentium 4)PowerPC G3 / G4 / G5Shows convergence of RISC and CISC with the same technologies being used

  • Post-RISC EraLine between CISC and RISC processors are blurredDifferent problems and technological conditions different solution, not strictly CISC or RISCEach computer must be evaluated not just on the basis of being CISC or RISC, but as a whole, including hardware and software