cisc & risc architecture

CISC & RISC Architecture

Suvendu Kumar DashM.Tech in ECE

VTP1492

History Of CISC & RISC Need Of CISC CISC

CISC Characteristics CISC Architecture

The Search for RISC RISC Characteristics

Bus Architecture Pipeline Architecture Compiler Structure Commercial Application Reference

Overview

1950s IBM instituted a research program. 1964 Release of System/360. Mid-1970s improved measurement tools demonstrated on

CISC. 1975 801 project initiated at IBM’s Watson Research Center. 1979 32-bit RISC microprocessor (801) developed led by

Joel Birnbaum. 1984 MIPS (Microprocessor without Interlocked Pipeline Stages)

developed at Stanford, as well as projects done at Berkeley. 1988 RISC processors had taken over high-end of the

workstation market.

History Of CISC & RISC

In the past, it was believed that hardware design was easier than compiler design Most programs were written in assembly language

Hardware concerns of the past: Limited and slower memory Few registers

Need Of CISC

As limited registers so …

Instructions have do more work, thereby minimizing the number of instructions called in a program.

Allow for variations of each instruction Usually variations in memory access.

The Solution

CISC, which stands for Complex Instruction Set Computer.

Each instruction executes multiple low level operations.

Ex. A single instruction can load from memory, perform an arithmetic operation, and store the result in memory.

Smaller program size.

CISC

A large number of instructions. Some instructions for special tasks used infrequently. A large variety of addressing modes (5 to 20). Variable length instruction formats.

Disadvantages :However, it soon became apparent that a complex instruction set has

a number of disadvantages:

These include a complex instruction decoding scheme, an increased size of the control unit, and increased logic delays.

CISC Characteristics

The essential goal of a CISC architecture is to attempt to provide a single machine instruction for each high level language instruction Ex: IBM/370 computers Intel Pentium processors

CISC Architecture

Compilers became more prevalent.

The majority of CISC instructions were rarely used.

Some complex instructions were slower than a group of simple instructions performing an equivalent task: Too many instructions for designers to optimize each one.

Smaller instructions allowed for constants to be stored in the unused bits of the instruction This would mean less memory calls to registers or memory.

The Search for RISC

RISC Stands for Reduced Instruction Set Computer.

It is a microprocessor that is designed to perform a smaller number of types of computer instruction so that it can operate at a higher speed.

RISC

Relatively few instructions 128 or less

Relatively few addressing modes. Memory access is limited to LOAD and STORE instructions. All operations done within the registers of the CPU.

This architectural feature simplifies the instruction set and encourages the optimization of register manipulation.

An essential RISC philosophy is to keep the most frequently accessed operands in registers and minimize register-memory operations.

RISC Characteristics

Fixed Length, easily decoded instruction format Typically 4 bytes in length

Single cycle instruction execution Done by overlapping the fetch, decode and execute phases of

two or three instructions known as Pipelining!!

Large number of registers in the processor unit. Use of overlapped Register Windows.

RISC Characteristics Cont..

Bus Interconnection of Processor units to memory and IO subsystem

BUS Architecture

Memory Bus: Memory bus (also called system bus since it interconnects the

subsystems) Interconnects the processor with the memory systems and also

connects the I/O bus. Three sets of signals –address bus, data bus and control bus

BUS Architecture Cont..

System Bus : A system’s bus characteristics --- according to the needs of the

processor, speed, and word length for instructions and data. Processor internal bus(es) characteristics differ from the system

external bus(es).


Buses to interconnect the processor Functional units to memory and IO subsystem


Address Bus Processor issues the address of the instruction byte or

word to the memory system through the address bus Processor execution unit, when required, issues the

address of the data (byte or word) to the memory system through the address bus.


Data Bus When the Processor issues the address of the instruction,

it gets back the instruction through the data bus When it issues the address of the data, it loads the data through the data bus.

When it issues the address of the data, it stores the data in the memory through the data bus.


Control Bus Issues signals to control the timing of various actions

during interconnection. Bus signals synchronize the subsystems


A technique used in advanced microprocessors where the microprocessor begins executing a second instruction before the first has been completed.

A Pipeline is a series of stages, where some work is done at each stage. The work is not finished until it has passed through all stages.

With pipelining, the computer architecture allows the next instructions to be fetched while the processor is performing arithmetic operations, holding them in a buffer close to the processor until each instruction operation can performed.

Pipeline Architecture

The pipeline is divided into segments and each segment can execute it operation concurrently with the other segments.

Once a segment completes an operations, it passes the result to the next segment in the pipeline and fetches the next operations from the preceding segment.


Instruction 1 Instruction 2

Instruction 3Instruction 4

X X

XX

Four sample instructions, executed linearly

CISC instructions do not fit pipelined architectures very well.

For pipelining to work effectively, each instruction needs to have similarities to other instructions, at least in terms of relative instruction complexity.


Instruction Pipelining Similar to the use of an assembly line in manufacturing plant.

New inputs are accepted at one end before previously accepted inputs appear as outputs at the other end.

Pipeline requires instruction to be divided into more stages.

So, that at every clock cycle, new instruction can be inserted for processing


Pipeline Architecture Cont..

Various instruction phases: Fetch Instruction(FI): fetch the next instruction Decode Instruction(DI): determine the opcode and operand Calculate Operands(CO):calculate the effective address of

source operands. Fetch Operands(FO):fetch each operand from memory. Execute Instructions(EI): perform the indicated operation and

store the result. Write result or Operand(WO): store the result into memory.


RISC Pipeline. Different from normal one.

Based on type of instruction.

According to instruction type, decide the number of phases in pipeline.

Number of stages in pipeline are not fixed.


RISC Pipeline. Most instructions are register to register

Two phases of execution I: Instruction fetch E: Execute

ALU operation with register input and output

For load and store Three phase execution I: Instruction fetch E: Execute

Calculate memory address D: Memory

Register to memory or memory to register operation


Effects of Pipelining(1)


Increase the Speedup Factor: I and E stages of two different instructions are performed

simultaneously. Which yields up to twice the execution rate of serial scheme.

Two problem prevents to achieve this the maximum speedup: Single port memory is used so only one memory access is possible

per stage. Branch instruction interrupts the sequential flow.


Four stage pipeline: E stage usually involves an ALU operation, it may be longer. So

we can divide into two stages:

E1: Register file read. E2: ALU operation and register write.


Optimization of RISC Pipelining: Delayed branch:

Does not take effect until after execution of following instruction. This following instruction is the delay slot.

Increased performance can be achieved by reordering the instructions!!!

This can be applicable for unconditional branches.


Normal and Delayed Branch:

Address Normal Branch

Delayed Branch

Optimized Delayed Branch

100 LOAD X, rA LOAD X, rA LOAD X, rA

101 ADD 1, rA ADD 1, rA JUMP 105

102 JUMP 105 JUMP 106 ADD 1, rA

103 ADD rA, rB NOOP ADD rA, rB

104 SUB rC, rB ADD rA, rB SUB rC, rB

105 STORE rA, Z SUB rC, rB STORE rA, Z

106 STORE rA, Z

Compiler Structure

A compiler is a Computer Program (or set of programs) that transforms Source Code written in a Programming Language (the source language) into another computer language (the target language, often having a binary form known as Object Code).

The most common reason for wanting to transform source code is to create an Executable program.

Compiler Structure

Compiler Structure Cont..

In a compiler, linear analysis

is called Lexical Analysis or Scanning and is performed by the Lexical Analyzer or Lexer,

hierarchical analysis is called Syntax Analysis or Parsing and is performed by

the Syntax Analyzer or Parser. During the analysis, the compiler manages a Symbol Table by

recording the identifiers of the source program collecting information (called Attributes) about them: storage

allocation, type, scope, and (for functions) signature.

When the identifier x is found by the lexical analyzer generates the token id enters the lexeme x in the symbol-table (if it is not already there) associates to the generated token a pointer to the symbol-table entry x.

This pointer is called the Lexical Value of the token. During the analysis or synthesis, the compiler may Detect Errors and

report on them. However, after detecting an error, the compilation should proceed

allowing further errors to be detected. The syntax and semantic phases usually handle a large fraction of the

errors detectable by the compiler.

Compiler Structure Cont..

RISC: First commercially available RISC processor was MIPS

R4000 Supports thirty-two 64-bit registers 128Kb of high speed cache

SPARC Based on Berkeley RISC model

PowerPC. Motorola. Nintendo Game Boy Advance (ARM7) Nintendo DS (ARM7, ARM9)

Commercial Applications

CISC: CISC instruction set architectures are

System/360 through z/Architecture, PDP-11, VAX, Motorola 68k, and Intel(R) 80x86.

Commercial Applications Cont..

Computer Organization And Architecture,8th Edition , William Stallings

http://nptel.ac.in/courses/Webcourse-contents/IIT-%20Guwahati/comp_org_arc/web/

http://www.borrett.id.au/computing/art-1991-06-02.htm

Reference







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cisc & risc architecture

Engineering

memory bus

system bus

bus signals

io bus

data bus whenit

data throughthe data

systems bus characteristics

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