cisc & risc architecture

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CISC & RISC Architecture Suvendu Kumar Dash M.Tech in ECE VTP1492

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CISC & RISC Architecture with contents History Of CISC & RISC Need Of CISC CISC CISC Characteristics CISC Architecture The Search for RISC RISC Characteristics Bus Architecture Pipeline Architecture Compiler Structure Commercial Application Reference

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  • 1. CISC & RISC ArchitectureSuvendu Kumar DashM.Tech in ECEVTP1492

2. History Of CISC & RISC Need Of CISC CISC CISC Characteristics CISC Architecture The Search for RISC RISC Characteristics Bus Architecture Pipeline Architecture Compiler Structure Commercial Application ReferenceOverview 3. History Of CISC & RISC 1950s IBM instituted a research program. 1964 Release of System/360. Mid-1970s improved measurement tools demonstrated onCISC. 1975 801 project initiated at IBMs Watson Research Center. 1979 32-bit RISC microprocessor (801) developed led byJoel Birnbaum. 1984 MIPS (Microprocessor without Interlocked Pipeline Stages)developed at Stanford, as well as projects done at Berkeley. 1988 RISC processors had taken over high-end of theworkstation market. 4. Need Of CISC In the past, it was believed that hardware design was easier thancompiler design Most programs were written in assembly language Hardware concerns of the past: Limited and slower memory Few registers 5. The Solution As limited registers so Instructions have do more work, thereby minimizing the number ofinstructions called in a program. Allow for variations of each instruction Usually variations in memory access. 6. CISC, which stands for Complex Instruction Set Computer. Each instruction executes multiple low level operations. Ex. A single instruction can load from memory, perform anarithmetic operation, and store the result in memory. Smaller program size.CISC 7. CISC Characteristics A large number of instructions. Some instructions for special tasks used infrequently. A large variety of addressing modes (5 to 20). Variable length instruction formats.Disadvantages :However, it soon became apparent that a complex instruction set hasa number of disadvantages: These include a complex instruction decoding scheme, anincreased size of the control unit, and increased logic delays. 8. CISC Architecture The essential goal of a CISC architecture is to attempt to provide asingle machine instruction for each high level language instruction Ex: IBM/370 computers Intel Pentium processors 9. The Search for RISC Compilers became more prevalent. The majority of CISC instructions were rarely used. Some complex instructions were slower than a group of simpleinstructions performing an equivalent task: Too many instructions for designers to optimize each one. Smaller instructions allowed for constants to be stored in the unused bitsof the instruction This would mean less memory calls to registers or memory. 10. RISC RISC Stands for Reduced Instruction Set Computer. It is a microprocessor that is designed to perform a smallernumber of types of computer instruction so that it can operateat a higher speed. 11. RISC Characteristics Relatively few instructions 128 or less Relatively few addressing modes. Memory access is limited to LOAD and STORE instructions. All operations done within the registers of the CPU. This architectural feature simplifies the instruction set and encouragesthe optimization of register manipulation. An essential RISC philosophy is to keep the most frequently accessedoperands in registers and minimize register-memory operations. 12. RISC Characteristics Cont.. Fixed Length, easily decoded instruction format Typically 4 bytes in length Single cycle instruction execution Done by overlapping the fetch, decode and execute phases oftwo or three instructions known as Pipelining!! Large number of registers in the processor unit. Use of overlapped Register Windows. 13. BUS Architecture Bus Interconnection of Processor units to memory and IOsubsystem 14. BUS Architecture Cont..Memory Bus: Memory bus (also called system bus since it interconnects thesubsystems) Interconnects the processor with the memory systems and alsoconnects the I/O bus. Three sets of signals address bus, data bus and control bus 15. BUS Architecture Cont..System Bus : A systems bus characteristics --- according to the needs of theprocessor, speed, and word length for instructions and data. Processor internal bus(es) characteristics differ from the systemexternal bus(es). 16. BUS Architecture Cont..Buses to interconnect the processor Functional units to memory andIO subsystem 17. BUS Architecture Cont..Address Bus Processor issues the address of the instruction byte orword to the memory system through the address bus Processor execution unit, when required, issues theaddress of the data (byte or word) to the memorysystem through the address bus. 18. Data BusBUS Architecture Cont.. When the Processor issues the address of the instruction,it gets back the instruction through the data bus Whenit issues the address of the data, it loads the data throughthe data bus. When it issues the address of the data, it stores the datain the memory through the data bus. 19. BUS Architecture Cont..Control Bus Issues signals to control the timing of various actionsduring interconnection. Bus signals synchronize the subsystems 20. Pipeline Architecture A technique used in advanced microprocessors where themicroprocessor begins executing a second instruction before the firsthas been completed. A Pipeline is a series of stages, where some work is done at each stage.The work is not finished until it has passed through all stages. With pipelining, the computer architecture allows the next instructionsto be fetched while the processor is performing arithmetic operations,holding them in a buffer close to the processor until each instructionoperation can performed. 21. Pipeline Architecture The pipeline is dividedinto segments andeach segment canexecute it operationconcurrently with theother segments. Once a segmentcompletes anoperations, it passesthe result to the nextsegment in thepipeline and fetchesthe next operationsfrom the precedingsegment.Instruction 1 Instruction 2X XInstruction 4 Instruction 3X XFour sample instructions, executed linearly 22. Pipeline Architecture CISC instructions do not fit pipelined architectures very well. For pipelining to work effectively, each instruction needs to havesimilarities to other instructions, at least in terms of relative instructioncomplexity. 23. Instruction Pipelining Similar to the use of an assembly line in manufacturing plant. New inputs are accepted at one end before previously acceptedinputs appear as outputs at the other end. Pipeline requires instruction to be divided into more stages. So, that at every clock cycle, new instruction can be inserted forprocessingPipeline Architecture 24. Pipeline Architecture 25. Pipeline Architecture Cont..Various instruction phases: Fetch Instruction(FI): fetch the next instruction Decode Instruction(DI): determine the opcode and operand Calculate Operands(CO):calculate the effective address ofsource operands. Fetch Operands(FO):fetch each operand from memory. Execute Instructions(EI): perform the indicated operation andstore the result. Write result or Operand(WO): store the result into memory. 26. Pipeline Architecture Cont..RISC Pipeline. Different from normal one. Based on type of instruction. According to instruction type, decide the number of phases inpipeline. Number of stages in pipeline are not fixed. 27. Pipeline Architecture Cont..RISC Pipeline. Most instructions are register to register Two phases of execution I: Instruction fetch E: Execute ALU operation with register input and output For load and store Three phase execution I: Instruction fetch E: Execute Calculate memory address D: Memory Register to memory or memory to register operation 28. Pipeline Architecture Cont..Effects of Pipelining(1) 29. Pipeline Architecture Cont..Effects of Pipelining(2) 30. Pipeline Architecture Cont..Increase the Speedup Factor: I and E stages of two different instructions are performedsimultaneously. Which yields up to twice the execution rate of serial scheme. Two problem prevents to achieve this the maximum speedup: Single port memory is used so only one memory access is possibleper stage. Branch instruction interrupts the sequential flow. 31. Pipeline Architecture Cont..Four stage pipeline: E stage usually involves an ALU operation, it may be longer. Sowe can divide into two stages: E1: Register file read. E2: ALU operation and register write. 32. Pipeline Architecture Cont..Effects of Pipelining(3) 33. Pipeline Architecture Cont..Optimization of RISC Pipelining: Delayed branch: Does not take effect until after execution of following instruction. This following instruction is the delay slot. Increased performance can be achieved by reordering theinstructions!!!This can be applicable for unconditional branches. 34. Pipeline Architecture Cont..Normal and Delayed Branch:Address NormalBranchDelayedBranchOptimizedDelayedBranch100 LOAD X, rA LOAD X, rA LOAD X, rA101 ADD 1, rA ADD 1, rA JUMP 105102 JUMP 105 JUMP 106 ADD 1, rA103 ADD rA, rB NOOP ADD rA, rB104 SUB rC, rB ADD rA, rB SUB rC, rB105 STORE rA, Z SUB rC, rB STORE rA, Z106 STORE rA, Z 35. Compiler Structure A compiler is a Computer Program (or set of programs) thattransforms Source Code written in a Programming Language (thesource language) into another computer language (the target language,often having a binary form known as Object Code). The most common reason for wanting to transform source code is tocreate an Executable program. 36. Compiler Structure 37. Compiler Structure Cont.. In a compiler, linear analysis is called Lexical Analysis or Scanning and is performed bythe Lexical Analyzer or Lexer, hierarchical analysis is called Syntax Analysis or Parsing and is performed bythe Syntax Analyzer or Parser. During the analysis, the compiler manages a Symbol Table by recording the identifiers of the source program collecting information (called Attributes) about them: storageallocation, type, scope, and (for functions) signature. 38. Compiler Structure Cont.. When the identifier x is found by the lexical analyzer generates the token id enters the lexeme x in the symbol-table (if it is not already there) associates to the generated token a pointer to the symbol-tableentry x. This pointer is called the Lexical Value of the token. During the analysis or synthesis, the compiler may Detect Errors andreport on them. However, after detecting an error, the compilation should proceedallowing further errors to be detected. The syntax and semantic phases usually handle a large fraction of theerrors detectable by the compiler. 39. Commercial ApplicationsRISC: First commercially available RISC processor was MIPS R4000 Supports thirty-two 64-bit registers 128Kb of high speed cache SPARC Based on Berkeley RISC model PowerPC. Motorola. Nintendo Game Boy Advance (ARM7) Nintendo DS (ARM7, ARM9) 40. Commercial Applications Cont..CISC: CISC instruction set architectures are System/360 through z/Architecture, PDP-11, VAX, Motorola 68k, and Intel(R) 80x86. 41. Reference Computer Organization And Architecture,8th Edition , William Stallings http://nptel.ac.in/courses/Webcourse-contents/IIT-%20Guwahati/comp_org_arc/web/ http://www.borrett.id.au/computing/art-1991-06-02.htm 42. Thank You