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RISC, CISC, and Assemblers Hakim Weatherspoon CS 3410, Spring 2013 Computer Science Cornell University &H Appendix B.1-2, and Chapters 2.8 and 2.12; als 2.16 and 2.17

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RISC, CISC, and Assemblers. Hakim Weatherspoon CS 3410, Spring 2013 Computer Science Cornell University. See P&H Appendix B .1-2, and Chapters 2.8 and 2.12; als 2.16 and 2.17 . Big Picture: Where are we now?. compute jump/branch targets. memory. register file. A. alu. D. D. B. - PowerPoint PPT Presentation

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RISC, CISC, and AssemblersHakim WeatherspoonCS 3410, Spring 2013Computer ScienceCornell UniversitySee P&H Appendix B.1-2, and Chapters 2.8 and 2.12; als 2.16 and 2.17 Big Picture: Where are we now?Write-BackMemoryInstructionFetchExecuteInstructionDecodeextendregisterfilecontrolalumemorydindoutaddrPCmemorynewpcinstIF/IDID/EXEX/MEMMEM/WBimmBActrlctrlctrlBDDMcomputejump/branchtargets+4forwardunitdetecthazard

Big Picture: Where are we going?3int x = 10;x = 2 * x + 15;Ccompileraddir5, r0, 10mulir5, r5, 2addir5, r5, 15MIPSassembly001000000000010100000000000010100000000000000101001010000100000000100000101001010000000000001111machinecodeassemblerCPU

Circuits

Gates

Transistors

Siliconop = addi r0 r5 10op = addi r5 r5 15op = r-type r5 r5 shamt=1 func=sllr0 = 0r5 = r0 + 10r5 = r5 j), BNE Rd, R0, Else// SUB Ri, Ri, Rj// if "GT" (greater than), i = i-j; J LoopElse:SUB Rj, Rj, Ri// or "LT" if (i < j)J Loop // if "LT" (less than), j = j-i;End:

ISA Variations: Conditional InstructionsIn MIPS, performance will be slow if code has a lot of branchesAt least one NOP (flush of pipeline) may follow a branch7while(i != j) { if (i > j) i -= j; else j -= i; }LOOP: CMP Ri, Rj // set condition "NE" if (i != j) // "GT" if (i > j), // or "LT" if (i < j) SUBGT Ri, Ri, Rj // if "GT" (greater than), i = i-j; SUBLE Rj, Rj, Ri // if "LE" (less than or equal), j = j-i; BNE loop// if "NE" (not equal), then loop

ISA Variations: Conditional Instructions=

0100=

0001=

1010=

0100In ARM, can avoid delay due to Branches with conditional instructionsIn ARM assembly, the loop avoids the branches around the then and else clauses. Note that if Ri and Rj are equal then neither of the SUB instructions will be executed, optimizing out the need for a conditional branch to implement the while check at the top of the loop, for example had SUBLE (less than or equal) been used.8ARM: Other Cool operationsShift one register (e.g. Rc) any amountAdd to another register (e.g. Rb)Store result in a different register (e.g. Ra)

ADD Ra, Rb, Rc LSL #4Ra = Rb + Rc