risc vs cisc

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Department of Electrical Engineering and Computer Science RISC vs. CISC Chetan Patil http://chetanpatil.info/ Few Slides Adapted From : Power Struggles: Revisiting the RISC vs. CISC Debate on Contemporary ARM and x86 Architectures (HPCA 2013)

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Learn how an architecture being a RISC or CISC affects and whether it's relevant or not.

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  • 1. Department of Electrical Engineering and Computer ScienceRISC vs. CISCChetan Patil http://chetanpatil.info/Few Slides Adapted From : Power Struggles: Revisiting the RISC vs. CISC Debate on Contemporary ARM and x86 Architectures (HPCA 2013)

2. Department of Electrical Engineering and Computer SciencePAPERS D. Bhandarkar and D. W. Clark. Performance from architecture: comparing a RISC and a CISC with similar hardware organization. In ASPLOS '91. [LINK] Power Struggles: Revisiting the RISC vs. CISC Debate on Contemporary ARM and x86 Architectures. In HPCA '13. [LINK] 3. Department of Electrical Engineering and Computer ScienceOVERVIEW What is RISC & CISC? Methods Evaluation & Key Findings Conclusion 4. Department of Electrical Engineering and Computer ScienceWhat is CISC & RISC? CISC Approach : MUL 2:3, 5:2RISC Approach : LOAD A, 2:3 LOAD B, 5:2 PROD A, B STORE 2:3, A 5. Department of Electrical Engineering and Computer Science1991 : METHOD 6. Department of Electrical Engineering and Computer ScienceMIPS M/200 vs VAX 8700 7. Department of Electrical Engineering and Computer ScienceSPECIFICATIONS 8. Department of Electrical Engineering and Computer Science1991 : EVALUATION & KEY FINDINGS 9. Department of Electrical Engineering and Computer ScienceMETHODOLOGYRESULTDISCUSSION 10. Department of Electrical Engineering and Computer ScienceResult: Instructions & CPI Instruction Ratio: Ratio of MIPS instruction extentions to VAX. RISC factor: Ratio of number of cycles per program on the VAX compared to MIPS 11. Department of Electrical Engineering and Computer ScienceResult: Operation Counts 12. Department of Electrical Engineering and Computer ScienceResult: Cache Behavior VAS cache results from hardware monitor. MIPS cache results from simulator. 13. Department of Electrical Engineering and Computer ScienceDiscussion: Architectural Factors Favoring MIPS: Operand specified decoding Number of registers. Floating-point hardware and instruction overlap. Simple jumps and braches. Fancy VAX instructions. Instruction scheduling. Translation buffers. Branch displacement size. Favoring VAX: Big I-Stream constants. Not-taken branches. 14. Department of Electrical Engineering and Computer Science1991 : CONCLUSION 15. Department of Electrical Engineering and Computer ScienceFrom architectural point of view: RISC as exmplified by MIPS offer a significant processor performance advantage over a VAX (CISC) of comparable hardware organization.Drawbacks: Compiler. Number of bechmarks. Application-level processor performance only. Not systems level. 16. Department of Electrical Engineering and Computer Science2013 : METHOD 17. Department of Electrical Engineering and Computer ScienceBeagleBoard ARM Cortex A8PandaBoard ARM Cortex A9Linux 2.6Intel Atom N450GCCIntel Sandy Bridge Core i717 18. Department of Electrical Engineering and Computer ScienceMobile CoreMark WebKitDesktopServerSPEC CPU2006Lighttpd CLucene Database kernels 18 19. Department of Electrical Engineering and Computer Science Performance measurement on real hardware Extensive use of performance counters Cycles, instructions, cache misses, branch misses Power measurements using Wattsup meters19 20. Department of Electrical Engineering and Computer Science 21. Department of Electrical Engineering and Computer Science 22. Department of Electrical Engineering and Computer Science2013 : EVALUATION & KEY FINDINGS 23. Department of Electrical Engineering and Computer ScienceMETHOD METHODOLOGY OLOGYPERFOR PERFORMANCE MANCEPOWER POWER & & ENERGY ENERGYTRADE TRADE OFF OFF 24. Department of Electrical Engineering and Computer SciencePerformance Analysis Flow: Present execution time for each benchmark. Normalize frequencys impact using cycle counts. To understand differences in cycle count and the influence of the ISA, present the dynamic instruction count measures, measured in both macro-ops and micro-ops. Use instruction mix, code binary size, and average dynamic instruction length to understand ISAs influence. To understand performance differences not attributable to ISA, look at detailed microarchitecture events. Attribute performance gaps to frequency, ISA, or ISAindependent microarchitecture features. Qualitatively reason about whether the ISA forces microarchitecture features. 25. Department of Electrical Engineering and Computer SciencePerformance Analysis: Key Finding 1 Execution Time Large performance gaps exist across the four platforms studied, as expected, since frequency ranges from 600 MHz to 3.4 GHz and microarchitectures are very different. 26. Department of Electrical Engineering and Computer SciencePerformance Analysis: Key Finding 2 Cycle-Count Performance gaps, when normalized to cycle counts, are less than 2:5 when comparing in-order cores to each other and out-of-order cores to each other. 27. Department of Electrical Engineering and Computer SciencePerformance Analysis: Key Finding 3 Instruction Count Instruction and cycle counts imply CPI is less on x86 implementations: geometric mean CPI is 3.4 for A8, 2.2 for A9, 2.1 for Atom, and 0.7 for i7 across all suites. x86 ISA overheads, if any, are overcome by microarchitecture. 28. Department of Electrical Engineering and Computer SciencePerformance Analysis: Key Finding 4 Instruction Format & Mix Combining the instruction-count and mixfindings, conclude that ISA effects are indistinguishable between x86 and ARM implementations. 29. Department of Electrical Engineering and Computer SciencePerformance Analysis: Key Finding 5 Microarchitecture 30. Department of Electrical Engineering and Computer SciencePerformance Analysis: Key Finding 5 Microarchitecture Contd.The microarchitecture has significant impact on performance. The ARM and x86 architectures have similar instruction counts. The highly accurate branch predictor and large caches, in particular, effectively allow x86 architectures to sustain high performance. x86 performance inefficiencies, if any, are not observed. The microarchitecture, not the ISA, is responsible for performance differences. 31. Department of Electrical Engineering and Computer SciencePerformance Analysis: Key Finding 6 ISA Influence on Microarchitecture Beyond the translation to microops, pipelined implementation of an x86 ISA introduces no additional overheads over an ARM ISA for these performance levels. 32. Department of Electrical Engineering and Computer SciencePower and Energy Analysis Flow: Present per benchmark raw power measurements. To factor out the impact of technology, present technologyindependent power by scaling all processors to 45nm and normalizing the frequency to 1 GHz. To understand the interplay between power and performance, examine raw energy. Qualitatively reason about the ISA influence on microarchitecture in terms of energy. 33. Department of Electrical Engineering and Computer SciencePower and Energy Analysis: Key Finding 7 Average Power Overall x86 implementations consume significantly more power than ARM implementations. 34. Department of Electrical Engineering and Computer SciencePower and Energy Analysis: Key Finding 8 Average Technology Independent Power The choice of power or performance optimized core designs impacts core power use more than ISA. 35. Department of Electrical Engineering and Computer SciencePower and Energy Analysis: Key Finding 9 Average Energy The choice of power or performance optimized core designs impacts core power use more than ISA. 36. Department of Electrical Engineering and Computer ScienceTrade-off Analysis Flow: Combining the performance and power measures, compare the processor implementations using Pareto-frontiers. Compare measured and synthetic processor implementations using Energy-Performance Pareto-frontiers. 37. Department of Electrical Engineering and Computer ScienceTrade-off Analysis: Key Finding 10 Power-Performance Trade-offs Regardless of ISA or energy-efficiency, high-performance processors require more power than lower performance processors. They follow well established cubic power/performance trade-offs. 38. Department of Electrical Engineering and Computer ScienceTrade-off Analysis: Key Finding 11 Energy-Performance Trade-offs It is the microarchitecture and design methodologies that really matter. 39. Department of Electrical Engineering and Computer Science2013: CONCLUSION 40. Department of Electrical Engineering and Computer ScienceISA being RISC or CISC does not matter for power and performance of modern processors. 41. Department of Electrical Engineering and Computer ScienceWhat is the ISAs role? Supporting specialization AVX crypto, Virtualization extensions Jazelle DBX, ARM Trustzone Exposing more workload-specific semantic information to the substrate Transactional Memory support Reliability-oriented extensions Many more 42. Department of Electrical Engineering and Computer ScienceQuestions? are guaranteed in life, answers aren't. 43. Department of Electrical Engineering and Computer ScienceThank You http://chetanpatil.info/talks.html