risc and cisc understanding the risc and cisc architectures

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RISC AND CISC UNDERSTANDING THE RISC AND CISC ARCHITECTURES http://cs.stanford.edu/people/eroberts/courses/soco/p rojects/risc/risccisc/

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  • Slide 1
  • RISC AND CISC UNDERSTANDING THE RISC AND CISC ARCHITECTURES http://cs.stanford.edu/people/eroberts/courses/soco/projects/risc/risccisc/
  • Slide 2
  • Definition Reduced instruction set computing, or RISC, is a CPU design strategy based on the insight that simplified instruction set (as opposed to a complex set) provides higher performance when combined with a microprocessor architecture capable of executing those instructions using fewer microprocessor cycles per instruction.[1] A computer based on this strategy is a reduced instruction set computer, also called RISC. The opposing architecture is called complex instruction set computing, i.e. CISC.
  • Slide 3
  • Microprocessor Architecture [See PowerPoint Architectures] Architecture of Central Processing Unit drives its working ability from the instruction set architecture upon which it is designed. Instruction Set Architecture can be defined as an interface to allow easy communication between the programmer and the hardware.
  • Slide 4
  • Processor design is the design engineering task of creating a microprocessor, a component of computer hardware. The design process involves choosing an instruction set and a certain execution paradigm (e.g. VLIW or RISC) and results in a microarchitecture described in e.g. VHDL or Verilog. This results in a die which is bonded a chip carrier. This chip carrier is then soldered onto a circuit board (PCB). CPU Design [See PowerPoint on CPU Design]
  • Slide 5
  • Addressing Modes: Addressing modes are the manner in the data is accessed. Depending upon the type of instruction applied, addressing modes are of various types such as direct mode where straight data is accessed or indirect mode where the location of the data is accessed. Addressing Modes
  • Slide 6
  • Instruction Set: It is a group of instructions that can be given to the computer. These instructions direct the computer in terms of data manipulation. A typical instruction consists of two parts: Opcode and Operand. Opcode or operational code is the instruction applied. It can be loading data, storing data etc. Oprand is the memory register or data upon which instruction is applied. Instruction Set [See PowerPoint Instruction Sets]
  • Slide 7
  • Apple vs Intel RISC OR CISC? By the end of this presentation see if you can a)Decide for yourself which architecture is superior and why b)Find out what Apple and Intel used What influenced their choices? c)What architecture would work best with smart phones and tablets?
  • Slide 8
  • RISC? RISC, or Reduced Instruction Set Computer. is a type of microprocessor architecture that utilizes a small, highly- optimized set of instructions, rather than a more specialized set of instructions often found in other types of architectures. The first RISC projects came from IBM, Stanford, and UC- Berkeley in the late 70s and early 80s. The IBM 801, Stanford MIPS, and Berkeley RISC 1 and 2 were all designed with a similar philosophy which has become known as RISC. Certain design features have been characteristic of most RISC processors: 1.one cycle execution time: RISC processors have a CPI (clock per instruction) of one cycle. This is due to the optimization of each instruction on the CPU and a technique called ; 2. 3.pipelining: a technique that allows for simultaneous execution of parts, or stages, of instructions to more efficiently process instructions; 4.large number of registers: the RISC design philosophy generally incorporates a larger number of registers to prevent in large amounts of interactions with memory Defining RISC Number of OPERATIONS recognised by Computer is Limited This reduces the no. of bits needed to store an instruction code Complex Instructions can be created using Combinations As operations recognised are limited, processing is initially slower..than the CISC architecture (which has more standard operations)
  • Slide 9
  • The Scenario Multiplying Two Numbers in Memory On the right is a diagram representing the storage scheme for a generic computer. The main memory is divided into locations numbered from (row) 1: (column) 1 to (row) 6: (column) 4. The execution unit is responsible for carrying out all computations. However, the execution unit can only operate on data that has been loaded into one of the six registers (A, B, C, D, E, or F). Let's say we want to find the product of two numbers - one stored in location 2:3 and another stored in location 5:2 - and then store the product back in the location 2:3. AD BE CF / x + - 1 2 3 4 1 2 3 4 5 6 Main Memory Registers Execution Unit x x y y z z
  • Slide 10
  • CISC Approach Part 1 of 2 The primary goal of CISC architecture is to complete a task in as few lines of assembly as possible. This is achieved by building processor hardware that is capable of understanding and executing a series of operations. For this task, a CISC processor would come with a specific instruction (we'll call it "MULT"). When executed, this instruction loads the two values into separate registers, multiplies the operands in the execution unit, and then stores the product in the appropriate register. Thus, the entire task of multiplying two numbers can be completed with one instruction: MULT 2:3, 5:2 AD BE CF / x + - 1 2 3 4 1 2 3 4 5 6 Main Memory Registers Execution Unit x x y y MULT 2:3, 5:2
  • Slide 11
  • CISC Approach Part 2 of 2 MULT is what is known as a "complex instruction." It operates directly on the computer's memory banks and does not require the programmer to explicitly call any loading or storing functions. It closely resembles a command in a higher level language. For instance, if we let "x" represent the value of 2:3 and "y" represent the value of 5:2, then this command is identical to the C statement "a = x * y." One of the primary advantages of this system is that the compiler has to do very little work to translate a high-level language statement into assembly. Because the length of the code is relatively short, very little RAM is required to store instructions. The emphasis is put on building complex instructions directly into the hardware. AD BE CF / x + - 1 2 3 4 1 2 3 4 5 6 Main Memory Registers Execution Unit
  • Slide 12
  • RISC Approach Part 1 of 4 RISC processors only use simple instructions that can be executed within one clock cycle. Thus, the "MULT" command described above could be divided into three separate commands: "LOAD," which moves data from the memory bank to a register, "PROD," which finds the product of two operands located within the registers, and "STORE," which moves data from a register to the memory banks. In order to perform the exact series of steps described in the CISC approach, a programmer would need to code four lines of assembly: LOAD A, 2:3 LOAD B, 5:2 PROD A, B STORE 2:3, AD BE CF / x + - 1 2 3 4 1 2 3 4 5 6 Main Memory Registers Execution Unit
  • Slide 13
  • RISC Approach Part 2 of 4 This may seem like a much less efficient way of completing the operation. Consider: 1)there are more lines of code, 2)more RAM is needed to store the assembly level instructions. 3)The compiler must also perform more work to convert a high-level language statement into code of this form. AD BE CF / x + - 1 2 3 4 1 2 3 4 5 6 Main Memory Registers Execution Unit
  • Slide 14
  • RISC Approach Part 3 of 4 However, the RISC strategy also brings some very important advantages. Because each instruction requires only one clock cycle to execute, the entire program will execute in approximately the same amount of time as the multi-cycle "MULT" command. These RISC "reduced instructions" require less transistors of hardware space than the complex instructions, leaving more room for general purpose registers. Because all of the instructions execute in a uniform amount of time (i.e. one clock), pipelining is possible. AD BE CF / x + - 1 2 3 4 1 2 3 4 5 6 Main Memory Registers Execution Unit
  • Slide 15
  • RISC Approach Part 3 of 4 Separating the "LOAD" and "STORE" instructions actually reduces the amount of work that the computer must perform. After a CISC-style "MULT" command is executed, the processor automatically erases the registers. If one of the operands needs to be used for another computation, the processor must re-load the data from the memory bank into a register. In RISC, the operand will remain in the register until another value is loaded in its place. AD BE CF / x + - 1 2 3 4 1 2 3 4 5 6 Main Memory Registers Execution Unit
  • Slide 16
  • CISCRISC Complex Instructions Emphasis on hardware Simpler Instructions broken down Emphasis on software Includes multi-clock complex instructions Single-clock, reduced instruction only Memory-to-memory: "LOAD" and "STORE" incorporated in instructions Register to register: "LOAD" and "STORE" are independent instructions Small code sizes, high cycles per second Low cycles per second, large code sizes Transistors used for storing complex instructions Spends more transistors on memory registers CISC VS RISC
  • Slide 17
  • The following equation is commonly used for expressing a computer's performance ability: The CISC approach attempts to minimize the number of instructions per program, sacrificing the number of cycles per instruction. RISC does the opposite, reducing the cycles per instruction at the cost of the number of instructions per program. The performance equation
  • Slide 18
  • ARM
  • Slide 19
  • What is ARM? ARM is a family of instruction set architectures for computer processors based on a reduced instruction set computing (RISC) architecture developed by British company ARM Holdings.
  • Slide 20
  • RISC OR CISC in ARM? A RISC-based computer design approach means ARM processors require significantly fewer transistors than typical CISC x86 processors in most personal computers. This approach reduces costs, heat and power use. Such reductions are desirable traits for light, portable, battery- powered devices including smartphones and tablet devices as well as embedded systems. A simpler design facilitates more efficient multi-core CPUs and higher core counts at lower cost, providing improved energy efficiency for servers c h p u
  • Slide 21
  • RISC does have huge advantages in processing, but it took a while before they gained respectability and a foothold in the commercial world. This was due to a lack of software support (to combine instructions to create complex ones) Windows 3.1 and Windows 95 were designed with CISC processors in mind. Many companies were unwilling to take a chance with the emerging RISC technology. Without commercial interest, processor developers were unable to manufacture RISC chips in large enough volumes to make their price competitive. Another major setback was the presence of Intel. Although their CISC chips were becoming increasingly unwieldy and difficult to develop, Intel had the resources to plow through development and produce powerful processors. Although RISC chips might surpass Intel's efforts in specific areas, the differences were not great enough to persuade buyers to change technologies. The story of RISC
  • Slide 22
  • Overall RISC Advantage? The Overall RISC Advantage Today, the Intel x86 is arguable the only chip which retains CISC architecture. This is primarily due to advancements in other areas of computer technology. The price of RAM has decreased dramatically. In 1977, 1MB of DRAM cost about $5,000. By 1994, the same amount of memory cost only $6 (when adjusted for inflation). Compiler technology has also become more sophisticated, so that the RISC use of RAM and emphasis on software has become ideal.
  • Slide 23
  • CISC and RISC Convergence State of the art processor technology has changed significantly since RISC chips were first introduced in the early '80s. Because a number of advancements (including the ones described on this page) are used by both RISC and CISC processors, the lines between the two architectures have begun to blur. In fact, the two architectures almost seem to have adopted the strategies of the other. Because processor speeds have increased, CISC chips are now able to execute more than one instruction within a single clock. This also allows CISC chips to make use of pipelining. With other technological improvements, it is now possible to fit many more transistors on a single chip. This gives RISC processors enough space to incorporate more complicated, CISC-like commands. RISC chips also make use of more complicated hardware, making use of extra function units for superscalar execution. All of these factors have led some groups to argue that we are now in a "post-RISC" era, in which the two styles have become so similar that distinguishing between them is no longer relevant. However, it should be noted that RISC chips still retain some important traits. RISC chips stricly utilize uniform, single-cycle instructions. They also retain the register-to-register, load/store architecture. And despite their extended instruction sets, RISC chips still have a large number of general purpose registers. *Additional Reading
  • Slide 24
  • Pipelining is often used by RISC architectures How do you think Pipelining benefits processing in relation to RISC architectures? All the instructions are dealt with separately by different parts of the processor so that instructions can be dealt with simultaneously
  • Slide 25
  • Slide 26
  • Recap on our knowledge of RISC AND CISC If you had something like 8 operations youd need more than 3 bits Or in other words: the more operations that the processor can recognise the more complex it is and the more bits are needed to store all the operation codes
  • Slide 27
  • Some processors are designed to have OPERATIONS and hence operation codes (for the things that they have to do) These are called CISC *Complex Set Instruction Computers
  • Slide 28
  • Some processors are designed to REDUCE the number of operations recognised, hence saving space on the representation of the operation codes. These are called RISC *Reduced Instruction Set Computers
  • Slide 29
  • RISC Machines Note: Just because they have fewer operations in their assembly language doesnt mean that they can do fewer things. It just means that missing instructions have to be made up from the ones that are there by clever programming.. Defining RISC Recap Number of OPERATIONS recognised by Computer is Limited This reduces the no. of bits needed to store an instruction code Complex Instructions can be created using Combinations As operations recognised are limited, processing is initially slower..than the CISC architecture (which has more standard operations)
  • Slide 30
  • Example of a Question and Mark Scheme Answer
  • Slide 31
  • What do you think? RISC OR CISC? a)Decide for yourself which architecture is superior and why b)Find out what Apple and Intel used What influenced their choices? c)What architecture would work best with smart phones and tablets?