# iki10230 pengantar organisasi komputer kuliah no. 4: cisc vs. risc instruction sets

of 41 /41
1 IKI10230 Pengantar Organisasi Komputer Kuliah no. 4: CISC vs. RISC Instruction Sets 12 Maret 2003 Bobby Nazief ([email protected]) Qonita Shahab ([email protected]) bahan kuliah: http://www.cs.ui.ac.id/kuliah/iki10230/ Sumber : 1. Hamacher. Computer Organization, ed-5. 2. Materi kuliah CS61C/2000 & CS152/1997, UCB.

Author: lexine

Post on 11-Jan-2016

18 views

Category:

## Documents

Embed Size (px)

DESCRIPTION

IKI10230 Pengantar Organisasi Komputer Kuliah no. 4: CISC vs. RISC Instruction Sets. Sumber : 1. Hamacher. Computer Organization , ed-5. 2. Materi kuliah CS61C/2000 & CS152/1997, UCB. 12 Maret 2003 Bobby Nazief ([email protected]) Qonita Shahab ([email protected]) - PowerPoint PPT Presentation

TRANSCRIPT

CS152: Computer Architecture and Engineering12 Maret 2003
Bobby Nazief ([email protected])
Qonita Shahab ([email protected])
bahan kuliah: http://www.cs.ui.ac.id/kuliah/iki10230/
2. Materi kuliah CS61C/2000 & CS152/1997, UCB.
*
shift left/right, rotate left/right
Input/Output Transfers
Register: Ri ; EA = Ri
Indirect-Register: (Ri) ; EA = [Ri]
Indirect-Memory: (LOC) ; EA = [LOC]
*
Add 10(R2),R1 ; R1 [R1] + [[R2]+10]
Base+Index: (R1,R2) ; EA = [R1] + [R2]
Add (R1,R2),R3 ; R3 [R3] + [[R1]+[R2]]
Base+Index+Offset: X(R1,R2) ; EA = [R1] + [R2] + X
Add 10(R1,R2),R3 ; R3 [R3] + [[R1]+[R2]+10]
Relative: X(PC) ; EA = [PC] + X
Beq 10 ; if (Z==1) then PC [PC]+10
Autoincrement: (Ri)+ ; EA = [Ri], Increment Ri
Add (R2)+,R1 ; R1 [R1] + [[R2]],
; R2 [R2] + d
Add -(R2),R1 ; R2 [R2] – d,
; R1 [R1] + [[R2]]
2.8 A x X + C x D pada single-accumulator processor
Multiply B ; Accumulator = A x B
Store X ; X can be A, B, or others except C or D
Add X ; Accumulator = A x B + C x D
*
Solusi PR #1
2.9 Jumlah nilai dari N siswa, J tes; J >> jumlah register
Move #SUM,R0 ; R0 points to SUM
Move J,R1 ; R1 = j
Lj:
Move J,R4
Sub R1,R4 ; R4: index to particular test of first student
Multiply #4,R4
Add R4,R3 ; R3 points to particular test of first student
Move N,R4 ; R4 = n
Ln:
Add R2,R3 ; R3 points to particular test of next student
Decrement R4
Move R5,(R0) ; Store the sum of particular test
Add #4,R0 ; R0 point to sum of the next test
Decrement R1
*
Clear R0 ; R0 accumulates the product.
LOOP:
Decrement R3 ; Decrement the counter.
Branch>0 LOOP ; Loop again if not done.
Store R0,DOTPROD ; Store the product in memory.
*
Store R5,30(R1,R2) ; EA = [R1] + [R2] + 30 = 5830
Add -(R2),R5 ; EA = [R2] – 1 = 4600 – 1 = 4599
Subtract (R1)+,R5 ; EA = [R1] = 1200
*
Term coined at Berkeley, ideas pioneered by IBM, Berkeley, Stanford
RISC characteristics:
Simple operations
RISC examples: MIPS, SPARC, IBM/Motorola PowerPC, Compaq Alpha, ARM, SH4, HP-PA, ...
CISC = Complex Instruction Set Computer
Term referred to non-RISC architectures
CISC characteristics:
Register-memory architecture
Variable-length instructions
Complex operations
*
32 x 32-bit FP regs (paired DP)
HI, LO, PC
Destination first: OPcode Rdest,Rsrc1,Rsrc2
LHU R1, 40(R3) Load halfword unsigned
LBU R1, 40(R3) Load byte unsigned
LUI R1, 40 Load Upper Immediate (16 bits shifted left by 16)
0000 … 0000
LUI R5
subtract unsigned subu \$1,\$2,\$3 \$1 = \$2 – \$3 3 operands
add imm. unsign. addiu \$1,\$2,100 \$1 = \$2 + 100 + constant
multiply mult \$2,\$3 Hi, Lo = \$2 x \$3 64-bit signed product
multiply unsigned multu\$2,\$3 Hi, Lo = \$2 x \$3 64-bit unsigned product
divide div \$2,\$3 Lo = \$2 ÷ \$3, Hi = \$2 mod \$3
divide unsigned divu \$2,\$3 Lo = \$2 ÷ \$3, Hi = \$2 mod \$3
*
xor xor \$1,\$2,\$3 \$1 = \$2 Å \$3 3 reg. operands
nor nor \$1,\$2,\$3 \$1 = ~(\$2 |\$3) 3 reg. operands
and immediate andi \$1,\$2,10 \$1 = \$2 & 10 Logical AND reg, constant
shift left logical sll \$1,\$2,10 \$1 = \$2 << 10 Shift left by constant
shift right logical srl \$1,\$2,10 \$1 = \$2 >> 10 Shift right by constant
shift right arithm. sra \$1,\$2,10 \$1 = \$2 >> 10 Shift right (sign extend)
shift left logical sllv \$1,\$2,\$3 \$1 = \$2 << \$3 Shift left by variable
shift right logical srlv \$1,\$2, \$3 \$1 = \$2 >> \$3 Shift right by variable
*
Compare and Branch
BEQ rs, rt, offset if R[rs] == R[rt] then PC-relative branch
BNE rs, rt, offset <>
BLEZ rs, offset if R[rs] <= 0 then PC-relative branch
BGTZ rs, offset >
BLT <
BGEZ >=
BLTZAL rs, offset if R[rs] < 0 then branch and link (into R 31)
BGEZAL >=
Instruction Example Meaning
set on less than slt \$1,\$2,\$3 if (\$2 < \$3) \$1=1; else \$1=0 Compare less than; 2’s comp.
set less than imm slti \$1,\$2,100 if (\$2 < 100) \$1=1; else \$1=0 Compare < constant; 2’s comp.
set less than uns. sltu \$1,\$2,\$3 if (\$2 < \$3) \$1=1; else \$1=0 Compare less than; natural numbers
set l. t. imm. uns. sltiu \$1,\$2,100 if (\$2 < 100) \$1=1; else \$1=0 Compare < constant; natural numbers
jump j 10000 go to 10000
For switch, procedure return
jump and link jal 10000 \$31 = PC + 4; go to 10000
For procedure call
*
LUI R1,high(AVEC) ; R1 points to vector A.
ORI R1,R1,low(AVEC)
ORI R2,R2,low(BVEC)
LUI R6,high(N)
AND R4,R4,R0 ; R4 accumulates the product.
LOOP: LW R5,0(R1) ; Compute the product of
LW R6,0(R2) ; next components.
ADDI R3,R3,-1 ; Decrement the counter.
BNE R3,R0,LOOP ; Loop again if not done.
LUI R6,high(DOTPROD) ; Store the product in memory.
SW low(DOTPROD)(R6),R4
8086: 16-bit, all internal registers 16 bits wide;
no general purpose registers; ‘78
8087: + 60 Fl. Pt. instructions, (Prof. Kahan)
adds 80-bit-wide stack, but no registers; ‘80
80286: adds elaborate protection model; ‘82
80386: 32-bit; converts 8 16-bit registers into
8 32-bit general purpose registers;
80486, Pentium, Pentium II: + 4 instructions
MMX: + 57 instructions for multimedia; ‘97
Pentium III: +70 instructions for multimedia; ‘99
Pentium 4: +144 instructions for multimedia; '00
*
Ukuran instruksi [n] bervariasi: 1 n 16 byte
0, 1, 2, 3, 4 1, 2 0,1 0,1 0, 1, 2, 3, 4 0, 1, 2, 3, 4
Prefix: (Lock, Repeat), Overrides: Segment, Operand Size, Address Size
MOV AL,BL ; byte (8 bit)
MOV AX,BX ; word (16 bit)
MOV EAX,EBX ; double-word (32 bit)
Prefix
Displacement
Immediate
SIB
Opcode
Mod
R/M
Register Indirect:
Index:
Base+disp.: MOV EAX,[EBP+10] ; EAX [EBP+10]
Index+disp.: MOV EAX,[ESI*4+10] ; EAX [ESI*4+10]
Base+Index: MOV EAX,[EBP+ESI*4] ; EAX [EBP+ESI*4]
*
XCHG Exchange
CMOVNE Conditional move if not equal
CMPXCHG Compare and exchange
*
*
JNE/JNZ Jump if not equal/Jump if not zero
JC Jump if carry
JCXZ/JECXZ Jump register CX zero/Jump register ECX zero
LOOP Loop with ECX counter
INT Software interrupt
*
INS/INSB Input string from port/Input byte string from port
OUTS/OUTSB Output string to port/Output byte string to port
CMPS/CMPSB Compare string/Compare byte string
SCAS/SCASB Scan string/Scan byte string
REP Repeat while ECX not zero
REPE/REPZ Repeat while equal/Repeat while zero
REPNE/REPNZ Repeat while not equal/Repeat while not zero
*
HLL Support:
ENTER High-level procedure entry; creates a stack frame
LEAVE High-level procedure exit; reverses the action of previous ENTER
Extended:
MMX Instructions
Operate on Packed (64 bits) Data simultaneously use 8 MMX Register Set
Floating-point Instructions
System Instruction
Streaming SIMD Extensions
*
LEA EBP,AVEC ; EBP points to vector A.
LEA EBX,BVEC ; EBX points to vector B.
MOV ECX,N ; ECX serves as a counter.
MOV EAX,0 ; EAX accumulates the product.
MOV EDI,0 ; EDI is an index register.
LOOPSTART: MOV EDX,[EBP+EDI*4] ; Compute the product of
IMUL EDX,[EBX+EDI*4] ; next components.
INC EDI ; Increment index.
LOOP LOOPSTART ; Loop again if not done.
MOV DOTPROD,EAX ; Store the product in memory.
*
*
Benefit: fewer instructions performance
Often true in C statements: c += b;
Benefit: smaller instructions smaller code
*
lw \$t0, 12(\$gp)
Benefit: simpler hardware easier to pipeline, higher performance
x86: “register-memory architecture”
All operations can have an operand in memory; other operand is a register; e.g.,
Benefit: fewer instructions smaller code
*
simple hardware performance
x86: “variable-length instructions”
small code size (30% smaller?)
More Recent Performance Benefit:
Instructions can include 8- or 32-bit immediates
*
LUI R1,high(AVEC)
ORI R1,R1,low(AVEC)
LUI R2,high(BVEC)
ORI R2,R2,low(BVEC)
LUI R6,high(N)
LW R3,low(N)(R6)
AND R4,R4,R0
IMUL EDX,[EBX+EDI*4]
INC EDI