1

LC-3 ArchitectureLC-3 Architecture

Patt and Patel Ch. 4Patt and Patel Ch. 4

2

CISC vs. RISCCISC vs. RISC

• CISC : Complex Instruction Set ComputerCISC : Complex Instruction Set ComputerLots of instructions of variable size, very Lots of instructions of variable size, very memory optimal, typically less registers.memory optimal, typically less registers.

• RISC : Reduced Instruction Set Computer RISC : Reduced Instruction Set Computer Less instructions, all of a fixed size, more Less instructions, all of a fixed size, more registers, optimized for speed. Usually registers, optimized for speed. Usually called a “Load/Store” architecture.called a “Load/Store” architecture.

3

What is “Modern”What is “Modern”

• For embedded applications and for For embedded applications and for workstations there exist a wide workstations there exist a wide variety of CISC and RISC and CISCy variety of CISC and RISC and CISCy RISC and RISCy CISC.RISC and RISCy CISC.

• Most current PCs use the best of Most current PCs use the best of both worlds to achieve optimal both worlds to achieve optimal performance.performance.

4

LC-3 ArchitectureLC-3 Architecture

• Very RISC, only 15 instructionsVery RISC, only 15 instructions

• 16-bit data and address16-bit data and address

• 8 general purpose registers (GPR)8 general purpose registers (GPR)

• Program Counter (PC)Program Counter (PC)

• Instruction Register (IR)Instruction Register (IR)

• Condition Code Register (CC)Condition Code Register (CC)

• Process Status Register (PSR)Process Status Register (PSR)

5

Instruction Fetch / Execute Instruction Fetch / Execute CycleCycle

In addition to input & output a program In addition to input & output a program also: also:

• Evaluates arithmetic & logical functions to Evaluates arithmetic & logical functions to determine values to assign to variable.determine values to assign to variable.

• Determines the order of execution of the Determines the order of execution of the statements in the program.statements in the program.

• In assembly this distinction is captured in the In assembly this distinction is captured in the notion of notion of arithmeticarithmetic, , logicallogical, and , and controlcontrol instructions.instructions.

6

Arithmetic and logical instructions evaluate variables and assign new values to variables.

Control instructions test or compare values of a variable and makes decisions about what instruction is to be executed next.

Program Counter (PC)Basically the address at which the current executing instruction exists.

Instruction Fetch / Execute Cycle

7

1. load rega, 102. load regb, 203. add regc, rega, regb4. beq regc, regd, 85. store regd, rege6. store regc, regd7. load regb, 158. load rega, 30

PC

Address

*Note: This is just pseudo assembly code

Instruction Fetch / Execute Cycle

8

The CPU begins the execution of an instruction by supplying the value of the PC to the memory & initiating a read operation (fetch).

The CPU “decodes” the instruction by identifying the opcode and the operands.

PC increments automatically unless a control instruction is used.

Instruction Fetch / Execute Cycle

9

Instruction Fetch / Execute Cycle

For example:For example:

PC PC ADD A, B, C ADD A, B, C

• CPU fetches instructionCPU fetches instruction

• Decodes it and sees it is an add operation, Decodes it and sees it is an add operation, needs to get values for the variables “B” & “C”needs to get values for the variables “B” & “C”

• Gets the variable “B” from a register or Gets the variable “B” from a register or memorymemory

• Does the same for variable “C”Does the same for variable “C”

• Does the “add” operation and stores the result Does the “add” operation and stores the result in location register for variable “A”in location register for variable “A”

10

Branch – like a goto instruction, next instruction to be fetched & executed is an instruction other than the next in memory.

ADD A, B, CBRn fredADD A, D, 3

fred ADD A, D, 4

If A is negative then next instruction to be executed is at fred, which is just an address

*Note: This is almost real LC-3 assembly

Instruction Fetch / Execute Cycle

11

Breaking down an Breaking down an instructioninstruction

ADD a, b, cADD a, b, c

a b cadd

Opcode

Destination register

Source registers/immediate

12

The Stored Program ComputerThe Stored Program Computer

1943: ENIAC1943: ENIAC

– Presper Eckert and John Mauchly -- first general electronic computer. (or was it John V. Atanasoff in 1939?)

– Hard-wired program -- settings of dials and switches.

1944: Beginnings of EDVAC1944: Beginnings of EDVAC

– among other improvements, includes program stored in memory

1945: John von Neumann1945: John von Neumann

– wrote a report on the stored program concept, known as the First Draft of a Report on EDVAC

13

First Draft of a Report on First Draft of a Report on EDVAC EDVAC

• The basic structure proposed in the draft The basic structure proposed in the draft became known as the “von Neumann became known as the “von Neumann machine” (or model). machine” (or model).

• This machine/model had five main This machine/model had five main components:components:– a memory, containing instructions and data– a processing unit, for performing arithmetic and

logical operations– a control unit, for interpreting instructions– and input and output to get data into and out of the

system.

14

Von Neumann Model*Von Neumann Model*M E M ORY

CON TR OL UN IT

M AR M D R

IR

P R OCE S S IN G UN IT

ALU TE M P

P C

OUTP UTM on ito rP rin terLE DD is k

IN P UTK eyboardM ous eS c anne rD is k

* A slightly modified version of Von Neumann’s original diagram

15

Locality of referenceLocality of reference

• We need techniques to reduce the instruction We need techniques to reduce the instruction size. From observation of programs we see that size. From observation of programs we see that a small and predictable set of variables tend to a small and predictable set of variables tend to be referenced much more often than other be referenced much more often than other variables.variables.

• Basically, locality is an indication that memory is Basically, locality is an indication that memory is not referenced randomly.not referenced randomly.

• This is where the use of registers comes into This is where the use of registers comes into play.play.

16

MemoryMemory

22kk x x mm array of stored bits: array of stored bits:

•AddressAddress

– unique (k-bit) identifier of location•ContentsContents

– m-bit value stored in location

Basic Operations:Basic Operations:

•LOADLOAD

– read a value from a memory location•STORESTORE

– write a value to a memory location

•••

0000000100100011010001010110

110111101111

00101101

10100010

address

contents

Von Neumann Model

17

Interface to MemoryInterface to MemoryHow does the processing unit get data to/from memory?How does the processing unit get data to/from memory?

MARMAR: Memory Address Register: Memory Address Register

MDRMDR: Memory Data Register: Memory Data Register

To To LOADLOAD a location (A): a location (A):

1. Write the address (A) into the MAR.2. Send a “read” signal to the memory.3. Read the data from MDR.

To To STORESTORE a value (X) to a location (A): a value (X) to a location (A):

1. Write the data (X) to the MDR.2. Write the address (A) into the MAR.3. Send a “write” signal to the memory.

M E M OR Y

M AR M D R

Von Neumann Model

18

Processing UnitProcessing UnitFunctional UnitsFunctional Units

– ALU = Arithmetic and Logic Unit– could have many functional units.

some of them special-purpose(multiply, square root, …)

– LC-3 performs ADD, AND, NOT

RegistersRegisters

– Small, temporary storage– Operands and results of functional units– LC-3 has eight registers (R0, …, R7), each 16 bits

wide

Word SizeWord Size

– number of bits normally processed by ALU in one instruction

– also width of registers– LC-3 is 16 bits

P R OCE S S IN G UN IT

ALU TE M P

Von Neumann Model

19

Input and OutputInput and OutputDevices for getting data into and Devices for getting data into and out of computer memoryout of computer memory

Each device has its own interface,Each device has its own interface,usually a set of registers like theusually a set of registers like thememory’s MAR and MDRmemory’s MAR and MDR

– LC-3 supports keyboard (input) and monitor (output)– keyboard: data register (KBDR) and status register (KBSR)– monitor: data register (DDR) and status register (DSR)

Some devices provide both input and outputSome devices provide both input and output

– disk, networkThe program that controls access to a device is usually called a The program that controls access to a device is usually called a driverdriver..

IN P UTK eybo ardM ouseS c annerD is k

OUTP UTM on ito rP rin terLE DD is k

Von Neumann Model

20

Control UnitControl UnitControls the execution of the programControls the execution of the program

Instruction RegisterInstruction Register (IR) (IR) contains the contains the current instructioncurrent instruction..

Program CounterProgram Counter (PC) contains the (PC) contains the addressaddress of the next instruction to of the next instruction to be executed.be executed.

Control unitControl unit::

– reads an instruction from memory • the instruction’s address is in the PC

– interprets the instruction, generating signals that tell the other components what to do

• an instruction may take many machine cycles to complete

CON TR OL UN IT

IRP C

Von Neumann Model

21

InstructionsInstructions

The instruction is the fundamental unit of work.The instruction is the fundamental unit of work.

Specifies two things:Specifies two things:

– opcode: operation to be performed– operands: data/locations to be used for operation

22

An instruction is encoded as a An instruction is encoded as a sequence of sequence of bitsbits. . (Like data)(Like data)

– Often, but not always, instructions have a fixed length, such as 16 or 32 bits.

– Control unit interprets instruction:generates sequence of control signals to carry out operation.

– Operation is either executed completely, or not at all.

A computer’s instructions and their formats is A computer’s instructions and their formats is known as its known as its Instruction Set ArchitectureInstruction Set Architecture (ISA)(ISA)..

Instructions

23

Ex: LC-3 ADD InstructionEx: LC-3 ADD InstructionLC-3 has 16-bit instructions.LC-3 has 16-bit instructions.

– Each instruction has a four-bit opcode, bits [15:12].

LC-3 has 8 LC-3 has 8 registersregisters (R0-R7) for temp. storage. (R0-R7) for temp. storage.

– Sources and destination of ADD are registers.

“Add the contents of R2 to the contents of R6, and store the result in R6.”

Instructions

24

Ex: LC-3 LDR InstructionEx: LC-3 LDR Instruction

Load instruction -- reads data from memoryLoad instruction -- reads data from memory

Base + offset mode:Base + offset mode:– add offset to base register - result is memory address– load from memory address into destination register

“Add the value 6 to the contents of R3 to form a memory address. Load the contents of that memory location to R2.”

Instructions

25

Instruction ProcessingInstruction Processing

Decode instructionDecode instruction

Evaluate addressEvaluate address

Fetch operands from memoryFetch operands from memory

Execute operationExecute operation

Store resultStore result

Fetch instruction from memoryFetch instruction from memory

26

FETCHFETCHLoad next instruction (at address stored in Load next instruction (at address stored in PC) from memory into Instruction Register PC) from memory into Instruction Register (IR).(IR).

– Copy contents of PC into MAR.– Send “read” signal to memory.– Copy contents of MDR into IR.

Then increment PC, so that it points to the Then increment PC, so that it points to the next instruction in sequence.next instruction in sequence.

– PC becomes PC+1.

EAEA

OPOP

EXEX

SS

FF

DD

Instruction Processing

27

DECODEDECODE

First identify the opcode.First identify the opcode.

– In LC-3, this is always the first four bits of instruction.

– A 4-to-16 decoder asserts a control line corresponding to the desired opcode.

Depending on opcode, identify other Depending on opcode, identify other operands from the remaining bits.operands from the remaining bits.

– Example:• for LDR, last six bits is offset• for ADD, last three bits is source

operand #2

EAEA

OPOP

EXEX

SS

FF

DD

Instruction Processing

28

EVALUATE ADDRESSEVALUATE ADDRESS

For instructions that require memory For instructions that require memory access, compute address used for access, compute address used for access.access.

Examples:Examples:

– add offset to base register (as in LDR)– add offset to PC– add offset to zero

EAEA

OPOP

EXEX

SS

FF

DD

Instruction Processing

29

FETCH OPERANDSFETCH OPERANDS

Obtain source operands needed to Obtain source operands needed to perform operation.perform operation.

Examples:Examples:

– load data from memory (LDR)– read data from register file (ADD)

EAEA

OPOP

EXEX

SS

FF

DD

Instruction Processing

30

EXECUTEEXECUTE

Perform the operation, using the Perform the operation, using the source operands.source operands.

Examples:Examples:

– send operands to ALU and assert ADD signal

– do nothing (e.g., for loads and stores)

EAEA

OPOP

EXEX

SS

FF

DD

Instruction Processing

31

STORE RESULTSTORE RESULT

Write results to destination.Write results to destination.(register or memory)(register or memory)

Examples:Examples:

– result of ADD is placed in destination register– result of memory load is placed in destination

register– for store instruction, data is stored to memory

• write address to MAR, data to MDR• assert WRITE signal to memory

EAEA

OPOP

EXEX

SS

FF

DD

Instruction Processing

32

Changing the Sequence of Changing the Sequence of InstructionsInstructions

In the FETCH phase, we increment the In the FETCH phase, we increment the Program Counter by 1.Program Counter by 1.

What if we don’t want to always execute the What if we don’t want to always execute the instruction that follows this one?instruction that follows this one?

– examples: loop, if-then, function call

33

We need special instructions that change the We need special instructions that change the contents of the PC.contents of the PC.

These are those These are those control instructionscontrol instructions from from before.before.

– jumps are unconditional – they always change the PC

– branches are conditional – they change the PC only if some condition is true (e.g., the result of an ADD is zero)

Changing the Sequence of Instructions

34

Ex: LC-3 JMP Ex: LC-3 JMP

Set the PC to the value contained in Set the PC to the value contained in a register. This becomes the a register. This becomes the address of the next instruction to address of the next instruction to fetch.fetch.

“Load the contents of R3 into the PC.”

Changing the Sequence of Instructions

35

Instruction Processing Instruction Processing SummarySummary

Instructions look just like data – it’s all Instructions look just like data – it’s all interpretation.interpretation.

Three basic kinds of instructions:Three basic kinds of instructions:

– computational instructions (ADD, AND, …)– data movement instructions (LD, ST, …)– control instructions (JMP, BRnz, …)

36

Six basic phases of instruction processing:Six basic phases of instruction processing:

F F D D EA EA OP OP EX EX S S

Instruction Processing Summary

• Not all phases are needed by every instruction

• Phases may take more than 1 machine cycle

37

Questions?Questions?

38