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SSCSSSCSSSCSSSCSIEEE SOLID-STATE CIRCUITS SOCIETY NEWSSummer 2007 Vol. 12, No. 3 www.ieee.org/sscs-news

The 40th Anniversary of Amdahl’s Law

sscs_NLsummer07 7/13/07 9:20 AM

Welcome tothe Sum-mer, 2007

Solid-State CircuitsSociety News!

We are delightedto receive feedbackfrom our readers.

Please refer to the Letters to the Edi-tor for comments on “The Origins ofthe Integrated Circuit” (Spring,2007). This Summer, 2007, issue isthe third of four that SSCS plans topublish annually (one each in Win-ter, Spring, Summer, and Fall).

The goal of each issue is to be a

self-contained resource with back-ground articles (that is, the ‘originalsources’) and current articles byexperts who describe the currentstate of affairs in technology and theimpact of the original papers and/orpatents.

For Summer, 2007 the theme is“The 40th Anniversary of Amdahl’sLaw,” and Dr. Amdahl has written aspecial Feature Article entitled “Com-puter Architecture and Amdahl’sLaw.” We are also reprinting a biog-raphy of Dr. Amdahl and excerptsfrom an interview that he gave inJanuary, 2007, to Dr. William S.

Anderson, retired Chairman ofNational Cash Register.

We also reprint Dr. Amdahl’s orig-inal article “Validity of the SingleProcessor Approach to AchievingLarge Scale Computing Capabilities”from the Spring Joint ComputerConference, 1967, pp. 483-485.

Thank you for taking the time toread the SSCS News. We appreci-ate all of your comments and feed-back! Please send comments [email protected].

LETTERS TO THE EDITORDr. Lanzerotti,

I want to compliment you on theoutstanding Spring 2007 issue ofthe SSCS news. The articles byThomas H. Lee and Riordan/Hod-deson are superb. I have alwaysbeen fascinated by the historybehind the technology I use in mydaily work and these two articlespulled all the facts together in ahighly readable format. Thanksagain and keep up the great work!

Sincerely,Bruce Tesch

Senior Member of Technical StaffMaxim Integrated Products

Dear Mary Lanzerotti,I wanted to write to say how much I

have enjoyed the recent issues of SSCSNews, and to applaud your work in pre-senting historical articles. If any of us atthe IEEE History Center can ever be ofhelp to you or your writers, please feel freeto contact me. We are always eager toassist any efforts by IEEE units to pro-mote electrical engineering history, andwe cheer your efforts.

With very best wishes,Robert

Robert D. ColburnResearch Coordinator

IEEE History Center, RutgersUniversity

39 Union StreetNew Brunswick, NJ 08901

+1 732 932 1066fax: +1 732 932 1193

http://www.ieee.org/web/abou-tus/history_center

2 IEEE SSCS NEWS Summer 2007

President:Richard C. JaegerAlabama Microelectronics CenterAuburn University, [email protected]: +1 334 844-1888

Vice President:Willy SansenK. U. LeuvenLeuven, Belgium

Secretary:David A. JohnsUniversity of TorontoToronto, Ontario, Canada

Treasurer:Rakesh KumarTechnology Connexions Poway, CA

Past President:Stephen H. LewisUniversity of CaliforniaDavis, CA

Other Representatives:Representative to Sensors Council

Darrin YoungRepresentative from CAS to SSCS

Domine LeenaertsRepresentative to CAS from SSCS

Un-Ku Moon

Newsletter Co-Editors:Mary Y. LanzerottiIBM T.J. Watson Research [email protected]: +1 914 945 1358

Lewis TermanIBM T. J. Watson Research Center [email protected]

Fax: +1 914 945-4160Elected AdCom Members at LargeTerms to 31 Dec. 07:

Bill BidermannDavid JohnsTerri FiezTakayasu SakuraiMehmet Soyuer

Terms to 31 Dec. 08:Wanda K. GassAli HajimiriPaul J. HurstAkira MatsuzawaIan Young

Terms to 31 Dec. 09:John J. CorcoranKevin KornegayHae-Seung (Harry) LeeThomas H. LeeJan Van der Spiegel

Region 8 Representative:Jan Sevenhans

Region 10 Representative:CK Wang

Chairs of Standing Committees:Awards David HodgesChapters Jan Van der SpiegelEducation CK Ken YangMeetings Bill BidermannMembership Bruce HechtNominations Stephen H. LewisPublications Bernhard Boser

For detailed contact information, see the Soci-ety e-News: www.ieee.org/portal/site/sscs

For questions regarding Society business, contact the SSCS Executive Office.

Contributions for the Fall 2007 issue of the Newsletter must be received by 8 August 2007 at the SSCS Executive Office. A complete media kit for advertisers isavailable at www.spectrum.ieee.org/mc_print. Scroll down to find SSCS.

Anne O’Neill, Executive Director IEEE SSCS445 Hoes LanePiscataway, NJ 08854Tel: +1 732 981 3400Fax: +1 732 981 3401Email: [email protected]

IEEE Solid-State Circuits Society AdCom

Editor’s Column

Katherine Olstein, SSCS Administrator IEEE SSCS445 Hoes Lane, Piscataway, NJ 08854 Tel: +1 732 981 3410 Fax: +1 732 981 3401Email: [email protected]


Summer 2007 IEEE SSCS NEWS 3

Photo courtesy of MattThomas. Dr. Gene

Amdahl and the WISC(Wisconsin Integrally Syn-chronized Computer), thesubject of his Ph.D. thesis

and the catalyst of hiscareer in design and

entrepreneurial activities.Summer 2007 Volume 12, Number 3

Editor’s Column . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2Letters to the Editor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2Corrections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21DVD Archive Notes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21Clarafication – Transitor Patent History . . . . . . . . . . . . . . . . . . . . . . . . .21

18

27

31

TECHNICAL LITERATUREComputer Architecture and Amdahl’s Law, Gene M. Amdahl . . . . . . . . . .4An Interview with Dr. Amdahl, William S. Anderson . . . . . . . . . . . . . . . . . . .10About Gene M. AmdahlValidity of the Single Processor Approach to Achieving Large Scale Computing Capabilities, Gene M. Amdahl (1967) . . . . . . . . . . . . . . . . . . . .19

PEOPLEDr. Gene Amdahl to Speak at ICCAD 2007, Patrick H. Madden . . . . . . . . . . . . . .22New Seniors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22Tools: ISSCC Paper Submissions - Increasing the Likelihood of Success, Jan Van der Spiegel and Kenneth Smith . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23

CHAPTER NEWSSSCS-Benelux and Leuven Student Branch Organize First Microelectronics Symposium, Jan Craninckx, Cedric Walravens . . . . . . . . . . . . . . . . . . . . . . . . . . .25SSCS Distinguished Lecturer Albert Wang Visits Central North Carolina . . . . . . .25Graduate Microelectronics Courses Initiated by SSCS-Italy . . . . . . . . . . . . . . . . .26SSCS-Santa Clara Valley: Did You Know That……?, Dan Oprica . . . . . . . . . . . . .26Razavi Kicks off DL Program in Vancouver, Resve Saleh . . . . . . . . . . . . . . . . . . . .27RFIT Sponsored by SSCS Singapore on 9 – 11 December 2007 . . . . . . . . . . . . .28

CONFERENCESISSCC 2007 Panel on the Ultimate Limits of Integrated Electronics, Sudhakar Pamarti . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29Europe’s Analog Design Experts Convene at 16th AACD Workshop in March, Jan Sevenhans and Jan Craninckx . . . . . . . . . . . . . . . . . . . . . . . . . . .30CICC in San Jose, 16-19 September . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3019th Hot Chips Conference to Meet on 19-21 August at Stanford University 31ESSCIRC on 11-13 September in Munich: The European Forum for Solid-State Circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .322007 IEEE Bipolar/BiCMOS Circuits and Technology (BCTM) in Boston on 30 September, Yih-Feng Chyan . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33IEEE Compound Semiconductor IC Symposium (CSICS) on 14-17 October in Portland . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34

NEWS4th IEEE International Symposium on Medical Devices and Biosensors . . . . . . . .28Eight Candidates Vie for Five SSCS AdCom Positions for 2008-2010 . . . . . . . . . .35News from the IEEE Council on Electronic Design Automation (CEDA) . . . . . . .37Timely JSSC Articles of Interest, Anne O’Neill . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39SSCS Members to Receive Nanotechnology Magazine, Bill Bidermann . . . . . .40TryEngineering.org Available in Seven Languages . . . . . . . . . . . . . . . . . . . . . . . .40Graduating Students Get a Discount on Dues . . . . . . . . . . . . . . . . . . . . . . . . . . . .40

CONFERENCE CALENDAR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .44


TECHNICAL LITERATURE


My educational backgroundhas never included anytraining in the field of

computing, so all of my designactivities have been based on myexperience and the necessity ofsolving current problems. Conse-quently, my computer architecturecontributions will largely be auto-biographical.

I was raised on a farm in easternSouth Dakota and attended a one-room grade school for all eightgrades. We didn’t have electricityuntil I was a freshman in highschool, so my technical experiencewas limited primarily to mechani-cal equipment. I enrolled in SouthDakota State College (SDSC) in thefall of 1941 in mechanical engi-neering, but decided it was not thefield for me. So I took a potpourriof courses in math, chemistry,electrical engineering and physics.World War II intervened early inmy freshman year, and I joined theNavy as an Electronic Technician,teaching electronics. Returning toSDSC in 1947, I selected physics asmy major, graduating in 1948.

I received a Wisconsin Alumni

Research Foundation assistantshipand began that summer in the fieldof Theoretical Physics at the Uni-

versity of Wisconsin in Madison.This was an unusual time inphysics, for they had just discov-ered “strange particles” in late1949, and the name “meson” hadnot yet been proposed. At thattime two other graduate studentsand I were assigned to determineif a force between nuclear particlesproposed by a Japanese physicistcould adequately describe the sim-plest 3-body nucleus, Tritium(Hydrogen 3). We worked for 30days using an 8-digit desk calcula-tor, and a slide rule to hold twomore most-significant digits. Wemapped the energy of the systemfor all relevant ranges of theparameters, but we couldn’t quiteachieve a stable state. We hadfound the proposed force to beinadequate, but I had found themeans of calculating to be evenmore inadequate! I then began tothink about how the computingcould be done better. The Univer-sity had no information on com-puters in its library, no courses incomputing and no computers, savefor an electronic analog computerin the Electrical EngineeringDepartment.

My major professor, Dr. RobertSachs, recognized my dilemmaand arranged for me to get a 2-month summer job in 1950 at theAberdeen Proving Grounds. Myassignment there was to program“super-sonic flow about a 3-dimen-sional body”. The instruction setwas that of the EDVAC, then underdevelopment. I wasn’t given anyintroduction to programming, or tothe structure of the computer. Idid not complete the programmingduring the 2 month period; I alsoheard that the development of theEDVAC was dropped because themercury delay line was unstabledue to temperature build-up whenoperating. I was not enamored ofthe EDVAC structure because theuse of fixed point with a limitedword length required a lot ofrescaling to maintain reasonableprecision. As I returned to Wiscon-sin I formulated a 3-address float-ing point structure, trying to make

it as simple as possible, and to usetechnologies that were commer-cially available. I chose a magnet-ic drum for main storage, with re-circulating registers to minimizethe use of electronics. For I/O Iplanned to use paper tape with ateletypewriter, which could bothpunch and read paper tape andprint as well.

I determined that I could usefloating point exclusively if I hada way to deal with the transfer ofword segments from one word toanother! The 3-address operationthat I came up with was Extract,which took “n” bits, beginning atbit “j” in word 1, was to be insert-ed, beginning at bit “k” in word 2,the result to be stored in location3. This eliminated the need forapproximately a dozen instruc-tions in fixed point! The completeinstruction set consisted of 10instructions – Add, Subtract, Mul-tiply, Divide, Compare (and trans-fer if the difference is zero ornegative), Transfer, Extract, Read-in, Read-out, and Halt. Read-inand Read-out were also very dif-ferent from any I/O operations Iobserved for several years follow-ing this, until I planned thedesign of my second computer atIBM in 1955, the IBM 709, when Iintroduced the I/O channel.Read-in and Read-out specifiedthe information source or sink,beginning at a specified point inthe source or sink and beginningat a specified location in the drumstorage and continuing until com-pleting the final specified loca-tion. The Read-in and Read-outinstructions were executed con-currently and independently ofcomputational operations. Thisoverlap of I/O with computingwas a major contributor to per-formance enhancement!

The magnetic drum had suffi-cient capacity to provide 32 tracksof storage, each containing 32words of 50 information bits and a5 bit-length space for track switch-ing time, for a total track length of1760 bit times. The 50 bit wordwas made up of 40 bits of numer-

Computer Architecture and Amdahl’s LawGene M. Amdahl

This is a picture of me in front of theentrance hall of the house I built so Icould finish my undergraduatedegree. I even had to make the frontdoor! The date of the photograph is1948.



TECHNICAL LITERATUREic fraction, 8 bits of exponent plus1 bit for exponent sign and 1 bitfor sign of the fraction. The arith-metic was performed on thenumeric fractions by re-circulatingthe fractions in re-circulating regis-ters while the exponents and signswere retained in electronic regis-ters for control purposes. The re-circulating registers had the readand write heads spaced 44 bitsapart, 40 bits for the fraction and 4bits for switching time. With thisspacing the fraction would have 40repetitions in a drum revolution,matching precisely the 1,760 bittimes in a drum revolution. Eachof the arithmetic operations wasperformed in the course of onedrum revolution. I thought I hadinvented a new way of performingdivision in one revolution, consid-ering the numerator fraction to bethe initial value of the remainder,subtracting the denominator frac-tion from the remainder andadding a 1 in the leftmost quotientdigit position, then shifting thedenominator fraction one bit posi-tion to the right, preparing for rep-etition. If at any stage of repetitionthe remainder became negative thedenominator fraction would beadded to that remainder instead ofsubtracted and a 1 would be sub-tracted in the corresponding quo-tient position rather than added. Ilater heard that Dr. John von Neu-man had patented it.

Each arithmetic operation andothers took one drum revolution tobe certain the instruction callingfor it to be acquired, then a secondrevolution to be certain theoperands were acquired, then arevolution to perform the opera-tion, and finally a revolution to becertain the result had been stored.Since the operations were non-conflicting, there were fourinstructions in the pipeline at alltimes, one picking up its instruc-tion, one picking up its operands,one performing its operation andone storing its result. Consequent-ly the computer performed onefloating point operation per drumrevolution. I believe there wereseveral world firsts in that design,the first electronic computer tohave floating point arithmetic (andcertainly the first to have only

floating point arithmetic), the firstelectronic computer to havepipelining, and the first electroniccomputer to have input and outputoperated concurrently and inde-pendently of computing!

I told one of my fellow physicsstudents about my computerdesign ideas, and he apparentlywas excited enough to pass theinformation on to the ElectricalEngineering Department, and inthe late fall of 1950 I was request-ed by them to give a lecture on mydesign ideas! I gave a seminar andabout a week later the head ofElectrical Engineering, Dr. Peter-son, called my major professor andasked him to change the subject ofmy doctoral thesis to be a recordof my computer design plan sothat their graduate engineers couldbuild it and be trained in this newfield! My major professor agreed,and I spent six months writing thenew thesis and ordering the mag-netic drum. I submitted my thesisin June, 1951, expecting to gradu-ate in June. But there was no oneat the University who felt compe-tent to properly evaluate it, so itwas sent to scientists at theAberdeen Proving Ground forevaluation. They approved, and Igraduated the following February.The thesis was titled “The LogicalDesign of an Intermediate SpeedDigital Computer”; I named thecomputer the WISC (WisconsinIntegrally Synchronized Comput-er). It was completed in 1955 andis now displayed in the ComputerHistory Museum in MountainView, California.

A copy of the thesis was appar-ently obtained by the IBM branchmanager in Milwaukee and sent toIBM at Poughkeepsie. NathanielRochester read it and had IBMmake me an offer to join them inPoughkeepsie. I accepted andjoined IBM in June 1952. My ini-tial assignment was to simulateneural networks on the IBM 701,according to the proposed charac-teristics in a monograph publishedby Professor Hebb. I worked on itfor several months and concludedthat the description was inade-quate. I then turned my attentionto character recognition and hadconsiderable success, even on the

crude characters of wire printing.The 701 had exhausted its marketafter the sale of 18 computers. Thecompany decided that a follow-oncomputer, the 704, should bedeveloped, utilizing the new mag-netic core memory rather than thecathode-ray tube memory in the701, for the capacity could bemuch larger. I was given the taskof designing it, for the other expe-rienced IBM designers were aboutto be committed to a joint devel-opment project with MIT to devel-op and produce the SAGE system.I decided to double the instructionsize in order to accommodate alarger address and additionalinstructions to provide floatingpoint arithmetic as well as thefixed point arithmetic of the 701. Ihad heard of an English computerhaving a “B-box”, a counter whichallowed the repetition of a loopuntil the count reduced to zero.Any address step-changing in anarray for each iteration stillrequired separate instructions. Ithought it would be more efficientif the count and the step-size couldbe combined, then the programcould be shorter and faster. I calledit indexing and put three indexregisters in the 704 to accommo-date different step sizes for differ-ent data arrays. I assigned two bitsin the instruction to identify noindexing and which of the threeindex registers to use in thisinstruction. I also discovered thatindex register contents could beavailable early enough to modifythe address in this instructionbefore fetching the data, thus hav-ing no additional execution time!It turned out that the Sage systemalso had an indexing capability,but I don’t know who had it first;they were a classified project, andI wasn’t cleared, so I had noknowledge of it to get the dates ofinvention.

When the time came to price the704 for the market, it was neces-sary to estimate the probable mar-ket size. Pricing people from IBMheadquarters came to talk to meand get my agreement on size.They initially estimated a market ofsix machines (I assume they con-sidered the 18 701 machines hadmostly satisfied the market). I was




incensed and insisted that themachine had so much more capa-bility than the 701 that it wouldhave a larger market size. Overthe next few weeks they cameback with 12, then 18 and finally32 before I agreed. The actualnumber sold was 140, making it anextremely profitable program!

I was then asked to design thefollow-on system, the 709, andshortly thereafter to design asupercomputer (called STRETCH)to utilize the new technology, tran-sistors. I was told it would be myproject, but that I would have toget a development contract, prefer-ably from the Livermore Labs orLos Alamos. This was late Novem-ber 1954. I consulted a bit withJohn Backus, and we agreed onthe principal characteristics theSTRETCH should possess. I stud-ied the capabilities of the pro-posed semiconductor technology,which was a new circuit typecalled ECL (Emitter CoupledLogic), sort of like the vacuumtube push-pull amplifiers. Theywere extremely fast circuits andvery power consuming. I didsome designing of a multiplier toestimate the probable performancethat could be achieved if efficient-ly instructed. I then worked on anew concept “look ahead” whichconsisted of fetching instructionswell in advance of their executiontime so that branch instructionscould be recognized early enoughto fetch an alternative instructionsequence with no delay. Thedesign analysis was very promis-ing, yielding several times the per-formance we could achieve usingvacuum tubes. Armed with my ini-tial design results I visited Liver-more first. They listened and werevery cordial, but they informed methat they had already committed tocontract with a competitor so theycouldn’t commit to us. I then vis-ited Los Alamos and presented tothem; they were very interestedand would negotiate with IBM. Ithen did some more fleshing out ofthe STRETCH design and alsodetermined what should be doneto the 704 to produce a 709. In the709 project I added a number ofreasonably useful new instructions,one of the most interesting ones

was a “history dependent tablelook-up”, which allowed codeconversions from BCD (BinaryCoded Decimal), IBM’s preferredcode, to ASCII, the newly adoptedAmerican Standard Code for Infor-mation Interchange, or vice versa.It also allowed two binary codeddecimal numbers (each decimaldigit occupying a 6-bit characterposition) to be added or subtract-ed in binary, then using the tablelook-up to convert the result to aproper binary coded decimalresult. These were two examples,but many more were ultimatelydeveloped by customers. Theprincipal change I wanted to makewas the introduction of an I/Ochannel, permitting the computerto specify the reading or writing ofa specified amount of data to orfrom a magnetic tape or drum intoor out of memory without thecomputer having to control thedata flow as it occurred, just as Idid in the WISC, but be able tocontinue computing with only theimpact of some memory cycledelays due to conflict of memoryrequests. This change was a sig-nificantly costly development sothat it required corporate approval.Elaine Boehm and I determinedthat we had to make an outstand-ing demonstration to win approval.We came up with the idea of atape sorting program. The IBM703 was a sorter-collator, a fairlymodestly priced machine sold tothe US Treasury. The expectedprice for the 709 we estimated tobe at least two or three times thatof the 703. We programmed thesort and found that it performed somuch faster than the 703 that thecost of sorting on the 709 was lessthan on the 703. This demonstra-tion tipped the balance and theI/O Channel development wasapproved! At this time (mid 1955)I was surprised to have a manassigned to my STRETCH project.I initially assumed he reported tome, but it became clear that hethought I reported to him. Thiswas very disconcerting, for I hadbeen assured that STRETCH wasmy project before I accepted theassignment and had then gottenLos Alamos to the negotiating tableand had achieved quite a bit of the

design. I wasn’t certain I had thesituation figured out for sure, so Icontinued on. This new man wasuninterested in my design and hadhis own approach. He wanted todesign a front end computer whichwould be a commercial computerwhich would then feed the backend which would be the scientificcomputer. To me this seemed tototally prevent any possibility ofresulting in the supercomputer thatI was commissioned to design!Late that year I was invited to meetwith the Laboratory manager; heshowed me his plan for restructur-ing the Laboratory. It was to be amatrix structure with several devel-opment projects feeding the tech-nology engineering groups. TheSTRETCH development was to bemanaged by the man assigned tome a few months earlier. I was tobe in charge of the STRETCHdetailed design. I was appalled, forI knew we could never agree, andthe project would fail. I didn’trespond about my reaction; I justwent back to my office and wrotemy letter of resignation. I didcontinue on until just beforeChristmas, providing my bestdesign ideas, all of which werelost, then left for South Dakota forChristmas with my and my wife’sfamilies, then on to Los Angeles tojoin Ramo-Wooldridge’s computerdivision.

Almost five years later Dr. Piore,IBM’s Chief Scientist who reporteddirectly to Tom Watson, came toLos Angeles and invited my wifeand me to have dinner atRomanoff’s restaurant in BeverlyHills. Dr. Piore’s wife was fromthe Romanoff family, so we hadremarkable attention! Dr. Pioreoffered me the position of manag-ing the Experimental Machinesdivision in IBM Research, with therequirement to be on the Eastcoast for a minimum of fourmonths and a maximum of sevenmonths. My wife and I acceptedand were back in New York Stateby November 1960. My first activ-ities were to look at the projects inmy division. I cancelled the onlytwo hardware design projectsbecause they had no chance ofbeing of value to IBM. One proj-ect was a computer design which



TECHNICAL LITERATUREhad been continually changed butnever complete enough to be eval-uated; the other was a governmentproject which utilized super con-ductor switches for logic, but therewas no way to amplify diminishingsignal levels. This left only soft-ware projects, which I retained,and the responsibility for design-ing a new supercomputer withinsignificant funding. I believe Iwas given this because theSTRETCH project had not met itsperformance target so its price hadbeen reduced and became a lossleader. The 704, 709, and the fol-low-on 7090 and 7094 had sus-tained IBM’s scientific computingmarket.

At this time IBM had theSPREAD committee in session.There were about five major com-puter families made by variousIBM divisions, each of which hadgenerations which weren’t quitecompatible. Unfortunately, thetotal development costs weregrowing impossibly large, for anynew device to be attachedrequired an engineering and soft-ware project to be manned andfunded for each member of eachfamily. So IBM’s developmentbudget was greater than most com-puter companies’ revenue! TheSPREAD committee’s goal was todefine data formats, kinds of I/Odevices, control, storage and logictechnologies which were to bestandardized, and to plan a newfamily of computers which wouldreplace all current families. Thiswas not only an enormous under-taking, but it was even more of apolitical undertaking, for it wouldrequire all of the divisions to yieldtheir fiefdoms to the king! Thiswas a major revolution beingfought, but the stakes were high,managing the costs to maintaincontrol of the world’s data pro-cessing market-place! I had onlybeen back east for a couple ofmonths when I was approachedby the president of the Data Sys-tems Division, Bob Evans. Heasked me to meet with him at abudgeting session to be held at asmall resort called Jug-End. I satthrough a session that amplydemonstrated the developmentbudgeting problem. After that ses-

sion Bob and I met privately, andhe asked me if I would considerdesigning the new family of com-puters. I asked him if the newfamily of computers would beupwardly compatible but notdownwardly compatible. He saidthat was the plan. I said I wouldnot be willing to do that, for itwould only end up with the samebudget problem I had justobserved, for the generationalproblem would exist immediately.I told him I thought the familycould be both upwardly anddownwardly compatible and withvirtually no cost impact, and if theywould enforce this constraint Iwould be willing to accept thechallenge. Bob thought for amoment, presuming I could possi-bly do it, and he agreed. So in1961 I was moving back to Pough-keepsie, where I worked for about10 hours a day defining data for-mats, the instruction set, and inseveral cases the hardware struc-ture, for each family member wasto have about a factor of three dif-ference in performance from itsneighboring members whichrequired registers in the smallermachines to be memory locations,but in larger machines to be in cir-cuitry. There were a total of 7machines in this System 360 fami-ly, covering a performance rangeof about 600 to 1. It is still IBM’smainframe line, though changedthrough the decades, and is IBM’slargest revenue product, and asdescribed in Halloween’s Palo AltoDaily News, it is superior to com-plexes of minicomputers or PC’s!

To meet the performance andcost constraints, the smallmachines had to use memory loca-tions as registers in appropriatecases, where the larger machinescould use hardware registers. Ialso discovered that there had tobe some portion of the architecturethat had to be reminiscent of eachof the two significant families thatwe were replacing, otherwise thedesigners from those familiescouldn’t develop the confidencethat the design would be accept-able in their market segment. Thisresulted in decimal operationsbeing memory to memory ratherthan in registers like the 1401 and

indexing very similar to the 7094.There were only two architecturaladvances of note in the full family;the most significant was “base reg-isters,” which allowed a muchsmaller address size required in theinstruction format to address aquite larger memory (I believe theinventor was Dr. Gerritt Blau), andthe other was making the address-ing of the disk storage and tapes tobe sufficiently alike so that theusers familiar with tapes couldexperiment with the new disk stor-age without having to use randomaccess exclusively (this was largelydue to 1401 I/O designers Ibelieve), in the fastest member, themodel 90’s there were three verypowerful ones, loop trapping,associated with look-ahead,planned by Dr. Tien Chi Chen andmyself, then virtual registers (regis-ters assigned when and whereneeded) and linked arithmeticunits, so results of one arithmeticunit could become an input toanother arithmetic unit withoutany intervening register storage;these were planned by the regulardesign team. The principal nega-tive consequence of the SPREADcommittee data format constraintsappeared in floating point, wherehaving to use binary sizes for theexponent size, eight bits, and forfraction shifting by multiples offour bits, for the rounding errorswere larger than I thought reason-able. I tried to get relief from theconstraint in this case, but wasrefused. It took about 20 yearsbefore IBM switched to IEEE float-ing point format. In the mid 1970s,the architectural concept inventedin England called “Virtual Memory”was introduced into the IBM Sys-tem 360, and with some months tolearn how to use it efficiently,became a very effective advance!Amdahl computers during thattime utilized IBM instruction setsthat could employ the IBM operat-ing system, which was almost uni-versal in the computing market-place. Consequently, Amdahlsdidn’t contain architecturaladvances which altered instructionresults, but did contain pipeliningas in the WISC and had muchmore advanced technology, suchas LSI (Large Scale Integration)




with air cooling, a world first(developed by Fred Buelow),rather than IBM’s MSI (MediumScale Integration) with water cool-ing. Amdahl also included anoth-er world first, remote diagnostics,called “Amdac,” invented by thefield engineers.

During this time, I had access totape storage programs and data his-tory for commercial, scientific, engi-neering and university computingcenters for the 704 through the7094. This gave insight on relativeusage of the various instructionsand a most interesting statistic --each of these computing centerwork load histories showed thatthere was 1 bit of I/O for eachinstruction executed! I also wasable to determine the speed of com-puting that could be maintained fora given memory size. This wasrelated to disk and tape speeds inthe environment of multi-process-ing. These latter two properties Idetermined in 1969, when I private-

ly estimated that System 360 wouldhave to change the address lengthto exceed about 15 MIPS (MillionInstructions Per Second). LivermoreLaboratory heard about the 1 bit ofI/O and thought it couldn’t be trueso they ran tests for a month andfound that during office hours,when users were using themachines from their consoles, thenumber of bits of I/O averaged 1.1,and at night doing batch processingit averaged 1.0. They were sur-prised, but neither they nor I knewwhy it should have that value.When virtual memory came intocommon usage, the number of bitsof I/O per instruction executedcame down. Although I had limiteddata, I could reasonably estimatethat it correlated quite closely withthe reduction of the percentage ofthe program size which hadn’tneeded to be brought in or retainedduring the course of its execution.

In 1967 I was asked by IBM togive a talk at the Spring Joint Com-

puter Conference to be held on theeast coast. The purpose was forme to compare the computingpotential of a super uniprocessorto that of a unique quasi-parallelcomputer, the Illiac IV, proposedby a Mr. Slotnik.

The proposed Illiac IV had a sin-gle Instruction unit (I-unit) driving16 arithmetic units (E-units). EachE-unit provided its own dataaddresses and determined whetheror not to participate in the execu-tion of the I-unit’s current instruc-tion, an interesting, but controver-sial proposal. The super uniproces-sor was a design type, not a specif-ic machine, so I had to estimate tothe best of my ability what perform-ance could reasonably be achievedby such a design. Figure 1 shows adiagram of the Illiac IV; Figure 2shows the performance of the IlliacIV on a problem having a varied,but reasonable, range of parallelismunder the control of an operatingsystem with characteristics similar tothose then currently in use, havingquite a bit of system managementand data movement code.

Figure 3 shows the performanceof the super uniprocessor on thatsame problem and operating sys-tem; Figure 4 shows the perform-ance of the Illiac IV with Slotnick’sexpected future goal of 256 E-unitsand running a problem having avaried range of parallelism, butreaching a level of parallelismmatching “America’s symbol ofpurity,” Ivory soap, 99.44%.

Figure 5 shows the formula Igenerated to estimate the Illiac IV’sperformance, giving it the benefitof assuming that if some paral-lelism existed all processors couldbe usefully employed.

These Figures are not quite thesame as in the 1967 presentation, forthey weren’t published, nor did Ikeep them, for I had no expectationof the intensity of their afterlife! Inever called this formula “Amdahl’sLaw” nor did I hear it called that forseveral years; I merely considered itan upper limit performance for a

Dr. Amdahl holding a 100gate LSI air-cooled chip. On his desk is a circuit boardwith the chips on it. This circuit board was for an Amdahl 470 V/6 (photographdated March 1973).

Photograph of the Amdahl 470 V/6.

Figure 1. A diagram of the Illiac IV.




computer with ONE I-unit and N E-units running problems under thecontrol of that time period’s operatingsystem! The debate between me andMr. Slotnick was joined by many inthe audience, and it became quiteheated. I felt Mr. Slotnick was tryingto egg me into attacking him ratherthan his computer design, but I care-fully avoided that, only to be attackedby Dr. Herbert Grosch in the audi-ence for not attacking him. It becamea bit of a circus, and I was quiteunhappy about being involved, for Ithought of it as a rational analysis oftwo competing design approaches,not a bashing of another human foroffering a controversial designapproach! Several years later I wasinformed of a proof that Amdahl’sLaw was invalidated by someone atLos Alamos, where a number of com-puters interconnected as an N-cubeby communication lines, but with

each computer also connected to I/Odevices for loading the operating sys-tem, initial data, and results. Thismade all control and data movementto be carried out in parallel. I didn’tenter the fray; I merely commentedthat what they called Amdahl’s Lawmerely described the Illiac IV, whichhad only one I-unit. I also heard thatAmdahl’s Law was used to challengethe multi-computer systems devel-oped by Massively Parallel, a Col-orado firm, where their chief systemdesigner looked at the formula andthough it appeared to have the formof an information theoretical state-ment and used it to further enhancehis system! As a result Massively Par-allel invited me to join their advisoryboard! I really still do not considerAmdahl’s Law to be as much of a lawas the relationships of memory size

and computer performance and alsothe number of bits of I/O per instruc-tion executed or as reduced, whenconsidered as a function of the frac-tion of program required to be in “vir-tual memory”. These seem to be lostin the mist of time! I also consider theWISC to be the most remarkablearchitectural achievement I’ve made,and with no input from any sourceother than sheer inventiveness.

There has been no publicityabout the capability of the actualIlliac IV. I did hear unofficially thatit was unable to be successfullydebugged at the University of Illi-nois and that it was shipped to theNASA facility here in Sunnyvalewhere debugging was being car-ried out by volunteers. I heard afew months later that they had got-ten it to work and had executed atest program, but that no informa-tion on its performance had beenmade available. I’m not certainthat this information was entirelyaccurate so I cannot vouch for it.

Figure 2. Illiac IV Performance

Figure 3. Super Uniprocessor Perfor-mance.

Figure 4. Performance of the Illiac IVwith Slotnick’s expected future goal of256 E-units.

Figure 5.

The formula generated to estimate theIlliac IV’s performance. The numera-tor in the formula is Ps x (S+P), andthe dominator is S+P/16. In this for-mula, S is the % of the problem thatmust be executed sequentially (orserially), and P is the % of the prob-lem which may be executed in paral-lel if the computer has this capability.The sum (S+P) is always equal to100%, or 1, for it is the workload to beperformed. Ps is the performance ofa computer which can only executethe problem in a totally sequentialmanner, regardless of the problempossessing the capability for parallelexecution, and which has the speedof the Illiac IV’s I-unit. The denomi-nator reflects the capability of the Illi-ac IV to be able to execute the P com-ponent 16 each instruction executiontime (this is giving an advantage tothe Illiac IV, for only in vector ormatrix operations where the sizes aremultiples of 16 would it perform thatwell). The ratio (S+P)/(S+P/16) repre-sents the speed-up of the Illiac IVarchitectural feature for parallelism.This speed-up times Ps is the opti-mistic performance of the Illiac IV.By the way, no one challenged thisformula, just my range of only up to50% parallel was thought by some tobe a bit low.

From: Naintre, PaulSent: Friday, March 30, 2007 11:29 AMSubject: ArrivederciHi Folks,The day has arrived after 27 yearswith Amdahl, when it's my turn tosay goodbye.

It was a pleasure working withsuch great people as yourselves.

I always likened Gene Amdahlto Enzo Ferrari: both builders ofpowerful, gleaming, machines.

Enzo's machines were measuredin horse power, max rpms, enginesize and number of Formula 1 wins.

Gene Amdahl's machines weremeasured in MIPs, max transactionsper second, no. of CPU engines andnumber of customer wins.

Two completely different indus-tries, both built from passion, courageand a desire to produce the world’smost powerful, revered, machines.

We certainly made the best prod-ucts in the world and I was veryproud to have the opportunity towork here with such great people.

I wish you all Good Luck and allthe very best for the future.

Paul.p.s. If you would like to stay in

touch my new email id is:[email protected].




William S. Anderson, whointerviewed Dr. Amdahlin January, 2007 in Palo

Alto, CA, is the retired Chairman ofthe National Cash Register Compa-ny. He was primarily interested inhow a start-up company could suc-cessfully compete with IBM whengiant companies like General Elec-tric and RCA were unable to do so,even after investing on the order offive billion dollars in their ventures.

(Q) What was your background,including education?(A) I was born on Nov. 16, 1922, ineastern South Dakota, and raisedon a farm. I attended a one-roomcountry school for my first eightgrades, then a small high school ofabout 150 students, graduating in1940 (we got electricity when I wasa freshman). I spent one year athome, doing farm work, beforeentering South Dakota State College(now a University). My father hadwanted me to attend a liberal-artscollege, for he didn’t want me to goto college to learn how to make aliving, but rather how to get themost out of life! My interests werein engineering at the time, so there-fore my choice. Since this was thefall of 1941, Pearl Harbor wasbombed early in my freshman year.I continued in college for the nextyear and a half, working as a janitorin the hospital for room and boardand helping with farm work duringthe summer. I wasn’t drafted due tosuch a shortage in farm labor. Iwas requested to teach Physics Lab-oratory that fall at SDSC, becausethey had more than one hundredsoldiers coming in for the ArmySpecialized Training Program andnot enough people who couldteach them. This was more satisfy-ing in terms of contributing to thewar effort. During that time I tookthe Navy’s Eddy Test, qualifying forand entering Naval electronicstraining, and teaching after that.When I was discharged in June of1946 I immediately married myfiancée, Marian Quissell, who grewup on a farm four miles from myhome. This marriage was a major

catalyst in my life, giving it stability,purpose and satisfaction! We havenow been married over 60 years.We’ve raised three children, Carl,Delaine, and Andrea. I considermy family the crowning glory of mylife! After getting married I decidedto return to SDSU. There was nohousing available in Brookings so Idecided to build a small house insections and erect it on an emptylot. Unfortunately there were no fit-tings for connecting to municipalwater, though I explored all sourceswithin two hundred miles! I finallydecided to approach McComb’scabin court on the edge of the city.Mr. McComb agreed to let me erectmy house there and connect to hiswater and power. He was a mostgracious and fair landlord. When Iwas due to graduate in June 1948, Iapplied to several graduate schoolsto study Theoretical Physics. I wasaccepted at the University of Wis-consin at Madison. At the Universi-ty of Wisconsin I received a Wis-consin Alumni Research Founda-tion assistantship plus the last of myGI bill. I completed my courses,took my final exams, including myorals, and submitted my thesis.Near graduation time in February1952 our first child, Carl, was born.

(Q) How did you get into comput-ers so early?(A) While studying for my doctor-ate, two other graduate studentsand I were assigned the task ofdetermining whether or not a pro-posed intra-nuclear force coulddescribe the three-body nucleus,Tritium (Hydrogen 3). We workedfor a month using a desk calculatorand a slide rule to map the energyof this nucleus, but there was nostable state. I felt there ought tobe a better way to do these com-putations, so I began inventing acomputer, which I defined in thefall of 1950. The head of ElectricalEngineering, Dr. Peterson, heard ofmy plans and invited me to give alecture on my design. After hear-ing it he requested my major pro-fessor, Dr. Sachs, to change mythesis subject from physics to the

recording of my computer design,so that graduate engineers couldbuild it and be trained in this newfield. I was then given a researchassociate position on the engineer-ing staff to start the project andwrite my thesis on the WISC (Wis-consin Integrally SynchronizedComputer). This set of eventschanged my future from physics tocomputer design and entrepre-neurial activities. The WISC is ondisplay at the Computer HistoryMuseum in Mountain View (CA).

(Q) What was your first computerdesign work at IBM?(A) IBM’s first scientific computer,the 701, had been sold to 18 cus-tomers and its market apparentlysaturated, so the decision to make afollow-on product was made. I wasgiven the assignment of designingit. It was to be called the 704. The701 had only fixed point and arather small memory. I elected touse the new larger magnetic corememory, and to introduce floating-point arithmetic. I designed indexregisters, which specified howmuch the addresses would changein each iteration, and installed threein such a way that the indexingtook no additional time.

(Q) Did you do any more designwork there?(A) The initial market success wasso positive that I was immediatelygiven the task of designing the fol-low-up machine, the 709, as well asthe task of designing a super-com-puter to be called STRETCH, for thetechnology was to be the new semi-conductor transistors. I was also totry to get an atomic energy lab tocontract for it. I quickly defined thechanges to the 704 to make it intothe 709; the biggest change was theinvention of the I/O channel, whichallowed the I/O to go on independ-ently and concurrently with com-puting, just as I had done in theWISC. The STRETCH projectrequired that I first learn the capa-bilities of the transistor technology,then to improve the speed by look-ing ahead in the program for branch

An Interview with Gene M. AmdahlWilliam S. Anderson, National Cash Register Company



TECHNICAL LITERATUREinstructions to prepare for anybranch required. This look-aheadtechnique and technology producedexcellent results, so, armed withthis, I approached Livermore Lab,only to learn they had just commit-ted to a development with a com-petitor. I then visited Los AlamosLab and got them interested enoughto commit.

(Q) After you left IBM in Decem-ber, 1955, what did you do atRamo-Woolridge?(A) At Ramo-Woolridge I wasimmediately put to work determin-ing how to solve military require-ments. Upon writing up a proposalI was sent to Washington that nighton the “Red-Eye.” After shaving andchanging my shirt in the Washing-ton air terminal I visited three dif-ferent military groups who eachhad new needs to meet, [and] thenoff to catch the late flight back toLA and to bed by midnight. Thenext morning I was back at workdetermining how to solve theseneeds. When we got some of thecontracts I expected I would havethe chance to do some of the devel-opment, but management liked theway I produced my solutions sothey considered me to be their “util-ity outfielder,” whereas I consideredmyself to be “out in left field”.

(Q) Why and where did you gofrom there?(A) I then began to seriously listento my college and grad schoolfriend, Dr. Harold Hall, who was ina new start-up company calledAeronutronics, and which had justbeen acquired by the Ford MotorCompany. This company appearedto have adequate capital and high-ly respected scientists in nuclearphysics, rocket technology, andelectronics. They also had quite agood stock option plan! I decidedto pursue it.

(Q) What did you do at Aeronu-tronics?(A) My initial work at Aeronutronicswas quite similar to that at Ramo-Woolridge, but here I had theopportunity to do a much morestructured solution. A significantone was the design of a flight dataentry machine, which allowed a

pilot to type into blanks on a cath-ode ray tube screen, then press abutton and have the plan automati-cally telegraphed to the FAA center;we called it FLIDEN. We won thecontract, but again I didn’t initiallyget the development project. Fairlyshortly thereafter the companymoved from the San Fernando Val-ley to Newport Beach. We had justmoved down when I was asked torescue the FLIDEN project. I com-muted for a month, working morethan two shifts. I found there wereover a hundred wiring errors andinstabilities in some of the circuitry.I was so beat by this schedule thatone late night as I was commutinghome I crossed over the highway toLA airport, then looked up to see awater tower in a town which was 5miles father south. I had no memo-ry of anything in between! I decid-ed that I had to stay in a motel untilI finished the project, which tookabout two more weeks. The projectwas a success, and the FAA used itfor a test facility, but funding fortheir plan never materialized. I pro-posed developing a computer forthe Ford Motor Company. When Ihad a chance to meet with themthey explained that if they went withus and something went wrong itwould be their fault, whereas if theywent with IBM and something wentwrong they would be in the clear,for they had gone with the best!

(Q) Why did you leave Aeronu-tronics?(A) The work in electronics beganto be very much the same as it hadbeen in Ramo-Woolridge, but wesurely loved living in NewportBeach! My mother had been ailing,and I wanted to visit her in SouthDakota, but there never seemed tobe a time when I could be spared,so I just resigned. When we gotthere it became clear that my moth-er had an untreatable cancer andthat it was terminal; she died twomonths later, and we returned forher funeral. It had been a mixedup 1960 so far, and I still had todecide what I would do next.

(Q) When you returned to work atIBM that year, what research didyou do there?(A) When I evaluated the projects

in my division, I found two that Iconsidered to have no usefulfuture – one which a computerdesign which kept being altered,but never completed to the pointwhere it could be evaluated. Theother was a government-fundedproject to develop a computerusing superconductor switches aslogic gates; unfortunately therewas no way to provide any ampli-fication of diminishing signal lev-els. After getting those dropped Ihad mostly software techniquedevelopment and the assignmentof responsibility for defining a newsupercomputer, but with insignifi-cant funding. (Q) After developing the System

360 at IBM, how did you end up inCalifornia again?(A) I was quite tired of the timeand politicking demands andremembered vividly that I had

Letter to Dr. Gene M. Amdahl fromThomas J. Watson, Jr., CEO of IBM,dated February 15, 1978.

Dr. Amdahl with Dr. Hanzo Omi, thefirst Fujitsu man he met (about1966). “Dr. Omi was a very finegentleman and scientist and hadbeen knighted twice by the emper-or for his technical contributions!”G. Amdahl




agreed to go east for a minimum of4 months and a maximum of 7months. I also knew that Dr.Piore’s intent was for me to go tothe Silicon Valley area whenreturned to California. I thenstructured my plan by calling Stan-ford’s Engineering School to see ifthey would invite me to be a visit-ing professor for a couple of quar-ters. They did, so I informed man-agement that I was returning toCalifornia as a visiting professorand that I would go on my own oras an IBM employee, it was up tothem. They elected the latter, andI moved in the fall of 1964.

(Q) Was your Stanford experiencesatisfying?(A) In January [1965] I taught com-puter design at Stanford; this wasquite interesting, for I experiencedquite a large range in the ease thatthe students had in their grasp of thematerial. I never determined the rea-son, for I had no knowledge of theirprevious experiences. The secondquarter I taught was concentrated onthe analysis and explanations for theperformance of a cache memory inenhancing the speed of the comput-er. It was not too well organized, forI was trying to increase my ownunderstanding. Concurrently I wasworking on a number of my petproblems at the IBM lab in LosGatos, with remarkable success.

(Q) Was IBM still planning ways touse your design talent?(A) In late January, while teaching atStanford, I received a telephone callfrom the east coast just before din-ner. The call was to inform me thatI was named an IBM Fellow, whichentitled me to work on any project ofmy choosing, with a small budget tosupport it. While hearing this newsmy knees got weak, and I had tohold on to a cabinet for support;then I heard some chimney fallingand realized it was an earthquakerather than an overly large reactionto the good news! A few monthslater I was asked to consider attach-ing my Fellow activities to a new labIBM was starting called AdvancedComputer Systems, ACS, whichwould be designing a super comput-er, hopefully to serve the Livermoreand Los Alamos labs. The project

would be developing a computerproposed by a group from IBMresearch. I knew quite a bit about itand liked much, but not all, of theplan. I agreed to do it, but being aFellow, I did not report to their man-agement. For a few weeks I tried tomake some changes in areas I didn’tlike, but to no avail. I recognizedthat with the requirement to developthe computer design, the technologyand the total software support, thatthere was no way they could possi-bly find a big enough market to meetIBM’s antitrust requirements of prof-itability. I didn’t want to be associat-ed with a loss-leading project, likehad happened to STRETCH in the1960s, so I thought about the prob-lem and came up with a differentapproach - design the computer tobe System 360 compatible and at thehighest speed we could achieve.This would eliminate all of the soft-ware development cost. To make itprofitable we could design one ortwo smaller machines with the per-formance spacing of the existing360 product line, thus sharing thetechnology development costsover a much larger market andmaybe meeting the profitabilityrequirements.

(Q) How did you fare in thedesign challenge and the conse-quences?(A) I presented my alternative tothe project managers only to haveit rejected out of hand, for theywere wedded to the architecturethey had developed. I was pon-dering how to separate myself fromthe impending loss leader whentheir top logic designer got intosome trouble. The managers con-sidered him unmanageable, butcouldn’t fire him so they found thesolution, transfer him to me! I wasdelighted for he was responsiblefor the design of the most perform-ance determining part of their com-puter. I knew that if he did thedesign of that part of the 360 alter-native, there could be no chargesof faulty design. It took a bit overtwo weeks to describe enough ofmy performance approachesbefore he recognized that it wasreally feasible to compete with theother design. He then went into itwholeheartedly and actually was

able to achieve a slightly higherperformance and a somewhatsmaller cost. Bob Evans came outto ACS with about five technicalpeople and they held a shoot-out.We won and I was made the labmanager. The first thing I did washave the two smaller computerscosted. I then submitted the threesystem plan to corporate pricing.The single highest speed computerwas a loss leader. The secondsmaller computer added made abreak-even program. Adding thethird even smaller computer cameout with normal profit! IBM man-agement decided not to do it, for itwould advance the computingcapability too fast for the companyto control the growth of the com-puter marketplace, thus reducingtheir profit potential. I then rec-ommended that the ACS lab beclosed, and it was.

(Q) What happened after the ACSlab was closed?(A) Just after the shoot-out, abouttwo thirds of the employees leftIBM, most of them forming a start-up venture in designing a time-shar-ing computer; they got about 18months worth of capital investment.A small group started a semiconduc-tor company to develop field effecttransistor memory chips for add-onmemory for IBM computers and alsoan ECL memory chip for cachememories. I stayed on at IBM ana-lyzing the performance of comput-ing systems as a function of memo-ry size and disk and tape storageunits in the environment of multi-programming. While I was doingthis, IBM management learned that acompany called Compat hadannounced a minicomputer. Theyhad granted me permission to be onthe board of my brother’s consultingcompany, Compata, and immediate-ly assumed it was Compat. Theirdiscussions went on for two or threemonths without ever asking mebefore they recognized that it wasn’tCompata; however emotions hadreached such a fever pitch that theysent me a letter demanding that Iresign from Compata’s board, for itdidn’t look good that an IBMemployee was on the board ofanother company in the computerfield. I felt that my name had value



TECHNICAL LITERATUREto him, and as well I was “hot underthe collar” about IBM’s handling ofthe ACS project, so in September1970 I wrote a letter explaining myposition and was resigning fromIBM rather than my brother’s board.I also informed them that I intendedto start my own large computercompany! The president of my divi-sion tried to talk me out of it, forthere was no money to be made inlarge computers!

(Q) Why and how did you decideto start Amdahl Corporation?(A) Ray Williams, the ACS financialman, was aware of my anger anddisgust and came to me with theinformation that he had some con-tacts in the venture capital world.He proposed that we immediatelydevelop a business plan, and he’darrange meetings with the VCs. Wetook about three weeks to do ananalysis of the formidable task ofcompeting head on with IBM, forwe intended to be compatible withIBM and, in fact, use their operat-ing system (we knew IBM haddecided to lease it independentlyof the mainframe to reduce theirantitrust risk). The reason for com-patibility was that the mainframemarket was almost exclusivelyIBM, and that producing a betterproduct than IBM seemed simplerthan changing the market place.

We wrote up our business plan inas open and clear a manner as wecould, outlining the difficulties anddefining our strategies to counterthem. We estimated our capitalrequirements at about $45 million.

(Q) How did you get your firststart-up money?(A) I then traveled to Japan, invit-ed by Fujitsu, to give several lec-tures on computers to their engi-neers and to their board of direc-tors. I had known several of theirtop people for three or four yearsand had great respect for them.When I returned Ray had arrangeda meeting with Ned Heiser,founder of a new venture firm inChicago. We presented our busi-ness plan and requested an invest-ment of $5 million. They consid-ered this for several days and cameback with an offer of $1 million.We refused on the basis that we’dhave nothing accomplished thatwe could show for raising moremoney. They then asked us todetermine the least that we wouldneed, so Ray and I pondered thiscarefully, and decided we coulddo it with $2 million, if we werecareful. Heiser agreed, and wereceived his investment in Decem-ber 1970, two days after receivingan overdrawn notice from ourbank!

(Q) Did you have problemsstaffing and designing a competi-tive computer?(A) We were asked by the ACSstart-up people to agree not tomake employment offers until theyhad given up hope of getting morecapital; we agreed, and in earlyJanuary 22 of their people listenedto our plan and joined, so we wereup and running. My plan to use alarger chip size for easier intercon-nection was improved upon byFred Buelow, who learned therewas a discarded, easily routedapproach called a gate-array,which wasn’t economical enoughfor chip manufacturers, but wecould get a 100 gate chip, Large-Scale-Integration (LSI). This wasphenomenal, for the ACS technol-ogy only provided about 35 gates,Medium-Scale-Integration (MSI),and took three or four months for

a gifted man to route! With apackage redesigned to providemuch better heat conduction wecould use air cooling instead ofchilled water. We tried to get thebig semiconductor companies tomake our chips for us, but none ofthem would. Texas Instruments lis-tened to our presentation, but after20 minutes their vice presidentcalled me aside and said that itwouldn’t work, and if it did it wasthe wrong level of integration, andif we kept on we would spend allour money and go belly-up withnothing to show for it! Quite dis-concerting!

(Q) How did you finance such ademanding undertaking?(A) During these early days Fujitsufriends would drop by from timeto time. They never asked muchabout our progress but they musthave sensed our growing confi-dence, for in late spring they askedif we would consider an invest-ment from them; they felt it wouldneed about 5 days of presentationto evaluate us thoroughly, andthey would sign an agreement toprotect our technology. We agreedand presented for three days. Onthe fourth day they stopped ussaying they fully believed. Theyinvested $5 million and sent 20engineers to assist in the develop-ment. Shortly after the presenta-tion our LSI chips came back, andthey performed just as predicted!We went on trying to raise morecapital, but no venture capital firmbelieved we could compete withIBM. It was difficult to argue thecase since RCA, General Electric,Xerox, and Philco were all gettingout of computers; RCA and Gener-al Electric had each spent about $5billion and were giving up! A sur-prise visit by Heinz Nixdorf fromGermany was exciting, for after afew hours he agreed to put in $5million. This also excited Fujitsu,for they decided to invest an addi-tional $5 million! These eventsstirred the venture capital peopleto invest $7.8 million!

(Q) How did you avoid encroach-ing on other IBM patents and othertechnical property?(A) When we started the design of

Gene M. Amdahl and Raymond A.Williams, the co-founders of AmdahlCorporation, playing in the “Live OakInvitational golf tournament atSharon Heights Golf and Country Clubin Menlo Park, CA, Gene’s club. Circa1995.




our computer I reminded every-body that we were all bound byour agreements with IBM not touse any of their intellectual prop-erty, but that if we used only thedescriptions in the IBM’s publiclyprovided user’s manual to do ourdesigns, it would be free of con-flict. Fortunately none of thedesigners had ever designed a 360computer, so that manual was nec-essary and there was no carryoverof 360 logic detail. I had a friendin IBM’s legal staff who laterinformed me that IBM had madetwo in-depth investigations of ourproduct to determine if there wasany misappropriation of IBM prop-erty, but decided we were clean asa hound’s tooth, however cleanthat is. We also had to test theavailability of the IBM operatingsystem licensed to our computer.We ordered it, and it took IBMalmost two months to decide theyhad to do it, but they did! In short,we didn’t do anything quite likeIBM’s patent coverage, and wetook advantage of their droppingtheir tie-in software policy as wellas their well-defined market place!

(Q) How could you develop aproduct so much faster than IBM’s?(A) The technology in our comput-er was much more advanced thanIBM’s, for we had opted for the LSIchip with 100 gates rather than theMSI (medium scale integration)with only 35 gates. This meant wecould avoid nearly two thirds ofthe chip crossings, which wouldcost significant time delays in thelogic paths involved. This alsoreduced the size of the machine,and each foot of wire cost 1nanosecond. We also designed asimpler machine, by a more order-ly, but not slower, instruction exe-cution sequence like I used in theWISC. There was also another fac-tor, based on IBM’s market man-agement approach, where theyavoided too great an advance intechnology upgrades, for userscould drop down one member ofthe 360 family if the smaller mem-ber was fast enough. Amdahl’soffering was a bit more than threetimes faster than IBM’s large mem-ber, and we priced it most compet-itively, for we had to overcome

customer’s management that IBMwas the only safe decision.

(Q) Why did you think you couldcompete with IBM when RCA andGE couldn’t?(A) IBM’s earlier competitorsdeveloped their offerings whileIBM was “bundling” its softwarewith its hardware, therefore thecompetitor had to develop its ownsoftware. RCA designed a machinenearly compatible with IBM’s andsoftware that was also quite simi-lar; however, the deviations fromIBM’s hardware were carefullydesigned to appear easy to moveto, but not appear too difficult toreturn to IBM if they didn’t like it.RCA, however, had made it quitedifficult to return, for they consid-ered it to be the “barb” on theirfishhook! Being later and IBMinsiders, we had the advantage toplan on IBM having to maintain itsunbundling; however, the VentureCapital world was unable to read-just its thinking when the newstrategy was presented by an aspir-ing startup! Some even thoughtwe couldn’t design an IBM com-patible computer since RCA could-n’t! The cost of developing ourown operating system and othersupporting software would havewell more than doubled our capi-tal requirements!

(Q) Why could you plan on usingthe IBM operating system?(A) When IBM decided that theywere in serious risk of an antitrustaction for offering their hardwarecomplete with all of the software,thus virtually keeping any othersupplier from being able to makean economically attractive offer inthis marketplace, they decided theseparation of their software pack-age from the hardware would notbe too costly, as long as the soft-ware package was kept bundled(this is my guess, for I was notinvolved in any decision-making).The pricing of the software bundlewas also economical enough todiscourage competition. IBM alsodid not make too big a publicannouncement as far as my recol-lection of the event, for the VCsdidn’t seem aware of it. IBM alsotook quite a bit of time to decide

they had to honor our order fortheir software package to belicensed to an Amdahl computer,but I was convinced they had to orthe antitrust threat would immedi-ately materialize!

(Q) How did Amdahl’s marketingresults progress?(A) The initial market penetrationby Amdahl was its first sale to theNASA space computing center inNew York, where we wereallowed to being installation onFriday night, with the expectationthat it would take about a weekand a half, like IBM required, butwere astonished when they wereinformed on Sunday noon that thecomputer was ready for use! Thenext sales were primarily to Uni-versities, where student usersappreciated the opportunity to mixin some of their own system soft-ware, rather than being restrictedto only IBM’s. We also sold one toa computing job-shop, but wewere still not able to get a commit-ment from a commercial accountuntil Massachusetts Mutual Insur-ance Company, who was veryunhappy with IBM, decided to buyfrom us instead. The installationwas very successful, and it wasrecognized that the Amdahl com-puter was viable! That broke thelog jam, and most of our comput-ers were sold to commercial enti-ties! Within the next 18 months,we had sold enough so that ournet profit, which was 30%, just likeIBM’s, had paid off all of our cor-porate development cost, whichhad reached some $60 million! Sowe had a perfect balance sheet.Our first full year of shipments hadbeen $96 million, our second yearhad been $196 million, and ourthird year had been $320 million!IBM had, of course, been effective-ly reducing its prices by buyingcustomer software packages of lit-tle value to them and had soldmany more machines than we had,but they realized they had toreduce the customer’s cost of com-puting to preserve their marketplace.

(Q) How did IBM respond to yoursuccess?(A) The next move by IBM was the



TECHNICAL LITERATUREannouncement of a new 360improved family, the first to be the3030 (I’m sure you hunters canrecognize the significance of thatchoice of number). This machinewas to be equal in speed toAmdahl’s and was to be priced30% lower than ours! Immediatelywe analyzed what we had to do torespond. We came up with animprovement of our own, includ-ing a smaller version to expand themarket we addressed. We also hadto negotiate with Fujitsu to getlower prices on their manufacturedparts (their manufacturing hadbeen very profitable, and with asmaller version, they could reducetheir prices and still fare as well).With this plan, we were able tomaintain our 30% pretax profit inspite of IBM’s attempt to “mow ourgrass to ground level”. Over timeour competition reduced the costof computing for the mainframecustomers by over an order ofmagnitude! IBM retaliated in Japanby calling on the government tolimit the use of their architectureand software there, or they wouldreduce the prices in Japan to killoff the Japanese computer compa-nies, or so the governmentinformed Fujitsu of this.

(Q) How did you expand yourmarket into Europe?(A) Nixdorf had not been a signif-icant player, for their marketingpeople had only had experienceselling small machines, and theydecided not to try to make achance as drastic as would berequired, so they sold their stockfor a very significant profit.Amdahl entered the Europeanmarket, first in Germany uponreceiving an inquiry and visit fromthe Max Planck Institute in Munichand from the European SpaceAgency in Ober Pfaffen Hofen(with Nixdorf’s blessing and assis-tance), then in Norway where Iwas questioned about my recollec-tions of my Norwegian roots andcoerced into singing a song writtenby the immigrants (this was publi-cized in Fortune Magazine underthe title “A Frog Sings in Norway”).Italy came to us in the person ofthe former IBM country managerwho now had responsibility for all

central government computing,and who couldn’t get a deal fromIBM. In France I struck a dealwhere we would get import licens-es for any sale we could make ifwe could have anything made forour computer in a factory inToulouse. Being an inveterate pun-ster I informed my VP of engineer-ing that to get the proper picturehe should make “la trek Toulouse”.We were quoted a price for mem-ory which was slightly less than itcost us to make it! Britain was easyto enter, but later.

(Q) Your relationship with Fujitsuwas so strong; did you ever con-sider tempering it?(A) I was concerned that ourdependence on Fujitsu was in dan-ger of making us effectively a sub-sidiary, and I felt that the only waywe could be independent wouldbe to find an alternative supplier ofnew and much denser chips forour new advanced computer offer-ings. I was unable to get supportfrom the engineering staff, for theyfelt they were not capable of deal-ing with some of the problems thatmight come up. In the meantimeFujitsu heard of this and began totry to make me stop agitating,accept their new planned chips. Itgot bad enough that the presidentcame to Sunnyvale [California] andverbally chewed me out. I hadwanted a reduced dependence onFujitsu, not a separation fromthem, for I was very much mindfulthat without them Amdahl wouldnever have survived! I also hadquite a number of very closeJapanese friends, and I still havethem today. I must also say thatFujitsu treated the company veryfairly for the rest of its existence.

(Q) Did your efforts affect yourhealth?(A) The stress of this struggle wasso severe that my back went intospasm. Some twelve years earlierI had ruptured a disc, and it hadhealed, but it had still remainedvery sensitive. I realized that thisspasm was so severe that I could-n’t go back to work for quite along time, so I decided it was bestto resign rather than continuestruggling.

(Q) What did you think you coulddo as a follow-on to Amdahl Cor-poration?(A) My back took about eightmonths to get back to near normal-ity. During that time I ponderedwhat I should do when healed.Carl and I brainstormed an interest-ing approach to very large scaleintegration, which we felt couldmake a wafer-size chip! I men-tioned it to Clifford Madden,Amdahl’s VP of Finance. He got soexcited that he insisted that thethree of us should start a new com-pany!

(Q) If incurring so many problemsin building a semi-conductor facil-ity, how could you have done itdifferently?(A) I was chairman of the board, forI still had to protect my back, Clif-ford was president, and Carl washead of engineering. We named thecompany Trilogy, for the techniqueemployed to make the wafer-scaleintegration with high yield was touse triplet gates, where it was possi-ble to test each gate and be able toremove one, or even two, of thegates if they were faulty, thus assur-ing an effectively working gateunless all three were faulty. Thefinancial planning communitybecame wildly excited, and wemanaged to acquire over $100 mil-lion. Carl and I had planned tohave a semiconductor companyprocess the chips, but some of thethings we would have to do weren’tstandard, so the president decidedwe’d have to build our own facili-ties. The building of the super cleansemiconductor facility was delayedduring construction by unusuallyheavy and extended rains, so thecosts mounted more rapidly thanplanned. The complexity of therouting program software, deposit-ing enough metal for high powerdistribution and good bonding ofthe chip to the chip carrier weresolved, but took extra time. Theonly problem we hadn’t completelysolved was the leakage of etchingfluids through layers of interconnec-tion, (the universal problem for allsemiconductor companies). We esti-mated that two more passes of mak-ing the chip, testing for leakagefaults, determining how to modify




the masks to fix it and making thenew masks would take about 24months. The costs of the delays hadreduced our capital so much thatonly about 24 months of run ratewere left! We had proven to oursatisfaction that we could do the

wafer sized chip, for we had madethree-quarters of the wafer success-fully, but by the time we could suc-cessfully produce our full chiprepeatedly, we would have nomoney left to exploit it, and we feltcertain we could not raise more

money! Carl suggested we couldsuccessfully produce 1/4 size chipsand design a small product usingthem. I felt that the level of revenuewe could achieve with thatapproach could hardly keep usafloat, so I contacted some of ourprincipal investors and asked whatthey would recommend. Theyasked us to acquire a company witha computer product that would ben-efit from our remaining funds, sowe did that. The negative publicityfrom this was as large as the positivepublicity when we started!

(Q) What was it about a start-upcompany that made it so attrac-tive to you?(A) If I had the chance to do it allover again I would first offerenough money to a semiconductorcompany to compensate for solvingthe nonstandard processes. If thatwouldn’t work, I would take Carl’ssuggestion and see if we could sellthe product design and chip avail-ability to stay in business. Thesemight not have worked, but if theydid we could have made a signifi-cant success! I strongly enjoyed theatmosphere of cooperative enthusi-asm in the start-up adventure!

Dr. Amdahl and his son Carl at the founding of Trilogy (circa 1981). They wereChairman and Vice President of Engineering, respectively. Clifford Madden, thePresident, was not available for this photograph.




About Gene M. Amdahl

Computer designer, author,inventor and corporate exec-utive, Gene Amdahl began

his career in information processingin 1952 with IBM Corporation inPoughkeepsie, New York.Between 1952 and 1960 he heldpositions as chief designer for the704, initial planner for the 709 and7030, and manager of architecturefor the System/360. Besides hisbachelor’s degree in EngineeringPhysics from South Dakota StateUniversity in 1948, he holds a Ph.D.in Theoretical Physics from the Uni-versity of Wisconsin, 1952.

While beginning work on hisdoctorate, he designed the firstoverlapped, electronic floating-point computer. In his doctoralthesis, he described how to buildthe computer he had designed.The construction of that computertook place over a period of fouryears by students at the Universityof Wisconsin. Although initiallydirected by him, until 1978 Dr.Amdahl never saw the finishedproduct. The computer had longsince been given to a private partyupon whose death it was offeredto Dr. Amdahl. The computer iscalled the WISC (Wisconsin Inte-grally Synchronized Computer).

In June of 1952 Gene Amdahljoined IBM and initially worked oncharacter recognition and intelli-gence simulation. In 1953 he wasmade chief planner and projectengineer for the IBM 704 develop-ment program. Following that, hedid the initial planning for the IBM709 and IBM 7030, before leavingIBM at the end of 1955.

In 1956 Dr. Amdahl joined RamoWoolridge in Los Angeles, wherehe prepared several military andinternal proposals in the data pro-cessing field. In addition, he didthe system planning for whatbecame the RW440 process controlcomputer.

In late 1956, he joined Aeronu-tronics, a subsidiary of the FordMotor Company, where he headedthe commercial data processingdepartment which was responsiblefor electronic data entry and com-

puter equipment.He rejoined IBM in 1960 and

during the period 1960-1970, wasdirector of experimental machines,manager of systems design foradvanced data processing systems,manager of technology for highspeed systems and director of theAdvanced Computing Systems Lab-oratory (which he assisted infounding). He was named an IBMFellow in 1965 at a time when fewpeople in IBM received that honor.The appointment, made for a five-year period, freed the recipient toengage in the work of his choice.

Dr. Amdahl is holder and co-hold-er of many patents on such develop-ments as recognition of recordedintelligence, analog-to-digital conver-sion device, message display andtransmission system, stored logiccomputer, large-scale shifter, memoryprotection system, storage protection

system, and the IBM System/360. Hehas written several articles on com-puter-oriented subjects and conduct-ed a lecture series at Stanford Univer-sity, as well as being a guest lecturerof the NATO Summer School inFrance in 1969 and 1976.

Gene left IBM in 1970 to form andoperate his own company, AmdahlCorporation, for the purpose ofdeveloping what was to become theAmdahl 470 family of computers –said to be the highest performing,largest capacity general-purpose busi-ness computers to date. The 470V/6computer was put into operation injust over four years, despite the gar-gantuan task of founding a large cor-poration, raising capital investmentfunds, pushing the state-of-the-art,attracting high caliber personnel anddealing with the multitude of detailsconnected with its operation. Heresigned as Chairman of the Board

A ceremonial signing (circa 1978) of the purchase documents for four Amdahl470 computers by British Overseas Airlines Company, BOAC. In the upper leftis Peter Williams, Head of Amdahl UK. Dr. Amdahl is seated at the lower left.The other people are BOAC Executives.



on September 1, 1979, and served asChairman Emeritus and Consultant tothe company until he severed all tieswith the company on August 31,1980.

In the fall of 1980, Dr. Amdahlfounded another venture, TrilogySystems, which acquired Elxsi in1985 for its principal computer sys-tem entry.

After 1987 Dr. Amdahl foundedAndor International, Ltd., a com-puter systems company in its prod-uct development stages.

Dr. Amdahl holds an honoraryDoctor of Engineering Degree fromSouth Dakota State University and isa Distinguished Alumnus of that uni-versity. He is recipient of the W.Wallace McDowell Award sponsoredby the IEEE Computer Society for hisoutstanding contributions to techni-cal design and computer architec-ture. He holds an honorary Doctor

of Science Degree and DistinguishedService Citation from the Universityof Wisconsin. He is recipient ofCase Western University’s presti-gious Michelson-Morley Award pre-sented to an engineer or scientist inrecognition of outstanding achieve-ments and contributions to the wellbeing of mankind. He is recipient ofthe Data Processing ManagementAssociation’s Computer SciencesMan-of-the-Year Award for 1976. Heis a Distinguished Fellow of theBritish Computer Society in recogni-tion of this work in computer design(1979). He is an elected member ofthe Quadrato della Radio (the Mar-coni Society – Italy, 1980). Hereceived an Honorary Doctorate ofScience from Luther College, Deco-rah, Iowa, in October, 1980. He isthe recipient of the University ofSouthern California’s “Entrepreneur

of the Year” Award, February 1981.Augustana College, Sioux Falls,South Dakota, awarded him theHonorary Doctorate in Science inMay 1984. He is the recipient of theHarry Goode Memorial Award,sponsored by the American Federa-tion of Information Processing Soci-eties in recognition of his outstand-ing contributions to the design,applications, and manufacture oflarge-scale, high-performance com-puters in May 1983. He was elect-ed Fellow of IEE in Great Britain in1987. He is the recipient of the Eck-ert Mauchly Award from the ACM-IEEE Computer Society in 1987. Heis the recipient of the CentennialAlumnus Award from the SouthDakota State University – NationalAssociation of State Universities andLand Grant Colleges in 1987.

In addition, he is a member ofthe National Academy of Engineer-ing (elected in 1967) and a Fellowand member of the IEEE Profes-sional Group. In 1973 he wascited in Business Week and For-tune magazines as being one ofthe “brightest new stars rising tochallenge the computer giant –IBM.” The London Times includedDr. Amdahl in its list of “The thou-sand makers of the 20th century.”

Gene M. Amdahl was born on afarm in Flandreau, South Dakota,November 16, 1922. Gene andMarian D. Quissell were married in1946; they have three children andreside in Palo Alto, California.


After the ceremonial signing (circa 1978), BOAC held a photo shoot beside theirSuper Sonic Transport (SST), Dr. Amdahl then flew back to New York on it.

Report published by Auerbach Pub-lishers Inc. in 1975 describing the listof advances of the 470V/7 over theIBM 680.

This photograph (circa 1984) shows the three parts of the Trilogy wafer-scalechip carrier. On the right is the chip in its wafer-cooled section. In the centeris the pressure contactor to the chip for power connections to the chip. On theleft is the 1,024 signal connector to the computer system.


Summer 2007 IEEE SSCS NEWS 19Summer 2007 IEEE SSCS NEWS 19

For over a decade prophets havevoiced the contention that theorganization of a single computerhas reached its limits and that trulysignificant advances can be madeonly by interconnection of a multi-plicity of computers in such amanner as to permit cooperativesolution. Variously the properdirection has been pointed out asgeneral purpose computers with ageneralized interconnection ofmemories, or as specialized com-puters with geometrically relatedmemory interconnections and con-trolled by one or more instructionstreams.

Demonstration is made of thecontinued validity of the singleprocessor approach and of theweaknesses of the multiple proces-sor approach in terms of applica-tion to real problems and theirattendant irregularities.

The arguments presented arebased on statistical characteristicsof computation on computers overthe last decade and upon the oper-ational requirements within prob-lems of physical interest. An addi-tional reference will be one of themost thorough analyses of relativecomputer capabilities currentlypublished- "Changes in ComputerPerformance," Datamation, Sep-tember 1966, Professor Kenneth E.Knight, Stanford School of Busi-ness Administration.

The first characteristic of interestis the fraction of the computation-al load which is associated withdata management housekeeping.This fraction has been very nearlyconstant for about ten years, andaccounts for 40% of the executedinstructions in production runs. Inan entirely dedicated special pur-pose environment this might bereduced by a factor of two, but it ishighly improbably that it could bereduced by a factor of three. Thenature of this overhead appears tobe sequential so that it is unlikelyto be amenable to parallel process-ing techniques. Overhead alonewould then place an upper limiton throughput of five to seventimes the sequential processingrate, even if the housekeepingwere done in a separate processor.The non-housekeeping part of theproblem could exploit at most aprocessor of performance three tofour times the performance of thehousekeeping processor. A fairlyobvious conclusion which can bedrawn at this point is that the effortexpended on achieving high paral-lel processing rates is wastedunless it is accompanied byachievements in sequential pro-cessing rates of very nearly thesame magnitude.

Data management housekeep-ing is not the only problem toplague oversimplified approachesto high speed computation. Thephysical problems which are ofpractical interest tend to haverather significant complications.Examples of these complicationsare as follows: Boundaries are like-ly to be irregular; interiors are like-ly to be inhomogeneous; computa-tions required may be dependenton the states of the variables ateach point; propagation rates ofdifferent physical effects may bequite different; the rate of conver-gence, or convergence at all, may

be strongly dependent on sweep-ing through the array along differ-ent axes on succeeding passes, etc.The effect of each of these compli-cations is very severe on any com-puter organization based on geo-metrically related processors in aparalleled processing system. Eventhe existence of regular rectangularboundaries has the interestingproperty that for spatial dimensionof N there are 3N different pointgeometries to be dealt with in anearest neighbor computation. Ifthe second nearest neighbor werealso involved, there would be 5Ndifferent point geometries to con-tend with. An irregular boundarycompounds this problem as doesan inhomogeneous interior. Com-putations which are dependent onthe states of variables wouldrequire the processing at eachpoint to consume approximatelythe same computational time asthe sum of computations of allphysical effects within a largeregion. Differences or changes inpropagation rates may affect themesh point relationships.

Ideally the computation of theaction of the neighboring pointsupon the point under considera-tion involves their values at a pre-vious time proportional to themesh spacing and inversely pro-portional to the propagation rate.Since the time step is normallykept constant, a faster propagationrate for some effects would implyinteractions with more distantpoints. Finally, the fairly commonpractice of sweeping through themesh along different axes on suc-ceeding passes poses problems ofdata management which affects allprocessors; however, it affects geo-metrically related processors moreseverely by requiring transposingall points in storage in addition tothe revised input-output schedul-ing. A realistic assessment of the

Validity of the Single Processor Approach toAchieving Large Scale Computing CapabilitiesReprinted from the AFIPS Conference Proceedings, Vol. 30 (Atlantic City, N.J., Apr. 18–20),AFIPS Press, Reston, Va., 1967, pp. 483–485, when Dr. Amdahl was at InternationalBusiness Machines Corporation, Sunnyvale, California

Dr. Gene M. Amdahl


This article was the first publica-tion by Gene Amdahl on whatbecame known as Amdahl's Law.Interestingly, it has no equationsand only a single figure. For thisissue of the SSCS News, Dr.Amdahl agreed to redraw the fig-ure. In the available hard copy itwas illegible. We print this his-toric paper to enable members toread the original source fromsome 40 years ago.

The Editors



effect of these irregularities on theactual performance of a parallelprocessing device, compared to itsperformance on a simplified andregularized abstraction of theproblem, yields a degradation inthe vicinity of one-half to oneorder of magnitude.

To sum up the effects of datamanagement housekeeping and ofproblem irregularities, the authorhas compared three differentmachine organizations involvingapproximately equal amounts ofhardware. Machine A has thirtytwo arithmetic execution unitscontrolled by a single instructionstream. Machine B has pipelinedarithmetic execution units with upto three overlapped operations onvectors of eight elements. MachineC has the same pipelined execu-tion units, but initiation of individ-ual operations at the same rate asMachine B permitted vector ele-ment operations. The performanceof these three machines is plottedin Figure I as a function of the frac-tion of the number of instructionswhich permit parallelism. Theprobable region of operation iscentered around a point corre-sponding to 25% data managementoverhead and l0% of the problemoperations forced to be sequential.

The historic performance versuscost of computers has beenexplored very thoroughly by Pro-fessor Knight. The carefully ana-lyzed data he presents reflects notjust execution times for arithmeticoperations and cost of minimum ofrecommended configurations. Heincludes memory capacity effects,input-output overlap experienced,and special functional capabilities.The best statistical fit obtained cor-responds to a performance propor-tional to the square of the cost atany technological level. This resultvery effectively supports the ofteninvoked “Grosch’s Law.” Utilizingthis analysis, one can argue that if

twice the amount of hardwarewere exploited in a single system,one could expect to obtain fourtimes the performance. The onlydifficulty is involved in knowinghow to exploit this additional hard-ware. At any point in time it is dif-ficult to foresee how the previousbottlenecks in a sequential comput-er will be effectively overcome. If itwere easy they would not havebeen left as bottlenecks. It is trueby historical example that the suc-cessive obstacles have been hur-dled, so it is appropriate to quotethe Rev. Adam Clayton Powell-"Keep the faith, baby!" If alterna-tively one decided to improve theperformance by putting twoprocessors side by side with sharedmemory, one would find approxi-mately 2.2 times as much hard-ware. The additional two tenths inhardware accomplish the crossbarswitching for the sharing. Theresulting performance achievedwould be about 1.8. The latter fig-ure is derived from the assumptionof each processor utilizing half ofthe memories about half of thetime. The resulting memory con-flicts in the shared system wouldextend the execution of one of twooperations by one quarter of theexecution time. The net result is aprice performance degradation to0.8 rather than an improvement to2.0 for the single larger processor.

Comparative analysis with asso-ciative processors is far less easyand obvious. Under certain condi-tions of regular formats there is afairly direct approach. Consider anassociative processor designed forpattern recognition, in which deci-sions within individual elementsare forwarded to some set of otherelements. In the associativeprocessor design the receiving ele-ments would have a set of sourceaddresses which recognize byassociative techniques whether ornot it was to receive the decisionof the currently declaring element.To make a corresponding specialpurpose non-associative processorone would consider a receivingelement and its source addressesas an instruction, with binary deci-sions maintained in registers. Con-sidering the use of thin film mem-ory, an associative cycle would belonger than a non-destructive readcycle. In such a technology thespecial purpose non-associativeprocessor can be expected to takeabout one-fourth as many memorycycles as the associative versionand only about one-sixth of thetime. These figures were comput-ed on the full recognition task,with somewhat differing ratios ineach phase. No blanket claim isintended here, but rather that eachrequirement should be investigat-ed from both approaches.


The diagram above illustrating “Amdahl’s Law” shows that a highly parallel machine has a harder time delivering a fairfraction of its peak performance due to the sequential component of the given computation and the overhead of coor-dination (e.g. synchronization) between the processors. Assuming a fixed sized problem, Amdahl speculated that mostprograms would require at least 25% of the computation to be sequential (only one instruction executing at a time),with overhead due to interprocessor coordination averaging 10%. The curves show that the more you depend on par-allelism for performance, the slower the system is likely to be in the probable case, 65%. The lowest curve (A) repre-sents the 32-wide SIMD processor, and the top curve (C) is for the modified vector processor. Scaled problems reducethe sequential component and the coordination overhead to a negligible level, making large numbers of processors veryefficient in those cases. Justin Rattner, Intel Senior Fellow, [email protected], July 2007.



CORRECTIONS – Winter 2007On page 12 in “A 30 Year Retro-spective on Dennard’s MOSFETScaling Paper” by Mark Bohr, thefirst paragraph should read: “1 umtransistor” not “1 mm transistor.”The second paragraph on page 12should read: “<10-10 amps/um”not “<10-10 amps/mm.” Receivedfrom Mark Bohr

On page 62, the name of the stu-dent design contest should be“DAC/ISSCC,” as a joint effort ofthe Design Automation Conferenceand the ISSCC. Received fromAnantha Chandrakasan

IMPORTANT SYSTEM NOTES:Internet Explorer 7 Will Not RunOlder SSC Digital Archive DVDs

2005 and prior DVDs will not workon Internet Explorer 7. For them towork either install Firefox(www.firefox.com) and use it tobrowse the DVD or downgradeback to Internet Explorer 6. Theerror message presented when run-ning these older disks on Explorer7 is ‘Cannot connect’ or ‘Page can-not be displayed’.

The 2006 pair of Archive DVDs,Foundations and Update work finewith Internet Explorer 7. They weremailed to subscribers in April. Topurchase your copy for $40 memberprice, order through the IEEE onlinestore shop.ieee.org/ieeestore/Prod-uct.aspx?product_no=JD28106

For tech support please [email protected].

CLARIFICATION - TransistorPatent HistoryMichael Riordan, the author of the

Spring 2007 SSCS News article“Crystal Fire, the Invention, Devel-opment and Impact of the Transis-tor,” wrote us to note “One smallpoint. The Shockley patent on pp.30-31 is not his key patent on thejunction transistor, which was filedon 26 June 1948 and (I believe)awarded later. I think the one youpublished is his patent on “filamen-tary” transistors, based on workthat was done in the summer of1948.”

SSCS excerpted Shockley’s earli-est patent based on issue date.Other sources agree with Riordanthat Shockley’s patent 2,569,347,

issued 5 months later but filedearlier, is the first appearance of“the brilliant revolutionary con-ception of the junction transistor.”(P.K. Bondyopadhyay, Proceed-ings of the IEEE “Shockley, thetransistor pioneer-portrait of aninventive genius”, Jan 1998 Page191 – 217)

For the Proceedings article (loginrequired): ieeexplore.ieee.org/search/wrapper.jsp?arnumber=658771

For free access to four historictransistor patents see “The Road tothe Transistor,” by Jed Margoliniwww.jmargolin.com/history/trans.htm

Shockley’s brilliant revolutionary conception of the junction transistor. Patent2,569,347, filed 26 June 1948.


PEOPLE


Dr. Gene Amdahl will receive a SIGDA “Pio-neering Achievement” award and will be thefeatured guest at the ACM/SIGDA member

meeting of ICCAD in San Jose, California on Tuesdayevening, 6 November. Normally limited to members,the meeting will be opened to all who wish to attend.

This year marks the 40th anniversary of “Amdahl’sLaw,” which has had a profound influence on thedesign of microprocessors and on computing systemsin general. In an address at the meeting, Dr. Amdahlwill describe the Law from a historical perspectiveand discuss its impact on systems being designedtoday. SIGDA organizers anticipate that there will bean extended discussion and some debate followinghis talk.

As the world's premier conference in electronicdesign technology, ICCAD (The International Confer-ence on Computer-Aided Design sponsored byIEEE/ACM) is an ideal venue for recognizing Dr.Amdahl. It is the major technical conference and net-working event for designers and design technologyprofessionals, covering system design, synthesis,modeling, simulation and layout for both traditionalCMOS and new nano-technologies.

Amdahl’s Law grew out of a spirited debate at theAFIPS Joint Computer Conference in 1967. At thetime, many computer designers believed that parallelcomputation was the obvious next step in enhancingperformance. Dr. Amdahl took a dissenting position,and instead advocated a focus on faster serial com-putation based on several simple mathematical obser-vations. In keeping with the spirit of the debate forty

years ago, Dr. Amdahl has made it clear that he wouldwelcome interruptions and discussion during his talk.

In its simplest form, Amdahl's Law assumes that forany computing task, S percentage of instructions mustbe performed in serial fashion, while P percentagecan be performed in parallel. The possible speedupthat could be achieved through parallel computationwith n processors would then be at best 1/(S + P/n).By looking carefully at a number of software applica-tions, and by studying work done by Prof. KennethKnight at Stanford, Dr. Amdahl inferred that there wasa significant percentage of serial work for most appli-cations. No matter how many processors mightbecome available, one would expect relatively limitedspeedup, with additional processors giving diminish-ing returns. Amdahl’s Law goes against intuition; onemight expect a factor of four improvement with fourprocessors. In practice, this is seldom the case.

Over the past four decades, many groups havetried to circumvent Amdahl's Law through cleverinterconnect structures, elaborate compilers, andalternative computing models. To date, however,progress has come through the avenues that Dr.Amdahl advocated. Improved serial computationthrough faster devices and wires, circuit optimization,and ever increasing clock rates has fueled the semi-conductor industry. Only a handful of applications(primarily graphics and large-scale scientific computa-tion) have enjoyed any significant benefit from par-allel computation. There is an industry-wide resur-gence of interest in parallel computation, spurred bymulti-core microprocessors; it is not yet clear how thisgeneration will deal with Amdahl’s Law.

Dr. Gene Amdahl to Speak at ICCAD 2007 Pioneering Achievement Award will Commemorate 40th Anniversary of “Amdahl’s Law”

Patrick H. Madden, SUNY Binghamton CSD [email protected]

Congratulations New Senior Members19 Elected in April

Giovanni Anelli Switzerland SectionStephen Bates Northern Canada SectionStephen Burnham Eastern Idaho SectionMrinal Das Bangalore SectionDaniel Foty Green Mountain SectionPatrice Gamand France SectionJae-Hong Hahn Oregon SectionW Margaret Huang Phoenix SectionEric A. M. Klumperink Benelux SectionMasaru Kokubo San Francisco Section

Sanjay Raman Virginia Mountain SectionRicardo A. Reis South Brazil SectionAntonio G. M. Strollo Italy SectionThomas Thomas Oregon SectionAxel Thomsen Central Texas SectionArnaud Tisserand France SectionF. E. Van Vliet Benelux SectionDerrick Wei Central Texas SectionDavid Yokoyama-Martin Oregon Section



PEOPLE

The ChallengeISSCC is the foremost milieu for presenting original workin the area of solid-state circuits and systems-on-a-chipand related system considerations. Thus, it is not surpris-ing that many engineering, design and computer profes-sionals strive to present their work at the conference,where experts from industry and academe around theworld gather to discuss the next generation of solid-statecircuits and systems.

This article is intended as a guide for prospectivesubmitters to improve their chances of paper accept-ance. But, as someone wishing to submit a paper toISSCC, you have a very basic and serious challenge: Itis that the ISSCC Technical-Program Committee is verydiligent in pursuing its goal of maintaining the highstandards for which the conference is known, and therewill be substantial competition from other submissions.

Key Criteria for AcceptanceThere are two key requirements that each authormust keep in mind when submitting a paper.

First and foremost is the technical quality of thework: Your paper will be read by expert reviewers (asmany as 15 per paper!) who are very familiar with thestate-of-the-art. You must convince them that theproduct of your work performs better than the mostrecent work of others, or describes an innovativeconcept and implementation.

Second is the quality of the draft manuscript: Yourpaper must allow reviewers to effectively evaluateyour contribution and to compare it easily with previ-ous work, and other submissions to the conference.

Early ConsiderationsBefore submitting your paper, you should ask your-self the following questions:• Does your paper advance previous work, or does it

introduce a new design concept? • Does the paper have hardware? In particular, has a

chip been fabricated and tested? While an innovative concept can be demonstratedthrough simulation, it is desirable to show resultsfrom a working chip.

• Does the topic of the paper fit within the scope ofISSCC? If so, within which of the subcommittees doesthe paper fit? (Note that the detailed topics coveredby ISSCC are assigned to subcommittees, described inthe Call for Papers at www.isscc.org/isscc.)

If the answer to any of these questions is negative,you may consider submission to another conference.In addition, if a substantial part of your paper hasalready been (or will be) published, you should not

submit the work, since the subcommittee will reject itdue to pre-publication. (To find out more about whatconstitutes prepublication, consult the Call for Papersor the ISSCC Website.)

Technical ContentThere are many good ways to write a paper andthereby to present your work in a clear and concisemanner. The remainder of this article is only onemethod of doing so. While it is by no means the onlyone, it can be effective if done well.

Independent of your choice of style, bear in mind,when writing the paper, to emphasize specific newresults with sufficient detail and data so as to be eas-ily understood. Also include schematics and measuredresults for key circuits, whenever appropriate.

Further detailed comments on the properties of agood paper follow, by section, below. Note that thisdescription reflects the order of your paper, not neces-sarily the order in which the sections may be written.For example, it is often best to write the conclusions first!

The IntroductionStart your paper with a brief introduction that clearlystates the nature and context of the problem you aresolving. Compare your approach with what othershave done recently, highlighting how yours is differ-ent and better. An important technique is to makegood use in the introduction of references to put yourwork into its correct context. References tell thereviewer that you are aware of the latest develop-ments in the field. Use recent ISSCC references when-ever possible; otherwise, emphasize IEEE journal andconference references. It is strongly recommendednot to use old references, except to emphasize thetime scale of the problem. Do not refer only to yourown work. A good write-up typically has 4 to 6 keyreferences. Comment briefly on each and every one ofthe items in your reference list, within your main text.

The Body of the PaperKeep in mind that you have a maximum of only 1100words for the body of the paper, so use the limitedspace carefully. Plan in advance, and make an out-line, very much like you design a system architecture.Early on, give the specifications of your design. Youshould highlight and emphasize innovative aspects.Explain the importance of these features in terms ofnew design, improved performance (that is, power,speed, etc), achievements, as well as new technology,and how they advance the state-of-the-art.

The central part of the paper should explain details

TOOLS:ISSCC PAPER SUBMISSIONS - INCREASING THELIKELIHOOD OF SUCCESSTips on Increasing Your Chance of ISSCC Acceptance

Jan Van der Spiegel and Kenneth C. Smith


PEOPLE


of the approach you introduced earlier. Focus on thekey ideas, and build up your arguments incremental-ly. It is always helpful to use a figure or diagram toillustrate your approach. Preferably show a circuitschematic, and explain briefly how the circuit works,and what is new about it. It is recommended that youinclude a die photograph, giving the dimensions ofthe chip and the technology that was used.

Measurement results are essential! Include meas-urements of the fabricated chip, and not just simula-tions. If you use simulation results, make it clear whathas been simulated, and what has been physicallymeasured on-chip. Explain briefly what measure-ments were done, and how. For power consumptionand area measurement, state clearly what blocks areincluded (or omitted). Show the results on a graph,but summarize critical aspects in table format to high-light the specifications and performance metrics. Beprecise and quantitative, and compare measuredresults against stated requirements or prior art. Ifappropriate, provide a figure-of-merit. Ideally, compareyour results with those reported in relevant previouslypublished ISSCC papers or other publications in the lit-erature. Be straightforward in making the comparisons,and do not ignore bad results; discuss and explain anyshortcomings, rather than ignoring them.

The ConclusionsThe last paragraph or two should summarize all yourimportant results, to give the reviewers a completepicture of the system/circuit and to convince them ofthe technical quality and accuracy of the results. Sum-marize briefly how the results advance the state-of-the-art.

Overall GuidelinesThe TitleThe title should be descriptive, giving a good ideaabout the paper’s contents and the achievements pre-sented. Do not make the title too broad or general,since it may appear to be a marketing or tutorialpaper. An example of a title that captures some of thekey aspects of a paper is “An 800mW 10Gb/s Ether-net Transceiver in 0.13µm CMOS.” This title is muchmore descriptive than “A novel high-speed CMOStransceiver.”

The AbstractEach paper must have an Abstract of at most 325 char-acters that captures the key elements of the paper.The Abstract should be focused and factual, and pro-vide a complete and quantified description of thework, including concrete performance data.

Don’tsMinimize theory in the body of the paper. If theory isessential, summarize the results and refer to othersources of such material in one or two references.Correspondingly, refrain from giving too many equa-

tions. Your paper is not a Ph.D. thesis: only relevantequations are needed, if any! If an equation is pre-sented, explain it briefly, but thoroughly. Similarly, donot write a tutorial paper. ISSCC submissions mustdisclose innovation concisely. Remember you haveonly 1100 words!

Unsupported expressions such as “Fastest,” “Small-est,” “Lowest power consumption,” etc. should beavoided. It is much more helpful to be quantitative,precise, and explicit in making comparisons with ear-lier work.

A Common Reason for RejectionA dominant reason why a paper is rejected is thelack of clear evidence of what is novel in the work,and the extent to which it advances the state-of-the-art. Successful submissions contain specific newresults with sufficient detail and data to be under-stood, and schematics and measured results for keycircuits, where appropriate. Correspondingly, if thepaper is not written well, or written so that thereviewers cannot evaluate it, the chances of accept-ance are going to be low. Thus, it is essential to payattention to the quality of the write-up, asexplained above.

Another reason for rejection is that the paper givesonly simulations, or deals mainly with modeling, andhas no hardware. Also, rejection is inevitable if a sub-stantial part of the work has been published beforethe candidate upcoming ISSCC (“prepublication”).

SummaryThe most successful submissions to ISSCC are thosethat emphasize innovation and advancement of thestate-of-the-art in solid-state circuits and systems-on-a-chip. Such submissions contain specific new resultswith sufficient detail and data to be easily under-stood, and with schematics and measured results forkey circuits.

DisclaimerIt should be understood that this article merely pro-vides suggestions and guidelines intended to improvethe quality of your paper submission. Corresponding-ly, there is no guarantee that a paper, however close-ly conforming to these suggestions and guidelines,will be accepted.

AcknowledgmentsThe authors acknowledge contributions and sugges-tions from Laura Fujino, Qiuting Huang, ShahriarMirabbasi, Sreedhar Natarajan, Willy Sansen, AlbertTheuwissen, and Chorng-Kuang Wang.

Resources: ISSCC Website: www.isscc.org/isscc“How to Write a Paper for ISSCC” is available as a

flash presentation, prepared for students at A-SSCC inNovember, 2006, at sscs.org/Chapters/07ChptrL-nch/07FebCafe.htm



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Atotal of 112 engineers registered for the firstSSCS-Benelux Microelectronics Symposiumon 14 March. Organized by the IEEE Student

Branch (SB) Leuven and the SSCS Benelux chapterto enhance the link between electrical engineeringstudents and local industry, this year’s theme was“Smart Power” -- a recurring topic in almost all mod-ern electronic systems and of great media interestwith regard to conserving the world’s scarce energyresources. The event, sponsored by AMIS, includeda total of five speakers who covered various aspectsof micro-electronic circuits.• Liesbet Van der Perre (IMEC) gave an overview of

recent achievements in the field of energy-efficientwireless communication that exploit the flexibilityoffered in software-defined radio (SDR) systems.

• Jan Sevenhans (AMIS) covered the use by two inter-national companies of high-voltage silicon tech-nologies in automotive and telecom applications.

• Dirk Leman (Melexis) showed advanced electronicsolutions in car engine control and tire pressuremonitoring systems.

• Patricia Van Reeth (AnSem) reported on the ultra-low-power transceiver circuits devised by start-upcompanies represented at the Symposium and fromthe Katholieke Universiteit for hearing aids and for

wireless sensor network nodes. • Finally, Bram De Muer (ICSense) showed a multi-

purpose, smart power sensor interface IC and itsapplications, such as a pressure sensor.Networking time for all participants was provided

by a closing reception. Plans are in the making for thesecond symposium next year!

SSCS-Benelux and Leuven Student Branch OrganizeFirst Microelectronics SymposiumFocus is “Smart Power” for Conserving Global Resources

Jan Craninckx, IEEE SSCS Benelux chapter chair, [email protected], Cedric Walravens, IEEE SBLeuven chair, [email protected]

The organizers and speakers (from left to right): PatriciaVan Reeth (AnSem), Cedric Walravens (IEEE SB LeuvenChair), Jan Craninckx (SSCS Benelux chapter chair), JanSevenhans (AMIS), Bram De Muer (ICSense) and DirkLeman (Melexis). Missing in this picture; Liesbet Vander Perre (IMEC).

SSCS Distinguished Lecturer Albert Wang VisitsCentral North Carolina

Albert Wang of the Illinois Institute of Technologyand Vice President of the Electron Devices Soci-ety delivered a Distinguished Lecturer seminar to

the EDS/MTT/SSC Joint Chapter at Greensboro, NorthCarolina at Analog Devices on April 20, 2007. Wang washosted by Chapter Co-Chairs Dimitrios Efstathiou andMichael Hughes of Analog Devices, Inc.

Wang’s talk on “Advanced ESD Protection Designfor RF ICs” was well received by the audience ofabout thirty engineers, faculty and students from Ana-log Devices, RF Micro Devices, A&T University(Greensboro, North Carolina) and Greensboro Tech-nical Community College (GTCC).

In an open session following the seminar, thegroup discussed many ESD related issues. This wasone of EDS/MTT/SSC Joint Chapter’s best attendedseminars.

AbstractESD (Electro-Static Discharge) failure becomes a majorIC reliability problem as semiconductor IC technologiescontinue to migrate into the VDSM (very-deep-sub-micron) regime. On-chip ESD protection circuitry

design emerges as a grand challenge to RF/mixed-sig-nal IC designs. Yet traditional trial-and-error approach-es still dominate the ESD design practices, whichbecome increasingly unacceptable to RF/MSIC designs.This lecture discusses various key aspects of ESD pro-tection design including ESD protection principles,mixed-mode ESD design method, RFESD design evalu-ation and ESD design prediction, etc. Practical ESD pro-tection circuit design examples are presented.

Back row from left: Dean Hoegeneyar, Mike Hughes,Abdoul Karim Adboulaziz, Dimitrios Efstathiou, AlbertWang, Swana Muthukrisnan, Iqbal Chaudry. Front rowfrom left: Numan S. Dogan, Tony Ivanov.


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The first Ph.D.-level course on microelectronicsat the University of Pavia, Italy on 1-3 May, 2007attracted more than 40 students. Approximate-

ly 25% came from industry and more than 30% fromother Italian Universities.

Organized in collaboration with the Department ofElectronics of the University of Pavia by the recentlyestablished Italy Chapter of IEEE Solid State CircuitsSociety and supported by the Society’s Chapter Sub-sidy Program, the course initiated a series entitled“Topics on Microelectronics.”

The series seeks to provide wide-ranging coverageof current challenges in the microelectronics world.In each segment, five overview and in-depth lectureson a selected topic by professors and qualifiedexperts from companies or research will ensure thatacademic and industrial approaches to research arerepresented.

The five topics in the first segment were:• “Continuous-time Sigma-Delta Modulators,” by A.

Di Giandomenico - Infineon (Austria)• “Frequency synthesis for wireless radios,” by M.

Conta – GloNav (USA)• “CMOS Buffer Amplifiers,” by R. Castello - Univer-

sity of Pavia (Italy)• “Interface Circuits for Resistive Chemical Sensors,”

by P. Malcovati - University of Pavia (Italy),• “Analysis and Design of Bandgap-Based Voltage

References,” by A. Gola - Infineon (Italy)

The second course in September, 2007 will offer:• “Design of CMOS down-conversion mixers,” by F.

Svelto – University of Pavia (Italy)• “Design of Analog Integrated Circuits under Low-

Noise Constraints,” by P.F. Manfredi – Univ. of. Pisa(Italy)

• “CMOS Charge Pumps,” by G. Torelli – Universityof Pavia (Italy),

• “Sigma-Delta Data-Converters for Telecom,” by F.Maloberti – University of Pavia (Italy),

• “CMOS interfaces for imagers,” by D. Stoppa – ITC-irst (Italy)

SSCS-Italy’s microeletronics Ph.D. program in Paviaevolved in response to the increasing number ofmicroelectronics companies -- Acco, Austrian MicroSys-tems, International Rectifier, Marvell, Maxim, NationalSemiconductor, STMicroelectronics, and others -- thathave recently established design centers in the area.The success of the initiative is due also to the contribu-tion of volunteers Laura Gobbi and Alessandro Cabrini.

IEEE SSCS-Italy will participate in the organization ofnext year’s International Workshop on Advances onAnalog Circuit Design (AACD2008) to be held in Paviaon April, 8-10, 2008 in the same lecture hall whereAlessandro Volta gave his lectures more than 200years ago.

A visit to the museum with the exhibition of theinstruments developed by Alessandro Volta will bepossible.

For further information about the initiatives of theChapter, or to participate in it, contact Andrea Baschi-rotto ([email protected]) or visit the websitewww.microelectronicsevents.com.


Graduate Courses Initiated by SSCS-Italy “Topics on Microelectronics” is First of Series at the University of Pavia

SSCS-Santa Clara Valley: Did You Know That……?By Dan Oprica, Santa Clara Valley IEEE Solid-State Circuits Chapter Programs Chair,[email protected]

• IEEE/SSCS Santa Clara Valley was THE FIRST SOLID-STATE CIRCUITS SOCIETY CHAPTER ESTAB-LISHED IN THE WORLD!

• We had our inaugural meeting shortly after ISSCC in1997; our first speaker was Kenneth Kundert.

• We celebrated our tenth anniversary on 22 March.The featured speaker was Stanford University Pro-fessor Mark Horowitz and the topic of his lecturewas “Rethinking Analog: Digitally Driven AnalogDesign.”

• SCV IS THE MOST NUMEROUS SSCS CHAPTER INTHE WORLD. -- We have about 1600 members, 80Senior Grade; 25 IEEE Fellows, six of them Life Fel-lows; 24 IEEE Life members, two of them SeniorIEEE Life members. -- A prestigious list of “Who iswho in Solid-State”!

• SCV HAS ESTABLISHED WORLD RECORD ATTEN-

DANCE OF ALL IEEE CHAPTERS: over 900 atten-dees in 11 technical meetings in 2004 (almost dou-ble from 466 in 2003). On May 13, 2004 we had 160participants at a lecture by Professor Phillip Allenon “The Practice of Analog IC Design.” During our10 years, we have had many other outstanding lec-tures attended by over 100 participants, such as:– “PLL History: A Personal Viewpoint,” presented

by Dr. Floyd M. Gardner, IEEE Fellow– “Cascaded Noise Shaping for Oversampling A/D

and D/A Conversion,” presented by ProfessorBruce Wooley, our Society Past President, andone of our best supporters.

• For the past 10 years we have held from 8 to 11technical meetings every year, typically on the thirdThursday of each month except for July andDecember, in the National Semiconductor, Building



CHAPTERSE Auditorium, at 2900 Semiconductor Dr. in SantaClara, CA. Refreshments are provided at 6:00 PM.;presentations start at 6:30 p.m. and usually last anhour (longer if necessary) for in depth coverage of thetopic. Attendees can ask questions of the speaker.

The great majority of the presentations are on ourweb site: www.ieee.org/scv/ssc/, one of most visitedIEEE Chapter sites in the world. • For our remarkable activity in 2004 we received the

IEEE Solid-State Circuits Society Outstanding Chap-ter of the Year Award!

• A majority of our Chapter Past Chairs attended our10th anniversary meeting: Jonathan David, JohnMerrill, Lee Colby, Dan Oprica, Sorin Spanoche andEric Hoffman.

• All the members of the 2004 Solid-State CircuitsSociety Outstanding Chapter of the Year Awardwining team were present: Chair Dan Oprica, ViceChair Sorin Spanoche, Treasurer Eric Hoffman, Sec-

retary June Song and Webmaster Perry Chow. • Past lecturers came: Ken Kundert IEEE Fellow, our

first lecturer; Allen Podell, IEEE Life Fellow and lec-turer in our early years (also our future speaker inMay 2007 on “Negative Impedance Converters”);Bhupendra Ahuja, IEEE Fellow; Dr. JayasimhaPrasad; IEEE Fellow and Electron Devices distin-guished lecturer.

• Present also were some of our best supporters:David Su, IEEE Fellow and Professor at StanfordUniversity, who has lectured in person and spokefour more times on SOCs with colleagues from Ath-eros Communications, Dr. Masoud Zargari, Dr.Manolis Terrovitis, Dr. Lalitkumar Nathawad, andDr. Weimin Si; Mr. Stefan Rusu, IEEE Fellow, whohas lectured twice on state of the art microproces-sors; and Mr. Aurangzeb K. Khan, who has lecturedtwice on EDA tools application for SOCs.Our 2007 Chapter officers are: Chair Adrian Gradi-

naru, Vice Chair Kara Poon, Treasurer Mark Hooperand Programs Chair Dan Oprica.

Professor Asad Abidi lectured at National Semiconductoron 19 October, 2006: “Evolution of CMOS Software-Defined Radio Receiver Front-End.”

From left to right: Eric Hoffman, Mark Hooper, Dan Oprica,Professor Asad Abidi, Adrian Gradinaru, Kara Poon.

Razavi Kicks off DL Program in VancouverResve Saleh, SSCS-Vancouver Chapter Chair, [email protected]

In the first of five technical seminars scheduled for2007, Prof. Behzad Razavi of UCLA spoke on “60-GHz RF Transceivers in CMOS: Why and How?” at

SSCS-Vancouver on 5 April. Over 100 people attended,including 63 IEEE members.

Dr. Razavi described the challenges of 60GHz RFdesign in CMOS based on an article he published inthe January 2006 issue of JSSC. He explained that withmultiple antennas and transceivers operating on onechip, and with the enormous analog and digital signalprocessing required for high-rate communications,CMOS technology is essential but such speeds are dif-ficult to reach. In a 0.13um technology, with fT around75GHz, he was able to design a receiver front-endrunning at 60GHz. One interesting comment heoffered was that direct conversion transceivers wouldeventually give way to heterodyne transceivers.“Three issues plague direct conversion at these fre-

quencies: generation, division, and distribution ofoscillator signals. In heterodyne systems, on the otherhand, all three issues are relaxed considerably,” hesaid. A variety of questions were asked by attendeesfrom academia and industry.

It was definitely our most exciting talk to date anda great way to start off the year for the Chapter, whichis celebrating its third year of existence. On June 14,2007 Dr. Ash Parameswaran will deliver a talk on hisresearch in polymer-based MEMS technology. He willpresent examples of various MEMS devices that can beproduced by this novel technology and cover someaspects of microassembly. Dr. Parameswaran is Direc-tor of the Institute of Micromachine and Microfabrica-tion Research at Simon Fraser University. We look for-ward to a large audience for this one as well. Threeother talks are planned for August, September andNovember to round out the year.


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The 2nd RFIT workshop will be held at Rasa Sen-tosa Resort on Sentosa Island in Singapore from9 to 11 December 2007.

The workshop aims at providing a forum forexchanging information on the latest developments inthe areas of RF and mmWave IC design, and integra-tion of wireless systems.

Manuscripts are sought by 24 August on UWB, soft-ware defined radio, Modeling, 3D integration, RFMEMs. LPLV Wireless Systems and ICs, RFID andDVB/DMB tuners.

The workshop is sponsored by the IEEE MTT Soci-ety and the SSCS Singapore Chapter. More details areavailable at www.rfit2007.org.

RFIT Sponsored by SSCS-Singapore on 9 – 11December 2007 Manuscripts Sought for 2nd International Workshop on Radio-Frequency Integration Technology

Yong Ping Xu, National University of Singapore, [email protected]

“From Terahertz Imaging to Telehealth Technologies”at Cambridge University, UK on 19-22 August4th IEEE-EMBS International Summer School and Symposium on Medical Devices andBiosensors (ISSS-MDBS)

The 4th International Summer School and Symposiumon Medical Devices and Biosensors (ISSS-MDBS),sponsored by the IEEE Engineering in Medicine andBiology Society (IEEE-EMBS), will be held at StCatharine’s College, Cambridge University, UK from19-22 August 2007. The theme is “From TerahertzImaging to Telehealth Technologies.” Terahertz imag-ing and spectroscopy techniques have progressedrapidly over the last decade and numerous medicalapplications are currently being explored. This com-bined summer school and symposium is intended topromote awareness of terahertz technology in themedical field and to inform terahertz scientists of thelatest advancements in medical devices and tele-

health, with a view to integrating terahertz technolo-gy into medical devices in the future. In the sympo-sium sessions, invited and contributed talks willdescribe original work in research and development.There will also be poster sessions of additional con-tributed work. The summer school sessions willinclude informative tutorials about the main topics ofinterest (listed below) and laboratory tours will beheld on 22nd August giving scientists from all back-grounds further opportunities to broaden their knowl-edge of medical science. This event directly precedesthe 29th Annual International Conference of IEEE-EMBS in Lyon (23-26 August) themed “Sciences andTechnologies for Health.”

Terahertz Topics: Related Topics: Telehealth Topics:Imaging techniques NIR and visible techniques Wearable medical devicesSpectroscopy techniques MRI Body sensor networks Medical applications Ultrasound Low-cost healthcare equipmentPharmaceutical applications Standards for healthcare devices

Textile electronics

Enquiries: Dr. E. Pickwell-MacPherson ([email protected]) Tel: + 852 2609-8260 Prof. Y.T. Zhang ([email protected]) Tel: + 852 2609-8459



CONFERENCES

Moderator Philip Wong set the entertainingtone of the discussion by insisting thataccording to current estimates there were as

many as a hundred MOS transistors for every ant onour planet, and wondering where this bounty oftransistors is leading us. He posed to the panelistsa laundry list of questions ranging from the physicallimits of scaling, the effects on circuit design, thelikelihood of architectural innovations, new materi-als, or techniques such as 3D chip stacking extend-ing the life of scaling, and the applications thatwould provide the economic impetus to furtherscaling.

The panel was interestingly split on the questionof CMOS scaling. While panelists from industry(Won-Sung Lee, Kiyoo Itoh, Hans Stork, and MarkBohr) pointed to limits imposed by the economicsof reducing variability, leakage, and other prob-lems associated with scaling as early as the 32nmnode, Prof. James Meindl sounded a strong note ofoptimism by painting the challenges brought byscaling as an opportunity to launch a new cycle ofinnovation and major new breakthroughs. In anapparent bid to bring controversy to the proceed-ings, Prof. Brodersen insisted that CMOS scalinghas already failed. However, it was refreshing tohear most of the panelists express confidence,albeit guarded, in the engineering community’sability to overcome the expected challenges in pro-

gressing towards the fundamental limits of inte-grated electronics.

As the evening progressed, there was near una-nimity in the panelists’ opinion that circuit design willchange, if it is not already doing so, to accommodatevariability and leakage. They also agreed that therewould be no dearth of applications to justify the eco-nomic costs of extending scaling even as their appli-cations of choice were different, ranging from robot-ics and transportation to health and biology-relatedapplications.

The eagerly awaited spark of controversy had towait until the moderator steered the discussiontowards architectural innovations and techniquessuch as 3D stacking and their ability to extend the lifeof CMOS scaling.

Prof. Meindl’s faith in 3D chip stacking and exot-ic “trimodal I/O” approaches involving electrical,optical, and fluidic interfaces for data communica-tion and heat removal needs was met by general dis-belief from the rest of the panel. Prof. Brodersenrepeatedly questioned the viability of the multi-coreprocessor architectures without addressing software,compiler, and other programmability issues. How-ever, the rest of the panel, particularly Intel’s MarkBohr, did not seem interested in taking the bait.Prof. Brodersen went on to argue that embeddedsystems that do not suffer from the software legacyissues of today’s computing platforms would providethe ideal developing ground for radically differentarchitectural approaches. Some of us in the audi-ence were disappointed by the other panelists’seeming reluctance to rebut Brodersen’s arguments.

Although the discussion was not as controversialas the audience would have liked, it was surelyentertaining, as attested by the particularly long inter-active Q&A session with the panel. The value of theevening’s discussions may perhaps be summarizedbest by the panelists’ unanimous “Yeah” to the ques-tion “Would you serve on the same panel in fiveyears time?”

At the end of a day of conference sessions, the“Ultimate Limits of Integrated Electronics” panel wasentertaining, informative, and well attended, withpeople filling up the large hall late into the night. Thetopic was of immediate import, and the speakers ofacknowledged wisdom.

ISSCC 2007 Panel Review: The Ultimate Limits ofIntegrated ElectronicsSudhakar Pamarti, UCLA, [email protected]

“There are as many as one hundred MOS transistors forevery ant on our planet.” H.-S. Philip Wong


CONFERENCES


The 16th annual Advances on Analog CircuitDesign (AACD) workshop was held on 27 - 29March, 2007 in the Hotel Thermae Palace in

Oostende, Belgium. Each day of the program included six tutorial lec-

tures, ample discussion time, and a panel discussioneach evening that explored the topic of the day, withlively audience interaction.

The AACD keynote by Eric Beyne (IMEC) on “Het-erogeneous integration of passive components for therealization of RF-System-in-Packages,” offered a

visionary view of packaging effects on the differentapplications, and commentary on relevant topics cov-ered by the AACD 2007 workshop.

17 papers were published in a full digest that will beavailable as a book later this year. More information maybe found at www.aacd.ws and [email protected].

AACD 2008 will be organized in Italy next year byProf. Andrea Baschirotto, Chair of SSCS-Italy.

Europe’s Analog Design Experts Convened at 16thAACD WorkshopJan Sevenhans, SSCS Region 8 Representative,[email protected]; Jan Craninckx, SSCSBenelux chapter chair, [email protected]

The Chairmen and local organizers of AACD 2007, from leftto right : Michiel Steyaert, KU Leuven, Belgium; HermanCasier, AMI Semiconductor, Oudenaerde, Belgium; ArthurRoermund, TU Eindhoven, the Netherlands; Jan Seven-hans, AMI Semiconductor, Vilvoorde, Belgium.

A group of 56 gathered to hear papers on automotive sen-sors with integrated compass, smart cameras on chip,inductive position sensors and protection and diagnosisapplications; power amplifiers for linear broadband com-munications, power combining techniques, switched RFPA’s, USB drivers and xDSL line drivers in nm technologies;very high frequency radio links, with building blocks formm-waves in CMOS, analog/RF design concepts in THzapplications, and SiGe circuits in the 80-160GHz range.

2007 IEEE Custom Integrated Circuits Conference(CICC 07) in San JoseShowcase for Circuit Design in the Heart of Silicon Valley on 16-19 September

What are the latest trends and innovative cir-cuit techniques for analog and digital ICs?Where are the major research universities

and industry laboratories going with FinFETs, ultra-wide band circuits, image sensors, digital signalprocessors, and high speed transceivers? How are cir-cuit designers solving the major issues today ofpower, variation, noise, jitter, GHz performance, sys-tem-on-chip integration, and limits to CMOS scaling?

The Custom Integrated Circuits Conference(CICC) addresses these questions in 2007, its 29thyear, at the DoubleTree Hotel in San Jose, CA, 16-19September.

Conveniently located in the heart of Silicon Valley,the conference is sponsored by the IEEE Solid-StateCircuits Society and technically co-sponsored by theIEEE Electron Devices Society. Here are some of thehighlights of 2007 CICC:

Sunday, September 16: Three full-day educational sessions taught by recog-nized industry experts:

• High-Speed Serial IO Design Techniques• Mixed-Signal SOC Design Methodology• Sub-1-Volt Analog Converter Design

Monday, September 17- Wednesday, September 19: Keynote address, “The Wireless Revo-lution Continues: Can TechnologyKeep Up with the Challenge?” by Dr.Bill Krenik, CTO of Wireless TerminalBusiness Unit of Texas Instruments.(Monday)

Panel discussion, “Are analogdesigners hopeless at scaling? Will dig-ital designers eat their lunch at 45nm

and below?” by leading experts from industry and

Bill Krenik



CONFERENCES

academia. (Monday)Luncheon presentation, “Growing up with Batteries

and Wires,” – humorous recollections from the daysof electric telephones and vacuum tubes, by PaulBrokaw, IEEE Fellow, Analog Devices Fellow inven-tor of the “Brokaw Bandgap”. (Tuesday)

Poster presentations, demonstrations, and vendorexhibits. (Monday and Tuesday)

Over 160 technical papers and invited presenta-

tions. (Monday-Wednesday) The CICC Technical Pro-gram Committee is especially enthusiastic about thesepapers: • Future Microprocessor Interfaces: Analysis, Design

and Optimization• Revolutionary NanoSilicon Ancillary Technologies

for Ultimate Performance Gigascale Systems • Towards a sub-2.5V, 100-Gb/s Serial Transceiver• A 0.25um 0.92mW per Mb/s Viterbi Decoder Fea-

turing Resonant Clocking for Ultra-Low-Power54Mb/s WLAN Communication

• A low power, high performance MIMO/diversitydirect conversion transceiver IC for WiBro/WiMAX(802.16e) in BiCMOS

• A 65uW, 1.9 GHz RF to Digital Baseband WakeupReceiver for Wireless Sensor Networks

• A Single-Chip UHF RFID Reader in 0.18 um CMOS• Time-Variant Characterization and Compensation of

Wideband CircuitsAdditional information about the conference

including the complete advance program and regis-tration form is available on the CICC website:http://www.ieee-cicc.org

Inquiries can be made to the CICC ConferenceManager, Melissa Widerkehr, Tel: (301) 527-0900/101.Email: [email protected].

Poster presentation and vendor exhibit, 2006 CICC

19th Hot Chips Conference Meets on 19-21 August at Stanford University Three days of Leading-Edge, Real-World Designs forHigh-performance Chips and TechnologiesDon Draper, [email protected], John Sell,[email protected], Allen Baum, [email protected]

Hot Chips, a symposium of the Technical Committeeon Microprocessors and Microcomputers of IEEE Com-puter Society and the IEEE Solid-State Circuits Society,will convene at Stanford University’s Memorial Audito-rium on 19-21 August. It is the primary forum for stateof the art designs and up-to-the-minute developmentsin high-performance chips, software, and systems.

DAY ONE A mind-expanding keynote address onMonday mid-morning will be present-ed by computer scientist and Hugo-award-winning science fiction writerVernor Vinge, who has speculated onpotential future interactions betweenmachines and humans in novels TrueNames and Rainbows End.

“What’s next beyond CMOS?,” aMonday evening panel promising lively debate, willfeature John Kubiatowicz of UC Berkeley, Mike May-berry of Intel, Mark Horowitz of Stanford, GhavamShahadi of IBM, and Stan Williams of HP.

Session 1 IBM Power6™An extensive look at the ultra-fast IBM Power6, address-ing its fault-tolerant design, system performance scalingand IBM’s elastic interface implementation.

Session 2 Multi-Core and Parallelism ISession 3 Multi-Core and Parallelism II

The NVIDIA GeForce 8800 chip, its architecture andan analysis of using it to execute non-graphics appli-cations within the CUDA(TM) parallel programmingenvironment. AMD’s Radeon R600 GPU with its unified shaderarchitecture, Intel’s 80-core teraflop research proces-sor, the TRIPS processor from the University ofTexas, Austin and the embedded multi-core Tileprocessor for multi-media from Tilera Corporation.

Session 4 Embedded and VideoThe SH-X3 SuperH multi-core processor from Rene-sas, an HD image processor from Texas Instrumentsand an H.264/AVC Codec chip set from NTT.

DAY TWOIn an after lunch keynote address on Tuesday, AMDCTO Phil Hester will reveal AMD’s future directionsin “Multi-Core and Beyond: Evolving the X86Architecture.”

To wind up the conference, “Big Iron” will describeSun Microsystem’s Victoria Falls highly-threadedprocessor with multi-chip scaling and the next-gener-ation mainframe microprocessor from IBM. Session 5 Technology and Software Directions

Multi-terabit switch fabrics using proximity commu-nication from Sun, thyrister-based memory from T-RAM Semiconductor and the Raksha software secu-rity architecture from Stanford.

Session 6 WirelessA 60GHz 4Gbps uncompressed 1080p transceiver by


CONFERENCES


SiBEAM and a 2x2 MIMO baseband for 802.11nlocal-area networking by Broadcom.

Session 7 NetworkingA packet processing chip set from Cisco, a 50Gbpscombined network processor and traffic managerfrom Bay Microsystems, a system on a Chip withintegrated accelerators and a low-latency, high-bandwidth switch/router chip from Fulcrum.

Session 8 Mobile PC Processors and ChipsetsThe power management implementation in theIntel 45nm Penryn Core™2 Duo microarchitecture,the next generation mobile X86 processor fromAMD, and the nForce 6801 and 680 chipsets fromNVIDIA.

Session 9 Big IronMulti-terabit switch fabrics using proximity commu-nication from Sun, thyrister-based memory from T-

RAM Semiconductor and the Raksha software secu-rity architecture from Stanford.

Sunday Tutorials “Approaches to System Design for the Working Engi-neer” will explore the use of FPGAs, ASICs, ASSPs atthe system design level. The second topic in themorning will be “Exploiting Chip-Level ProcessorHeterogeneity through Fine-Grained ReconfigurableInteractions.”

The afternoon tutorial will explore the data centerissues of increasing power consumption and heatremoval in “Enterprise Power and Cooling: A Chip-to-Data Center Perspective.”

For further information and to register, go to theHot Chips web page: http://www.hotchips.org/hc19/main_page.htm

ESSCIRC: The European Forum for Solid-StateCircuits on 11-13 September Meeting with ESSDERC Sister Conference in Munich

Due to the increasing level of integration for SoC(system-on-chip) design stemming fromadvances in silicon technology, technologists,

device experts and circuit and system designers mustcollaborate as never before. Therefore, this year’s ESS-CIRC/ESSDERC conference at the Technical Universityin Munich will share plenary keynote presentations andjoint sessions, while keeping separate Technical Pro-grams. Cosponsored by the IEEE SSCS, ESSCIRC pro-vides an annual European forum for the presentationand discussion of recent advances in solid-state circuits.

Joint ESSCIRC/ESSDERC Plenary Talks Distinguished invited speakers will discuss issues ofinterest to attendees at both conferences:• W. Ziebart (Infineon Technologies) “Technical and

Economical Trends in Microelectronics”• DeHon (University of Pennsylvania) “Nanoelectron-

ic Architectures”• S. Nassif (IBM) “Holistic Coupling of Manufacturing

and Design“• A. Theuwissen (DALSA) “CMOS Imagers – Status,

Trends, and Future Perspectives”• P. Fromherz (MPI for Biochemistry) “Joining Micro-

electronics with Microionics: Nerve Cells and BrainTissue on Semiconductor Chips”

• K. Ishimaru (Toshiba) “45/32 nm CMOS”Attendees registered for either conference are encour-aged to attend the scheduled parallel sessions.

• Sensors and ImagersTechnology; mixed signal design; algorithms.

• Yield and ReliabilityYield and reliability related technology develop-ment, characterization, and modeling; design formanufacturability.

Plenary Talks at ESSCIRCThree invited speakers will address issues focused onsolid-state circuits of specific interest to the integratedcircuit design community:• K. Makinwa (TU Delft) “Smart Sensor Design: The

Art of Compensation and Cancellation”• K. Itoh (Hitachi) “Low-Voltage Limitation of Future

CMOS LSIs”• P. Kinget (Columbia University) “Sub-1-V Analog

Integrated Circuits”

ESSCIRC papers will focus on the following:

Analog CircuitsAmplifiers; continuous-time & discrete-time filters;comparators; multipliers; voltage references; switched-capacitor circuits.

Mixed Signal Circuits and SystemsNyquist-rate and oversampled A/D and D/A convert-ers; sample-and-hold circuits; A/D and D/A convertercalibration circuits.

RF CircuitsRF/IF/baseband circuits including LNAs; mixers; IFamplifiers; power amplifiers; power detectors; activeantennas; modulators; demodulators; VCOs; frequen-cy dividers; frequency synthesizers; PLLs.

Wireless and Wireline Communication CircuitsReceivers/transmitters/transceivers for wireless sys-tems, base stations and handsets; TV/radio/satellite;wireless sensor networks.

Digital Signal Processing and ArithmeticDSPs and DSP kernels, signal processing, and arith-metic building blocks.

Digital and Memory CircuitsDigital circuit techniques; I/O and interchip commu-



CONFERENCESnication; reconfigurable digital circuits; clocking;memories; microprocessors.

NanoelectronicsDigital, analog and mixed signal circuits using emerg-ing devices such as multi-gate MOSFETs (Double-Gate MOSFETs; FinFETs, Triple-Gate MOSFETs),nanowires/nanotubes and quantum devices.

A Tutorial Day on Monday, 10 September and aWorkshop Day, on Friday 14 September will precedeand follow the conference.

Tutorials• Industrialization of MEMS• Technologies for 45nm and 32nm CMOS

• SDR-Concepts for Multi-Standard Mobile Phones • Design for Manufacturing: “Variability in UDSM

Technologies’’

Workshops• Nanoscale CMOS and Beyond-CMOS Nanodevices• Compact Modeling for Nano CMOS/SOI Technologies• International Workshop on Emerging non volatile

memories• Controlling leakage power in nanometer CMOS:

Technology meets design• Analytical Techniques for Semiconductor Materials

and Process Characterization VMore information is available at the conference web-site: www.esscirc2007.org.

2007 IEEE Bipolar/BiCMOS Circuits and TechnologyMeeting (BCTM) in Boston, September 30 to October 2 Dr. Tak H. Ning to Deliver Keynote Address

Yih-Feng Chyan, BCTM General Chair, [email protected]

You want to be at the 2007 IEEE Bipolar/BiCMOSCircuits and Technology Meeting (BCTM) inBoston if you're interested in leading edge

processes, devices, and circuits used in state-of-the-arttelecommunication systems and power control systems.Bipolar and BiCMOS technologies, particularly SiGeHBT BiCMOS technologies, continue to play a key rolein these systems. BCTM is cosponsored by the IEEESSCS and ED Societies

The 2007 IEEE Bipolar/BiCMOS Circuits and Technol-ogy Meeting (BCTM) will be held September 30 to Octo-ber 2, 2007 2 at the Boston Marriott Long Wharf Hotel inBoston, Massachusetts (marriott.com/hotels/travel/boslw-boston-marriott-long-wharf).

Keynote Address by Dr. Tak H. NingWe are fortunate to have Dr. Tak H.Ning for the keynote. Dr. Ning and hiscolleagues invented and developed thepolysilicon-emitter self-aligned bipolartransistor, which is the basis of modernbipolar transistor technology. Don’t

miss this opportunity to hear Dr. Ning’s presentationon “Historical Development of Devices Based onBipolar Phenomena.”

Short Course on Bipolar IC Design This short course features three renowned experts on“Bipolar IC Design Beyond Handsets and Into Mil-limeter Waves: Challenges and Opportunities forPower Amplifier and mm-wave Transceiver ICDesign.” Invited speakers include:• “Bipolar-based Power Amplifier design Beyond

Handsets and into MM-wave integrated circuits:Design, Modeling, Characterization, Packaging,Reliability” Larry Larson (UCSD, USA)

• “MM-wave SiGe BiCMOS circuit design for automo-tive application” Herbert Knapp (Infineon, Germany)

• “MM-wave SiGe BiCMOS circuit design for mm-wave application” Brian Floyd (IBM, USA)

The BCTM Banquet will be held on Mondayevening at the New England Aquarium, located atLong Wharf. Following the conference on Wednes-day, there will be a workshop on compact modelingfor RF/Microwave applications organized by TU Delft.

Two days of technical paper sessions including aspecial session on Emerging Technologies, a lunch-eon with guest speaker, exhibits, and the eveningbanquet round out the program. Booths feature thelatest products of interest to the bipolar community.The banquet will be held at Boston’s New EnglandAquarium featuring the 4-story tall Giant Ocean Tank,a 200,000 gallon ocean habitat coral reef home to sea-turtles, sharks, moray eels and over 50 species of trop-ical fish. We look forward to you joining us and con-necting with your colleagues at this year’s BCTM. Findfull details and registration for the conference on theconference web page (www.ieee-bctm.org).

Boston’s harbor front is the city’s center for explorationby land and by sea. Follow the red brick cobblestones ofthe Freedom Trail to historic sites of the American Revo-lution. Pass through Christopher Columbus Park to theNorth End, once the gateway for newcomers to NewEngland and now the location of spirited cafes andrestaurant gems. At the Faneuil Hall Marketplace, youwill find what you are looking for in the variety of shopsand pubs located in a building characteristic of Boston’s18th century architecture. The conference will be heldduring the fall season when the autumn leaves begin tochange and the city is energized by interactions betweenstudents, researchers, and innovative industry and com-merce. For details on local attractions and activities andto learn more about the city, please follow this link to thecity of Boston’s visitor web guide: (www.cityofboston.gov/visitors/thingstodo.asp).

See you in Boston!


CONFERENCES


We cordially invite you to the 2007 Com-pound Semiconductor IC Symposium onSunday – Wednesday, October 14 – 17th in

beautiful Portland, Oregon. The high-performancewireless and high-speed digital communications mar-kets are thriving due to impressive strides in newmaterials and devices, greater integration levels, novelcircuit implementations, and ever-changing systemspartitions.

Over the last 29 years the Compound Semiconduc-tor IC Symposium (CSICS – formerly named the GaAsIC Symposium) has been and continues to be animportant international forum in which advances insemiconductor circuit and device technology are pre-sented, debated, and discussed. The scope of theSymposium encompasses devices and circuits inGaAs, SiGe, InP, GaN, and InSb as well as targetingthe fields of RF/mm-Wave CMOS and high-speed dig-ital CMOS to provide a truly comprehensive confer-ence. This is the ideal forum for presentation of thelatest results in high-speed digital, analog,microwave/millimeter wave, mixed mode, and opto-electronic integrated circuits.

This year’s 2007 CSIC Symposium is comprised of afull three-day technical program with two short cours-es, a primer course, and a technology exhibition.

The technical program consists of approximately 60high quality state-of-the-art technical papers, fourpanel sessions, two Short Courses on “CompoundSemiconductor Devices and Integrated Circuits forMillimeter Wave Imaging” and “Compound Semicon-ductor Power Amplifiers” and an Industry Exhibit. TheSymposium will also offer the popular annual intro-ductory level Primer Course on “Basics of CompoundSemiconductor ICs.” This year, the Symposium willfeature approximately 15 invited papers on a widerange of important topics encompassing device engi-neering to circuit application using advanced com-

pound and other related semiconductor technologies.In addition, the Symposium will continue the traditionof including important papers on “late breakingnews.”

On Monday and Tuesday, the technology exhibi-tion will feature informative and interesting displayswith corporate representatives on hand. The list ofexhibitors can be found in the CSICS advance pro-gram which will be published and distributed in lateJune.

Several social events complement the Symposium,including the Sunday Evening CSICS Opening Recep-tion, the Monday CSICS Exhibition Opening Recep-tion, the CSICS Tuesday evening Theme Party to beheld at McMenamins Pub and Breweries Crystal Ball-room, and the CSICS Exhibition Luncheon on Tues-day. The Theme Party will include entertainment anda tasting of locally produced Oregon wine and beer.A breakfast will also be served on Monday, Tuesday,and Wednesday

Proclaimed North America’s “Best Big City” byMoney magazine, Portland exhibits unmatched natu-ral beauty as well as a wealth of opportunities forleisure, sports, shopping, and outdoor activities. Theconference downtown location offers easy access tothe vibrant Pearl District with destination restaurants,art galleries, and shopping. While you’re in Portland,be sure to enjoy the scenic beauty of the ColumbiaRiver Gorge, enjoy the hike to Multnomah Falls anddrive the Historic Columbia River Highway. Otherlocal attractions include Mt. Hood, the WillametteRiver, the rose gardens, the Japanese garden, the Ore-gon Coast, and the wine country.

For registration and further information please visitthe CSICS website at www.csics.org. Further ques-tions may be addressed to the Symposium TechnicalProgram Chair: William Peatman, Ph: +1-908-668-5000ext. 5842, Email: [email protected]

IEEE Compound Semiconductor IC SymposiumMeets in Portland CSICS 2007 on 14-17 October



SSCS-NEWS

The SSCS Nominations Committee hasannounced a slate of eight candidates for thefive available positions in the 2007 AdCom elec-

tions. Terri Fiez, Bill Bidermann, and Mehmet Soyuerare incumbents. Tohru Furuyama, Venu Gopinathan,Tadahiro Kuroda, Bram Nauta, and Jan Sevenhans arenew candidates. Additional nominees may be addedthrough a petition process that is described below.

The AdCom is the governing body of the Solid-StateCircuits Society. It oversees conferences, publications,educational efforts, chapters, finances and other areas rel-evant to the Society’s activities. Elected AdCom membersserve three-year terms, which are staggered so there arealways some experienced and some new members. Theballot is mailed to eligible voting members in the fall.

Process to Become a Petition Candidate for AdComInterested society members can get on the AdComelection slate through a petition process managed bythe IEEE Corporate Office. To begin this process,notify the SSCS Executive Office by email([email protected]) no later than August 1st andinclude a statement verifying the nominee’s agree-ment to be a candidate. Self-petitioning is acceptable.Once a petitioner’s eligibility is verified, he/she isposted on the petition site until September 1, whenthe petition process closes.

The number of signatures needed to qualify for the2007 election slate is defined by IEEE Bylaw I-308.16 as2% of SSCS voting members as of 31 December, 2006,or 227 signatures; signatures will be verified during thepetition process (additional signatures above the mini-mum are recommended to provide a safety factor).Any voting member of the Society may sign such a peti-tion in either of two ways: 1) via a link to the petitionsite provided on the Society’s home page<www.sscs.org>, or 2) with an original signature on ahard copy petition.

There is no official IEEE hard copy petition formfor society elections. Each petition must include:• the name of the candidate• the title of the position the candidate is running for

For each person signing the petition:• name (printed)• IEEE member number• signature

Hard copy petitions must be received by the SSCSExecutive office by 1 September to be entered intothe IEEE petition system.

The CandidatesWilliam R. Bidermann received his B.S.and M.S. degrees in Electrical Engineeringand Computer Science from the Massa-chusetts Institute of Technology in 1978.He is currently President of BK Associates,a Silicon Valley consulting firm and has

recently been involved in the display industry, devel-oping correcting drivers for AMOLED displays forNuelight, Inc. as well as dynamic-range CMOS imagesensors for Pixim, Inc. He managed the AdvancedDevelopment Group at DEC, which produced a self-contained liquid-nitrogen-cooled computer systemand the groundbreaking Alpha microprocessor. Overthe past 20 years, Mr. Bidermann contributed to thefirst uVAX microprocessors, managed the first SPARCV9 implementation at HaL Computers, and led thedevelopment of a novel media-processor at Chromat-ic Research. He began his career at HP Labs, where hedesigned dynamic RAMs and EEPROM devices.

Mr. Bidermann is the Treasurer of the ExecutiveCommittee of the Symposia on VLSI Circuits andTechnology and has served as its General Chair(‘99–‘00) and Program Chair (‘97–‘98). He has been onthe VLSI Symposia Program Committee since 1993and has twice been a member of the ISSCC ProgramCommittee, serving currently on its Technical Direc-tions subcommittee. He has edited several special edi-tions of the IEEE Journal of Solid-State Circuits andhas been a member of the SSCS AdCom since 2005.

Terri S. Fiez received the B.S. and M.S.in Electrical Engineering in 1984 and1985, respectively, from the University ofIdaho, Moscow. In 1990, she receivedthe Ph.D. degree in Electrical and Com-puter Engineering from Oregon State

University, Corvallis. From 1985 to 1987 and in 1988she worked at Hewlett-Packard Corp. in Boise andCorvallis, respectively.

In 1990, Dr. Fiez joined Washington State University asan assistant professor and became an associate professorin 1996. In the fall of 1999, she joined the Departmentof Electrical and Computer Engineering at Oregon StateUniversity as Professor and department head andbecame the Director of the School of Electrical Engineer-ing and Computer Science in 2003. She has served onthe committees of the IEEE International Solid-State Cir-cuits Conference, IEEE Custom Integrated Circuits Con-ference, and ISCAS, and was a guest editor of the Jour-nal of Solid-State Circuits. Dr. Fiez was awarded the NSFYoung Investigator Award, the Solid-State Circuits SocietyPredoctoral Fellowship, and the 2006 IEEE EducationActivities Board Innovative Education Award. Herresearch interests are the design of high performanceanalog signal processing building blocks, simulation andmodeling of substrate coupling effects in mixed-signalICs, and innovative engineering education approaches.

Tohru Furuyama received the B.S.degree from the University of Tokyo,Japan in 1975, the M.S. degree from Cor-nell University, Ithaca, NY, in 1984 andthe Ph.D. degree from the University ofTokyo in 1988. Since 1975 he has been

Eight Candidates Vie for Five SSCS AdComPositions for 2008-2010


SSCS-NEWS


with Toshiba Corporation, where he developed sev-eral commodity DRAM’s and the first Rambus DRAM.He also led one of the first embedded DRAM projectsfor graphics application LSI’s. From 1994 to 1996 hewas the 64Mb DRAM design manager for the Toshi-ba/IBM/Siemens joint DRAM development project inBurlington, VT. Since 2002, he has been responsiblefor various R&D activities; advanced CMOS technolo-gies, NAND flash memories, embedded memories,novel memories, embedded processors (MeP: Toshibaproprietary Media embedded Processor), digitalmedia SoC’s and related softwares as a general man-ager of the Center for Semiconductor Research &Development.

r. Furuyama is presently the Japan Chapter Chair ofthe IEEE Solid-State Circuits Society. He has served onthe Technical Program Committees of the IEEE Inter-national Solid-State Circuits Conference (ISSCC) andIEEE International Test Conference (ITC). He will bethe Technical Program Committee Chair of the 2009IEEE Asian Solid State Circuits Conference (A-SSCC).He has authored and co-authored more than 40 jour-nal and conference papers and holds over 70 U.S.patents. He is an IEEE Fellow for contributions to highspeed dynamic random access memory (DRAM)design and technologies.

Venu Gopinathan was born in India in1963. He received the B.Tech. Degree inElectronics from the Indian Institute ofTechnology, Madras, India in 1986. In 1990he received the Ph.D. from Columbia Uni-versity, NY in the field of high-speed con-

tinuous-time filters.In 1990 he joined the SC Research group of Texas

Instruments, Dallas where he worked on high-speedCMOS analog circuits (A/D converters filters, etc.) foradvanced hard-disk drive read-channels. He latermoved to New Jersey and co-founded the design cen-ter for TI Research in New Jersey. Between 1997 and1999, he worked at Bell Labs’ Circuits Research Lab inMurray Hill, NJ.

In 2000, he moved to Broadcom Corporation, andco-developed nonlinear equalizers for optical disper-sion compensation over a period of four years. Healso led the high-speed serial communications groupat Broadcom during the same period. In 2004 hemoved to Texas Instruments, Bangalore R&D Centerwhere he is the Director of the Wireless SolutionsGroup, in charge of delivering Bluetooth, WLAN, DTVand GPS chips.

From 1996 to 1999, he served as an adjunct associ-ate professor at Columbia University teaching courseson analog IC’s and high-speed data converters. Healso served as a guest editor of IEEE JSSC for the Ana-log Special issue of December, 2000 and the issues ofMarch 1995 and March 1996.

He has been a member of the Data Converter tech-nical program subcommittee of ISSCC since 1999, andwas awarded “best panel organizer” in 2001 for “Arestartups killing Innovation”. He was on the CICCTechnical Program Committee from 1999 to 2002,

chairing the Analog Subcommittee for the last twoyears. He has authored several papers in journals andconferences and holds 14 granted US patents with fivemore pending. He has lectured in a short-course atISSCC 2004 and other venues.

Tadahiro Kuroda received the Ph.D.degree in electrical engineering from theUniversity of Tokyo in 1999. In 1982, hejoined Toshiba Corporation, where hedesigned CMOS SRAMs, gate arrays andstandard cells. From 1988 to 1990 he was

a Visiting Scholar at the University of California,Berkeley, where he conducted research in the field ofVLSI CAD. In 1990, he returned to Toshiba forresearch and development of BiCMOS ASICs, ECLgate arrays, high-speed and low-power CMOS LSIs formultimedia and mobile applications. He developed aVariable Threshold-voltage CMOS (VTCMOS) technol-ogy for controlling VTH through substrate bias and aVariable Supply-voltage scheme for controlling VDDby an embedded DC-DC converter, and employedthem in a microprocessor core and an MPEG-4 chipin 1997. In 2000, he moved to Keio University, Yoko-hama, Japan, where he has been a professor since2002. This year he is Visiting MacKay Professor at theUniversity of California, Berkeley. His research inter-ests include ubiquitous electronics, sensor networks,wireless and wireline communications and ultra-low-power CMOS circuits. He has published more than200 technical publications including 50 invitedpapers, 18 books/chapters, and filed more than 100patents.

Dr. Kuroda served as the General Chairman for theSymposium on VLSI Circuits and as Vice Chairman forASP-DAC. He has chaired sub-committees for A-SSCC,ICCAD and SSDM, and served on conference programcommittees for the Symposium on VLSI Circuits, CICC,DAC, ASP-DAC, ISLPED, and others. He is an IEEE Fel-low and an IEEE SSCS Distinguished Lecturer.

Bram Nauta was born in Hengelo, TheNetherlands in 1964. In 1987 he receivedthe M. Sc. degree cum laude in electricalengineering from the University ofTwente, Enschede, The Netherlands. In1991 he received the Ph.D. degree from

the same university on the subject of analog CMOS fil-ters for very high frequencies.

In 1991 he joined the Mixed-Signal Circuits and Sys-tems Department of Philips Research, Eindhoven theNetherlands, where he worked on high speed ADconverters and analog key modules. In 1998 hereturned to the University of Twente as full professorheading the IC Design group, which is part of theCTIT Research Institute. His current research interestis high-speed analog CMOS circuits. He is also a part-time consultant in industry.

Dr. Nauta served as Associate Editor of IEEETransactions on Circuits and Systems -II; Analog andDigital Signal Processing (1997-1999), as Guest Edi-tor (1998) and Associate Editor (2001-2006) for the



SSCS-NEWSIEEE Journal of Solid-State Circuits. He is member ofthe technical program committees of ISSCC, ESS-CIRC, and Symposium on VLSI circuits. He is co-recipient of the ISSCC 2002 "Van Vessem Outstand-ing Paper Award". As of August 2007, he will serveas Editor in Chief of the IEEE Journal of Solid-StateCircuits.

Jan Sevenhans, who is an IEEE Fellowrecognized for “contributions to solid-state telecom transceiver integration,”joined the Communication High Voltagebusiness unit of AMI Semiconductor inBelgium in 2005 and previously was a

distinguished Member of the Technical Academy ofAlcatel Bell in Antwerp, Belgium. He served as Pro-gram chair of ISSCC 2006 and has been EuropeanChair of the International Solid-State Circuit Confer-ence (ISSCC). In 2002 he chaired the workshop“Analog telecom access circuits and concepts” atISSCC.

Born in 1955, Dr. Sevenhans received a Mastersdegree in 1979 and a Ph.D. in 1984 from the KULeuven in Belgium; his doctoral dissertation focusedon CCD imagers for facsimile applications. Hejoined Alcatel Bell in 1987, working on analog andRF circuit design for telecom applications in GSM,ADSL, ISDN, and POTs, and on CMOS and bipolarsilicon technology. He has filed many patents andpublished numerous articles in IEEE conferenceproceedings and journals. Since the late eighties hehas been involved in many European research proj-ects such as GSM in Jessi, Medea, Medea+, RACE,IST, and ESPRIT and Girafe - Gigahertz Radio frontEnds, in addition to Medea A203, SODERA, andSPACE. Over the past ten years, he has served asreviewer and/or evaluator of several European proj-ects, and is currently Region 8 representative for theSSCS AdCom.

Mehmet Soyuer received the B.S. and M.S.degrees in electrical engineering from theMiddle East Technical University, Ankara,Turkey in 1976 and 1978. He received thePh.D. degree in electrical engineering fromthe University of California at Berkeley in

1988, subsequently joining IBM at the Thomas J. WatsonResearch Center, Yorktown Heights, NY as a ResearchStaff Member. His work has involved high-frequencymixed-signal integrated circuit designs, in particularmonolithic phase-locked-loop designs for clock and datarecovery, clock multiplication, and frequency synthesisusing silicon and SiGe technologies.

At IBM Thomas J. Watson Research Center, Dr. Soyuermanaged the Mixed-Signal Communications Integrated-Cir-cuit Design group from 1997 to 2000. He was the SeniorManager of the Communication Circuits and SystemsDepartment from 2000 to 2006. In 2006, he was promotedto the position of Department Group Manager, Communi-cation Technologies, at Thomas J. Watson Research Center.

Dr. Soyuer has authored numerous papers in the areasof analog, mixed-signal, RF, microwave, and nonlinearelectronic circuit design, and he is an inventor and co-inventor of eight U.S. patents. Since 1997, he has been atechnical program committee member of the Interna-tional Solid-State Circuits Conference (ISSCC). He was anAssociate Editor of the IEEE Journal of Solid-State Circuitsfrom 1998 through 2000, and was one of the Guest Edi-tors for the December 2003 Special ISSCC Issue. Dr.Soyuer chaired the Analog, MEMS and Mixed-Signal Elec-tronics Committee of the International Symposium onLow Power Electronics and Design (ISLPED) in 2001. Hewas also a technical program committee member of theTopical Meeting on Silicon Monolithic Integrated Circuitsin RF Systems (SiRF) in 2004 and 2006. He served as anelected member of the Solid-State Circuits Society (SSCS)Administrative Committee (AdCom) for the last threeyears. Dr. Soyuer is a senior member of IEEE and a Dis-tinguished Lecturer of IEEE-SSCS.

CEDA Currents News from the IEEE Council on Electronic Design Automation

T. W. Williams Wins EDAA Lifetime Achievement AwardThe European Design and Automation Associationhas awarded the 2007 EDAA Lifetime AchievementAward to Thomas W. Williams for his outstandingcontributions to the state of the art in testability ofelectronic circuits, and specifically to full-scan design.This award is given to candidates who have madeinnovative contributions that have impacted the wayelectronic systems are designed. Past recipientsinclude Kurt Antreich (2003), Hugo De Man (2004),Jochen Jess (2005), and Robert Brayton (2006).

Thomas W. Williams is a Synopsys Fellow and anadjunct professor at the University of Calgary, Alber-ta, Canada. He has also served at IBM Microelectron-ics Division in Boulder, Colorado, as manager of theVLSI Design For Testability Group, which dealt withdesign for test (DFT) of IBM products. Williams has aBS in electrical engineering from Clarkson University,

an M.A. in pure mathematics from the State Universi-ty of New York at Binghamton, and a Ph.D. in elec-trical engineering from Colorado State University.Along with Edward B. Eichelberger, Williams pub-lished the first paper on the level-sensitive scandesign (LSSD) technique for testing logic circuits.Since then, he has been leading, defining, and pro-moting DFT concepts and has significantly influencedthe IC design community to adopt full scan as a defacto standard. As a result of his efforts, the EDAindustry has been able to base many of its leadingtools on the foundation of the full-scan design struc-ture. Prior to the adoption of full scan, the industryhad to deal with the sequential complexity of a non-scan design. Now, full-scan design has become apragmatic basis for a range of today’s design tools,including mainstream logic synthesis, static timinganalysis, and formal-verification solutions.


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Williams was also a founding member of the IEEETest Technology Technical Committee. In 1978, hestarted the first TTTC workshop—the DFT workshopalso known as the “Vail Workshop,” which was thefirst test workshop of any kind. He also cofoundedthe first test workshop in Europe, the European DFTWorkshop. This later grew into the European TestConference and then into a significant portion of theDesign, Automation and Test in Europe Conference(DATE).

He has authored several seminal papers related totest technology and scan design. An IEEE Fellow,Williams has received several awards, including theW. Wallace McDowell Award from the IEEE Comput-er Society (which he shared with Ed Eichelberger in1989). In 1997, he was presented the IBM CorporationAward for Test by president and CEO of IBM, Louis V.Gerstner.

For more information about this award, contactBernard Courtois ([email protected]).

Richard Newton Passed AwayEDA pioneer A. Richard Newton, Dean of Engineer-ing at the University of California, Berkeley, passedaway on 2 January 2007. The news came as a shockto the entire community. In a short span, RichardNewton wore many hats and contributed to the Soci-ety in so many ways as an academic, entrepreneur,and administrator, but above all as a visionary withenormous compassion. He made seminal researchcontributions to the EDA field and helped found keyEDA companies, including SDA Systems (nowCadence Design Systems), Crossbow, and Synopsys.From 1998 to 2002, he was a venture partner withMayfield Fund, a respected Silicon Valley VC firm.

Both our flagship publications have formal obituar-ies: In the Jan-Feb 2007 issue of IEEE Design and Test,Aart De Geus from Synopsys gave a personal accountof Newton’s life and contributions to the EDA indus-try. Subsquently, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems pub-lished a recollection from Newton's colleagues in aca-demia. For more information about the life andaccomplishments of A. Richard Newton, please visitwww.coe.berkeley.edu/newsroom/newton.

Student Programming Challenge at IWLS- Spring 2008CEDA sponsors an annual student ProgrammingChallenge during the International Workshop onLogic & Synthesis (IWLS) scheduled in late spring.Winning submissions become open source, releasedas part of the OpenAccess (OA) Gear infrastructure.The programming challenge advances and promotesan open-source logic synthesis system that providesthe basis for future comprehensive EDA tool flows,and a research platform based on the OpenAccessdatabase.

Individual students, as well as teams of multiplestudents, participate in this challenge to either imple-ment their current research on this platform or imple-

ment known and published synthesis algorithms aspart of their education. A list of suggested algorithmsis available at www.iwls.org/challenge.

The ChallengeThe challenge is to implement one or more logic opti-mization or verification algorithms on the OpenAccessindustrial EDA database. The algorithms should makemaximum use of the OpenAccess database, be imple-mented in a native manner, and adhere to the codingconventions of OpenAccess.

The algorithm should also be implemented withinthe OA Gear infrastructure. OA Gear provides an RTLVerilog reader and synthesis into a technology-inde-pendent netlist, an AIG (and-inverter graph); a simplemapper that directly maps the AIG’s nodes onto aspecified set of three library elements (AND, NOT,and FF); accurate timing analysis with slew propaga-tion; and a simple equivalence checker based on theAIG representation.

Technology-dependent optimization algorithmsshould be implemented directly on OpenAccess.Technology-independent algorithms should use thefunctional layer in OA Gear, along with the AIG pack-age. Participants should evaluate the results of thetechnology-dependent algorithms by performingaccurate timing analysis, preferably the incrementaltiming analysis of the OA Gear timer.

The winners will be invited to either give a talk orpresent a poster as part of the IWLS program, andtravel grants are awarded.

For more information and to download the soft-ware, go to www.iwls.org/challenge. Inquiries can bedirected to [email protected].

Upcoming CEDA eventsInternational Workshop on Power and TimingModeling, Optimization and Simulation (PATMOS)3-5 September 2007Göteborg, Swedenwww.ce.chalmers.se/research/conference/patmos07

2007 IFIP International Conference on VeryLarge Scale Integration (VLSI-SoC)15 Oct - 17 Oct 2007 Georgia Institute of Technology, Atlanta, GA www.vlsisoc2007.gatech.edu/

IEEE/ACM International Conference on Comput-er-Aided Design (ICCAD)4-8 November 2007San Jose, Calif.www.iccad.com

For more information regarding CEDA sponsorship ofconferences and meetings, contact Richard Smith,[email protected].

Please send contributions for CEDA Currents toKartikeya Mayaram ([email protected]) orPreeti Ranjan Panda ([email protected]).



SSCS-NEWS

Now you can see what are the most down-loaded articles from the previous month,any time you access the home page of

JSSC in IEEEXplore. This list is an interestingmeasure of what attracts others as the most read-able articles in an issue. It can be a useful way toschedule your reading when you have just a lim-ited amount of time. As competitive intelligence,the top downloads can be considered a metric ofwhat other designers think are timely topics toresearch.

And now this list is easy to find, since Xplorehas automated the monthly posting of the topaccessed articles for all its journals, on each one’sunique home page. When Xplore Version 2.3 wasupdated in March 2007, a new link pointing to“Top Accessed Articles for the Month” is right inthe middle of each transaction’s web page. Mostof the time only the previous month’s articles willhave reported enough downloads to be included.This URL goes to the JSSS home page in Xplore.

ieeexplore.ieee.org/xpl/RecentIssue.jsp?punum-ber=4

Want More? Access Top 100 DocumentsSince the JSSC is the most downloaded publi-cation of any in Xplore, a longer list of JSSCpopular downloads can be found any month in“Top 100 Documents,” a list from all the publi-cations in Xplore, standards and conferencesincluded. The “Top 100 Downloads” is avail-able from the Xplore home page in the lower lefthand corner. Reading through the top 100 can alertyou to a report on topics that interest you but in pub-lications you haven’t time to subscribe to, for exam-ple, materials science, nanotechnology, RFID, or bio-

electronics. Also among the top 100 you’ll find clas-sics from years past, that readers continue to access.Is it professors who assign these gems to their stu-dents, or experienced pros who remember where toreturn to refresh their fundamental understanding?

Timely JSSC Articles of InterestXplore User Tips

By Anne O’Neill, Executive Director SSCS, [email protected]

Wanted! Your Explanation: Why Gray and Meyers1982 Op-Amp Design Tutorial Is Still So Useful.“MOS operational amplifier design-a tutorialoverview,” by Gray, P.R.; Meyer, R.G., in the JSSC,Dec 1982, Pages: 969- 982.

This 25 year-old tutorial continues to be among thetop 100 downloads of the 1 1/2 million articles thatIEEE Xplore offers. Are students learning from it?Are experienced designers double checking theillustration of the equivalent circuit, countingnodes, trying to get to the bottom of the improve-ment quest for offsets and power supply rejection?Or do you have better sources to suggest? Is thebipolar architecture still a draw? Tell us your opin-ion. The SSCS News will summarize the topresponses. Deadline for reply, October 15. Send [email protected].

Select the “Top Accessed Articles for the Month” from the centerof Journal’s home page in Xplore.

Xplore lists the top 10 article read the previous month.


SSCS-NEWS


SSCS members have expressed interest in the burgeon-ing field of Nanotechnology and in tracking develop-ments in this area. To answer this need, all members ofSSCS will receive the new Nanotechnology Magazine aspart of their membership, beginning this fall. Publishedby the IEEE Nanotechnology Council, which the Societyjoined late last year, the first issue will feature the article“Convergence of Bio, Nano, and Information Technolo-gies,” by C. M. Ho and J. M. Chen, Institute for CellMimetic Space Exploration, UCLA, USA.

Other key articles will be:

“Semiconductor Research Corporation (SRC) Roadmapin Nanotechnology” (tentative title)Steven Hillenius, Vice President, SRC

Tutorial: “Carbon Nanotube Fabrication andApplications”Chongwu Zhou, University of Southern California, USA

“The Market Maturation of Nanotechnology”Louis J. Ross, Editor, Commercialization Section (IEEE

Nanotechnology Magazine)

“Investing in Nanotechnology Companies in Japan”J. Nakano, Innovation Engine, Japan

“IEEE-NANO 2007 Commercialization Workshop – AReview”Louis J. Ross,

“IEEE-NANOMED 2007 – A Review”Michael Dancu, Integrated Biodynamics, USA

The Nanotechnology Magazine is edited by Dr. Wen J. Li,Director, Centre for Micro and Nano Systems and Profes-sor, Mechanical and Automation Engineering Dept. TheChinese University of Hong Kong www.mae.cuhk.edu.hk/~wen. Dr. Meyya Meyyappan is CouncilPresident. SSCS representatives to the Council are BillBidermann and Ian Young. Please forward commentsand suggestions to either of these members of AdCom.

Further information may be found at ttp://www.ewh.ieee.org/tc/nanotech/.

SSCS Membership to Receive NanotechnologyMagazine Bill Bidermann, SSCS Meetings Chair

TryEngineering.org Now Available in Seven Languages The IEEE pre-university portal, TryEngineer-ing.org, once available in only English, is nowavailable in Chinese, French, German, Russian,Japanese and Spanish. In addition, the portal'smonthly newsletter is now featured in English,French and Spanish.

Users can examine the seven versions bychecking the language box on the top right-hand sideof the entry page to www.TryEngineering.org. The non-

English versions were derived from the Englishedition with the help of professional transla-tors. The translations were reviewed by engi-neers who are native speakers of the six lan-guages into which the site was rendered.

TryEngineering.org is a project of IEEE, IBM,and the New York Hall of Science. The transla-

tions and monthly newsletters are supported by the LifeMember Committee and the IEEE Foundation.

Graduating Students Get a Discount on DuesKeep IEEE informed of your fall address

IEEE Student Members who are scheduled to graduate in2007 will automatically receive a 50% discount off their2008 renewal bill. This discount is applicable regardlessof the degree being received. Student members whohave chosen to continue their education and pursue anadvanced degree can reclaim their IEEE Student memberstatus as long as they continue to carry 50% of a full-timecourse load in an IEEE-designated. Under such a sce-nario, they would retain their eligibility for the 50% dis-count once they have completed their next degree andhave not reached the eight-year student limit.

This “recent graduate” discount is only available oncein a lifetime. Therefore, any member who has previ-ously taken the discount upon receiving an earlierdegree would not be eligible to claim it again. To qual-

ify for the discount, the Student Member must transitiondirectly to Higher Grade membership immediately aftergraduation, without any break in membership. Thegraduate does not need to fill out any paperwork toqualify. Their 2008 renewal invoice will automaticallyreflect the discount.

In order to receive their renewal notice graduatesneed to keep IEEE informed of their fall address eitheronline with a member web account www.ieee.org/web/web/accounts/ or by sending new contactinformation to [email protected]. ContinuingSSCS members receive the SSCS News and are kept cur-rent of upcoming conferences. Remember SSCS confer-ences might be a goal for submitting graduate researchfor acceptance and presentation.


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SSCS SPONSORED MEETINGS2007 Custom Integrated Circuits Conferencewww.ieee-cicc.org/16–19 September 2007San Jose, CA, USAContact: Ms. Melissa [email protected]

2007 A-SSCC Asia Solid-State Circuits Conferencewww.a-sscc.org/12–14 November 2007Jeju Island, KoreaContact: : [email protected]

2007 ISSCC International Solid-State Circuits Conferencewww.isscc.org3– 7 February 2008 San Francisco, CA, USAPaper deadline: 17 September 2007Contact: Courtesy Associates, [email protected]

2008 Symposium on VLSI Circuitswww.vlsisymposium.org19–22 June 2008Honolulu, HIPaper deadline: TBDContact: Phyllis Mahoney, [email protected] Business Center for Academic Societies, Japan,[email protected]

SSCS PROVIDES TECHNICAL CO-SPONSORSHIP ISLPED International Symposium on LowPower Electronics and Designwww.islped.org/ 27-29 Aug 2007Portland, ORContact: Diane Marculescu, [email protected]

Hot Chipswww.hotchips.org11 Sep - 13 Sep 2007 Palo Alto, CA, USAContact: John Sell, [email protected]

ESSCIRC/ESSDERC 2007 - 37th European SolidState Circuits/Device Research Conferenceswww.esscirc2007.org11 Sep - 13 Sep 2007 Munich, GermanyContact: Mr. Philip [email protected]

2007 IEEE Integrated Circuit Ultra-Wide BandICUWB www.icuwb2007.org24 – 26 Sep 2007 Singapore Contact: Michael Y.W. Chia, [email protected]

2007 IEEE Bipolar/BiCMOS Circuits and Technology Meeting - BCTM www.ieee-bctm.org30 Sep - 02 Oct 2007 Boston, MA Contact: Ms. Janice [email protected]

2007 IEEE Compound Semiconductor Integrated Circuit Symposium (CSICS)(Formerly GaAs IC Symposium) www.csics.org14 Oct – 17 Oct 2007Portland, ORContact: William Peatman [email protected]

2007 IEEE/ACM International Conference onComputer-Aided Design (ICCAD) www.iccad.com/future.html04 - 8 Nov 2007San Jose, CAContact: Ms. Kathy [email protected]

2008 International Symposium on VLSI Technology, Systems and Applications (VLSI-TSA) vlsidat.itri.org.tw21 - 23 Apr 2008Hsinchu, Taiwan Paper Deadline: 15 October, 2007Contact: Ms. Stacey C.P. [email protected]

2008 Design Automation Conferencewww.dac.com9–13 June 2008Anaheim, CA, USAPaper deadline: TBDContact: Kevin Lepine, Conference [email protected]

2008 Radio Frequency Integrated Circuits Symposium www.rfic2007.org15–19 June 2008Honolulu, HawaiiPaper deadline: TBDContact: Dr. Luciano [email protected]

SSCS EVENTS CALENDARAlso posted on www.sscs.org/meetings

SSCS IEEE SOLID-STATE CIRCUITS SOCIETY NEWS is published quarterly by the Solid-State CircuitsSociety of The Institute of Electrical and Electronics Engineers, Inc. Headquarters: 3 Park Avenue, 17thFloor, New York, NY 10016-5997. $1 per member per year (included in society fee) for each member ofthe Solid-State Circuits Society. This newsletter is printed in the U.S.A. Application to mail Periodicalspostage rates is pending at New York, NY and at additional mailing offices.Postmaster: Send address changes to SSCS IEEE Solid-State Circuits Society News, IEEE, 445 Hoes Lane,Piscataway, NJ 08854. ©2007 IEEE. Permission to copy without fee all or part of any material without acopyright notice is granted provided that the copies are not made or distributed for direct commercialadvantage and the title of publication and its date appear on each copy. To copy material with a copy-right notice requires specific permission. Please direct all inquiries or requests to IEEE Copyrights Man-ager, IEEE Service Center, 445 Hoes Lane, Piscataway, NJ 08854. Tel: +1 732 562 3966.

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