moon sscs dl

Emerging ADCsEmerging ADCs(New/interesting ideas for ADC design)

Presentation at Columbia University Presentation at Columbia University –– NYCNYCSeptember 17, 2010p

Un-Ku MoonOregon State UniversityOregon State University

Electrical Engineering and Computer Science

It’s a Mixed-Bag of New/Interesting Ideas

Which will emerge gas the winner?

This tutorial

Taste of a variety

EmergingEmergingADCsADCs

Page 2U. Moon Oregon State UniversityOregon State University Emerging ADCs

Still brewing…

What Motivates These Emerging Ideas?

CMOS Scaling

Analog switches difficult to operate

High gain opamps difficult to build

Noise immunity worsens with increasing integration and smaller signal swing

Minimum size device matching degrades withMinimum size device matching degrades with device scaling

Add your favorite problem/challenge here

And general others… such as future and emerging markets/applications, etc.


g g

Today’s Presentation

Let me summarize/present, and let us ponderWe will look atWe will look at

Selective/popular emerging ADCs

Random slices of emerging ADCsRandom slices of emerging ADCs

We won’t make any serious value judgmentBut we can argue about it :-)But we can argue about it : )

Ultimately future will make that judgment

Primarily to provide exposure to various ideasy p pFor you to take home and digest/improve/innovate

For you to critique, filter, ridicule…


Presentation Content

Zero-crossing detector (comparator) based ADCVCO (noise-shaping quantizer) based ADCContinuous-time input pipelined ADCCorrelated level shifting (CLS) based ADC

Stochastic (mostly digital) ADCAsynchronous SAR ADC

Perhaps your favorite is missing…


First Things First

I would like to acknowledge and thank my colleagues and graduate students who provided much of the following material

Dr Rob Gregoire Hoyoung LeeDr. Rob GregoireDr. David GubbinsBen Hershberg

Hoyoung LeeDr. Nima MaghariDr. Tawfiq Musah

Yue Hu Dr. Skyler Weaver


ZeroZero--Crossing Detector (Comparator) Based ADCCrossing Detector (Comparator) Based ADC

Sepke et al. ISSCC 2006 & JSSC Dec-2006Brooks et al. ISSCC 2007 & JSSC Dec-2006

Shin et al. VLSI 2008Brooks et al. ISSCC 2009

Chu et al. VLSI 2010

Huang et al. TCAS2 May-2009Musah et al. CICC 2009


Comparator-Based SC (CBSC) Circuits

Opamp is replaced with a comparator and a switched current source

High gain comparator can be designed as a cascade of several stages since it has no stability constraint

Mi i t d l i l h t


Minimum comparator delay ensures marginal overshoot

Comparator-Based Pipelined ADC

CFΦ2 Q

Sepke et al. ISSCC 2006

Φ1

Φ1

CS

Φ2

Φ1

Φ2

VIN

CL

Φ

I1 Φ2

ΦPC

VX

Q1

VO

Φ1Φ2 2

DVRP VCM

VCMΦ2

ΦPCQ2Q1

Q2

I2

Q

VCMVX

Fi t/ f f t li ti f th CBSCFirst/proof-of-concept realization of the CBSCComparator is a cascade of several gain stagesA fine charging phase minimizes overshoot


10bit (52dB SNDR) 8MS/s pipelined ADC in 0.18µm

Zero-Crossing-Based Circuits (ZCBC)

CFΦ2 Φ2

Φ

Brooks et al. ISSCC 2007

Φ1

Φ1

CS

Φ2

Φ1VINI1

Q

Φpc

VX

I2

VO

Φpcb Φ2

Φ1Φ2Φ2

DVRP VCM

CLΦpc

Q

Φpcb

VX

ZCD

VCMVO

C t l d ith i l i d t t (ZCD)Comparator replaced with simple zero-crossing detector (ZCD)Currents split to minimize switch nonlinearities8bit (6.4 ENOB) 200MS/s pipelined ADC in 0.18µm CMOS


( ) p p µ

Fully Differential ZCBC with CMFB

CFΦ2

I1

Φ1

Shin et al. VLSI 2008

Φ1

Φ1

CS

Φ2

Φ1VOP

Φ2

VINP

DVRP

I2

Q1

CL

ZCD

Φ2

ΦPC

VXP

ΦPC

Φ2

CSΦ1Φ2

Φ1

DVRP

DVRNOCC

Q2

VCM

CL

+logic QA

QBVXN

ΦPC

VCM

VINN

Φ1VON

CF Φ2

I2

CMFBVOP

VON VXP

VXN

XN

ZCD cascade of two differential pairs and an inverter CMFB and overshoot correction improves accuracy


CMFB and overshoot correction improves accuracy10bit 26MS/s pipelined ADC in 65nm CMOS

Fully Differential ZCBC – No CMFB

CF

Φ

Φ2

VOPV

I1 I2

Φ1

Φ2Brooks et al. ISSCC 2009

Φ1

Φ1

CS

Φ2

Φ1

Φ2

VINP

DVRP

DVQ

CL

VCM

Φ2

ΦPC

VXP

ZCD

ΦPC

ΦPC

VCM

VINN

Φ2

CSΦ1

VON

Φ2

Φ1

DVRNCM

CL

QA

VXNVXN

ΦPCΦPC

CM

Φ1VON

CF Φ2 VXP

Φ2 I2I1Also see…Li et al. JSSC Sep-2004Ahmed et al. ISSCC 2009

Output differentially sampled (floating switch) – No CMFBZCDs digitally trimmed (background) to remove overshootReplica/dummy current sources for matching and noise rejection


Replica/dummy current sources for matching and noise rejection12bit (62dB SNDR) 50MS/s pipelined ADC in 90nm CMOS

FOM of These Pipelined ADCs Improving

FOM = P/(fs*2ENOB)

Chu et al.VLSI 2010(100 MS/s)

53-80 fJ/step

X


Fully Differential CBSC Integrator (∆Σ)

CF

V

I1

I

Q1

Φ1Φ2

VRN

Φ2

VRPHuang et al. TCAS2 May-2009

Φ1

Φ1

CS

Φ2

VOP

Φ2

VINPQ2

I2

CL

Φ2

ΦPCVXP

ΦPC

Φ2VRN

Φ1 Φ2Φ2

Φ1

VCM

CL

Q1

Q2

VXNΦPC

VCM

Φ2

VRP

VINN CSVON

CF

I2

VXP

VXN

Φ2

VRP

Φ2

VRN

Q2

Q1

Coarse/fine charging with CMFB (not shown)Comparator realized as self-biased differential amplifier


Comparator realized as self biased differential amplifierSecond-order 2-level DSM in 0.18µm CMOS

Fully Differential ZCBC Integrator (∆Σ)Musah et al. CICC 2009

CBSC/ZCBC integrator:

Use of resistor current sources eliminates need for CMFBNew charging scheme reduces some errors & maximizes swing

CBSC/ZCBC integrator:More issues…


New charging scheme reduces some errors & maximizes swingSecond-order 2-level DSM in 45nm digital CMOS

VCO (NoiseVCO (Noise--Shaping Shaping QuantizerQuantizer) Based ADC) Based ADC

H i t l JSSC J 1997Hovin et al. JSSC Jan-1997Iwata et al. ISCAS 1998 & TCAS2 Jul-1999

Wismar et al ESSCIRC 2006Wismar et al. ESSCIRC 2006Kim et al. ISCAS 2006

Straayer et al. VLSI 2007 & JSSC Apr-2008Straayer et al. VLSI 2007 & JSSC Apr 2008Straayer et al. VLSI 2008 & JSSC Apr-2009

Park et al. ISSCC 2009Maghari et al. EL Jun-4-2009


Time Domain Signal Processing

The proponents make the case that time

domain signal resolution is independent of supply p pp yscaling and more robust

to voltage noise


VCO Based ADC Resolution

Sampling period Numberof

rising edges

)(log

)(log

2

minmax2

etuningrangVCO

samplesample

VKff

ffresolution

⋅=

−=fmax

1LSB(2π)

8

)(log2samplef

fmin

1LSB(2π)

2

1LSB(2π)

Issues:Need wide/linear VCO tuning range for high resolution ADC VCO based ADC linearity limited by nonlinear voltage-to-frequency conversion


VCO as Voltage-to-Frequency/Phase Conversion ]1[][][ −−⋅⋅= nenXTKnP SVCO

][][][ nenPnY +=

]}[]1[][{21 nenenXTK SVCO +−−⋅⋅=π

]}[)1(][{21][ 1 zEzzXTKzY SVCO

−−+⋅⋅=π

)1( 1−−= zNTF

Quantization = Edge countingInherent first-order noise shaping

Hovin et al. JSSC Jan-1997Iwata et al. ISCAS 1998 & TCAS2 Jul-1999


Noise-Shaping VCO Quantizer Based “DSM”

Hovin et al. JSSC Jan-1997Wismar et al. ESSCIRC 2006

Kim et al. ISCAS 2006

VCO ti i l i t tVCO as continuous signal integratorVCO input spans entire input range

VCO nonlinearity and phase noise unfiltered


VCO-Based Delta-Sigma (Higher Order) ADC

Iwata et al. ISCAS 1998 & TCAS2 Jul-1999Straayer et al. VLSI 2007 & JSSC Apr-2008

High gain filter placed before VCOVCO input span attenuatedVCO nonlinearity and phase noise filtered (largely improved but still nonlinear)

Also see: Straayer et al VLSI 2008 & JSSC Apr 2009


Also see: Straayer et al. VLSI 2008 & JSSC Apr-2009Gated ring oscillator (GRO) based time-to-digital converter (TDC)

Linear Voltage-to-Phase QuantizationPark et al. ISSCC 2009

PHASE instead of frequency is quantized and fed back via DAC equivalent (this is just the quantizer portion of DSM)DAC equivalent (this is just the quantizer portion of DSM)

leverages infinite gain of VCO as a phase integratorNonlinearity of VCO quantizer eliminated


Higher order filter (∆Σ) for further noise shaping

Dual Slope Based Noise-Shaping Quantizer

Quantization error

Maghari et al. EL Jun-4-2009C

1ϕ R Quantization error…Stored on integrating cap (not reset)

X

DV

1ϕ

2ϕoutV

Effectively added to the new input sample

First-order1ϕ 2ϕoutV 1ϕ First-ordernoise-shaping(like the VCO)t

outD

tLSB - e(n)

Stop DischargeStop DischargeTraditional Proposed

This opens paths tomany possibilities…


ContinuousContinuous--Time Input Pipelined ADCTime Input Pipelined ADC

Gubbins et al.CICC 2008, CICC 2009, JSSC-2010


Problem Statement

Interfacing to high performance ADC is not trivialMany application notes writtenIncorrect external circuitry leads to poor ADC results

Typical application circuit


Gray, Smith, EDN May 1998

Conceptual Front-end Sampler


Continuous-Time Input

Prediction block and sub-ADC

Gubbins et al. CICC 2008

Eased accuracy requirementsAnalog filter requires tweaking/calibrationIdac has half a period to settle like S/C MDAC


Idac has half a period to settle like S/C MDAC

Prediction Filter

Zeros and poles:Goal of equiripple magnitude and linear phase lead


Filter Frequency Response• Prediction filter provides T/2 phase lead

– Filter does not affect ADC frequency response


Windowed Continuous-Time Input

Gubbins et al. CICC 2009

Window = SINC filteringAnti-alias filter merged into first stage


Anti alias filter merged into first stageResidue is windowed and sampled into second stage

Measured ADC Frequency Response

Fs=26MHz 40dB/dec

ADC

-14dB -40dB/dec

ADCGain(dBs)


Input Signal Frequency (MHz)

Improved Jitter Performance (Simulation)

79

84SNR vs. Input Frequency (Spectre 13b ADC model)

SNR(impulse sampling)

69

74

79

[dB

]

SNR(window sampling)

SNR(window residue sampling)

59

64

69

SNR

54

59

0 2 4 6 8 10 12 14 InputFrequency[MHz]

~3dB improvement at Nyquist (12.5MHz)Jitter affects input signal and reference (i.e. correlated)

Input Frequency [MHz]


p g ( )Low frequency number depends on first stage resolution

Correlated Level Shifting (CLS) Based ADCCorrelated Level Shifting (CLS) Based ADC

Gregoire et al. ISSCC 2008 & JSSC Dec-2008Hershberg et al. ISSCC 2010 & JSSC Dec-2010


Low Voltage Issues0.9V

0.15V

Bias 0.6V “useful”

range

0.15V

0.0V

Limited “useful” rangeLow and nonlinear gain – hard to digitally calibrateg g yProcess scaling will not increase headroom1/3 supply unusable (in this example)2 25 it ( ) f SNR


2.25x capacitance (power) for same SNR

CLS Closed-Loop Performance

0.9V

Bias Out

0.0V

=1/2=1/2

30dB opamp: ~5 bits, small swingCLS: > 10 bits large swing


CLS: > 10 bits, large swing

CLS Step 11

2

Sample input

3LS

OP

0

INOP OUT

0

OUT

0 0

ININININ


0 0

CLS Step 2Flip around, sample output

A/212VIN+ A/21+


CLS Step 3Level shift

A/212VIN+

( )2IN

A/212V+A/21

2VIN+ ( )A/21+A/21+


CLS ≠ CDS (Approach)

CLS LS

Subtracts signalOpamp processes error

CDSSubtracts errorO

DS

Opamp processes signal


CLS ≠ CDS (Open-Loop)

CLSCLS(gain)·(best gain+)

CDS36dB

CDS(gain)2

30 dB opampBest 30 dB opamp(gain)

Best Gain


Testing (Beyond) Rail-to-Rail


Measured ENOB

VDD =0.9VVREF=1.0VFs=20MHz

Fin=1, 10MHz6.2mW (analog)( g)


Split-CLS Advantage

Vo

ФФA VDD = 1V

Hershberg et al. ISSCC 2010 & JSSC Dec-2010

CCLSФS Ф1

Vi

ФA

A1

Vx150mV

1V 600mV

450mV

100 VФA

Ф2

V V

ФSФ1

(+/-Vr,0) A2

150mV

450mV

100mV

Aeff = A1·A2

High gain using simple opamps,

VCMI VCMO150mV

1 220dB + 60dB

even in deep submicron (80dB)

A1 – use zero-crossing detector (ZCD)11+ ENOB results


A2 – use low-swing high-gain opamp11+ ENOB results

Stochastic ADCStochastic ADC(Mostly Digital and Hopefully Synthesizable ADC)(Mostly Digital and Hopefully Synthesizable ADC)(Mostly Digital and Hopefully Synthesizable ADC)(Mostly Digital and Hopefully Synthesizable ADC)

Weaver et al. ASSCC 2008 & TCAS1 2010


Fundamental Observation

Comparator offset defines flash ADCOffset is randomIndividual offsets are unknownOffset distribution can be known

0.4

ensi

ty

Input-referred offset

00.10.20.3

Prob

abili

ty D

e


-3 -2 -1 0 1 2 30

Comparator Offset (σ)

P

System Level Consideration: A Closer LookApply ramp to comparators with random offsetsShift in reference shifts transfer functionTwo Gaussian CDFs spaced 2σ sum to a lineTwo Gaussian CDFs spaced 2σ sum to a line

256

384

512

utpu

t

Σ–1σ

-3 -2 -1 0 1 2 30

128

Input (σ)

Ou

768

1024

ut

ramp input

–1σ x512 Σ256

512

Out

p

Σ+1σ x512 0

128

256

384

512

Out

put -3 -2 -1 0 1 2 3

0

Input (σ)


x512 -3 -2 -1 0 1 2 3Input (σ)

2.4mm x 2.4mm in 0.18µm CMOS


192 x 20 x 2 = 7680 comparators

Measurement Results

0.5

0.75

m2 )

1000

1500

μW)

Area

0

0.25

0.5

Are

a (m

0

500

1000

Pow

er ( μ

Power

384 768 1152 1536 19200

384 768 1152 1536 19200

Comparators

5

5.5

6NO

B

384 768 1152 1536 19204

4.5

Comparators

EN

Nonlinearity reductionGaussian lookup table


Comparators

Can We Fully Synthesize ADC?

Add digital-like analog blocks to digital libraryMatch supply pitch and library rulespp y p yGenerate other files required by synthesis tool

La o t LEF Verilog etcDesired Layout, LEF, Verilog, etc.analogblock


Digital library

This Just Might Work…

Entire ADC described in verilog/VHDL

module adc_block(in,out);input in;reg out;

endmodule

verilog/VHDLsynthesis

ADC Layout

synthesis


Asynchronous SAR ADCAsynchronous SAR ADC

Ch t l ISSCC 2006Chen et al. ISSCC 2006Yang et al. CICC 2009 & JSSC 2010

C.C. Liu et al.VLSI 2009 & JSSC 2010, ISSCC 2010, VLSI 2010


Conventional SAR Architecture

QS

QM

QS

Dn-1

DDn-2

D0

N clock per N-bBinary search algorithm

Reduces both circuit complexity and power consumptionCharge redistribution for high accuracyCharge redistribution for high accuracyRelatively low speed operation

N clock periods needed for N-bit conversionPo er cons med in high speed clock generator


Power consumed in high speed clock generator

Asynchronous ClockingChen et al. ISSCC 2006

DO

Capacitor Network

Vin

VREFSAR

Async

Vx

Async Clock Generator

Async. CLK

Async.

QS

CLK

Next clock is generated from previous latch outputNo need for high-speed synchronous clock generatorCould minimize clock timing marginDelay decreased with submicron scaling


Low noise and low power…

Metastability in Asynchronous SAR

Yang et al. CICC 2009 & JSSC 2010

Generate metastability information for eachGenerate metastability information for each conversion

e.g. Look at how many cycles are completed for each i (l th f ll t t t bilit )conversion (less the full count = metastability)

When metastability occursFill remaining bits with the opposite polarity of the last g pp p yresolved bit (all were reset to zero before conversion)In other words, replace the unresolved bits (including the metastability one) with “10…0” or “01…1”y )

This is my interpretation of Yang’s presentationContact the author for clarification!


Contact the author for clarification!

Record Setting (FOM) Asynchronous SARs

10 bit 50 MSPS in 0.13μmEnergy efficient Clk_in

Vref

C8 C9C7C6C4C3C2 C5C1

C.C. Liu et al. VLSI 2009 & JSSC 2010

gyasymmetric switching to

yield 52 fJ/cs FOMSAR Dout

10

Bootstrapped Switch

Vip

Vin

C8 C9C7C6C4C3C2 C5C1

Cunit=10fF, Ci=2Ci+1, i=1~8 Vref

10 bit 100 MSPS in 90nmC.C. Liu et al. ISSCC 2010 0 b t 00 S S 9015.5 fJ/cs FOM with added redundancy


Concluding Comments

Well… this is your favorite/LAST slide!

What looks most promising to you?What looks most promising to you?Comparator/zero-crossing based circuitsVCO-based/noise-shaping quantizersCorrelated Level Shifting (CLS)Continuous-time input pipelineSomething else? all passive architectures SAR varietiesSomething else?... all passive architectures, SAR varieties, dynamic source follower, etc.

Maybe none of the above... still brewing!

Emerging

Maybe none of the above... still brewing!


EmergingADCs

moon sscs dl

Documents