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SSCSSSCSSSCSSSCSIEEE SOLID-STATE CIRCUITS SOCIETY NEWSFall 2008 Vol. 13, No. 4 www.ieee.org/sscs-news

Gordon BellBell’s Law for the Birth and Deathof Computer Classes

sscs_NLfall08.qxd 10/8/08 10:04 AM

As in the past,the goal ofthis issue is

to be a self-con-tained resource, withoriginal sources andnew contributions

by experts describing the currentstate of affairs in technology in viewof the influence of the originalpapers and/or patents.

Since launching the redesign of

the Newsletter in 2006, it has beenour vision to provide the Society’s11,000 members with a publicationthat celebrates not only their techni-cal accomplishments but also theirpersonal achievements by reportingawards and publishing photographs,personal commentary, and specialhistorical and business articles toprovide coverage depth and breadth.

Throughout the past two years,Paul Doto of the IEEE Newsletter

team has been on board with usevery step of the way to convey ourvision to SSCS members through theuse of specially-requested design ele-ments that he took the time to incor-porate into each issue on our behalf.

Thanks to Paul, the layout of eachissue has uniquely highlighted tech-nical articles by and about our featureauthor, members’ accomplishmentsand work-in-progress, educationaloutreach and our Distinguished Lec-turer Program, Society news, and keyactivities of our conferences andchapters throughout the world.

To forward our vision, Paul wentabove and beyond to personallydesign full-color full-portrait coversbased on author-supplied photo-graphs and creative twists on oursociety’s red and black theme. Thedistinguishing elements of our pub-lication are its cover portraits, red-and-black cover theme and straight-forward red title, black cover back-ground, and interior section colorhighlights. We have personallypromised all Feature Authors thattheir photos will appear on thecover, and Paul’s efforts have ele-gantly fulfilled these agreements.

Thank you, Paul!! It has trulybeen a pleasure working with you.

Please consider sending a thankyou to Paul for all of his hard workand commitment to our society’smission. His email address [email protected]; his webpage ishttp://www.pauldoto.com.

In this final issue of the SSCS News,we feature Gordon Bell, who has con-tributed an extensive new FeatureArticle entitled “Bell’s Law for the Birthand Death of Computer Classes: ATheory of the Computer’s Evolution.”Dr. Bell is a principal researcher atMicrosoft Research in Silicon Valley,working in the San Francisco Labora-tory. His home page is: http://research.microsoft.com/~GBell. Weare delighted to have the opportunityto present Dr. Bell and his work.

2 IEEE SSCS NEWS Fall 2008

SSCS NewsEditor-in-Chief:Mary Y. LanzerottiIBM T. J. Watson [email protected]: +1 914 945 1358

Technology Editor:Richard C. JaegerAlabama MicroelectronicsCenter AuburnUniversity, [email protected]

Tutorials Editor:Rakesh KumarTechnology ConnexionsPoway, [email protected]

Associate Editor forEurope/Africa:Tony HarkerAlba Centre Alba CampusLivingston Scotland EH54 [email protected]

Associate Editor for the FarEast:Pengfei ZhangBeken CorporationShanghai, [email protected]

News Editor:Katherine OlsteinIEEE [email protected]

Administrative CommitteePresident:Willy SansenK. U. Leuven, [email protected]: +32 16 321975

Vice-President:Bernhard BoserUniversity of CaliforniaBerkeley, CA

Secretary:David A. JohnsUniversity of TorontoToronto, Ontario, Canada

Treasurer:Rakesh KumarTechnology ConnexionsPoway, CA

Past- President:Richard C. JaegerAlabama MicroelectronicsCenterUniversity, AL

Other Representatives:Representative to SensorsCouncil

Darrin YoungRepresentative from CAS toSSCS

Domine LeenaertsRepresentative to CAS fromSSCSUn-Ku Moon

Elected AdCom Members atLargeTerms to 31 Dec. 08:Wanda K. GassAli HajimiriPaul J. Hurst

Akira MatsuzawaIan Young

Terms to 31 Dec. 09:John J. CorcoranKevin KornegayHae-Seung (Harry) LeeThomas H. LeeJan Van der Spiegel

Terms to 31 Dec. 10:Terri S. FiezTadahiro KurodaBram NautaJan SevenhansMehmet Soyuer

Region 8 Representative:Jan Sevenhans

Region 10 Representative:C.K. Wang

Chairs of Standing Committees:Awards John J. CorcoranChapters Jan Van der SpiegelEducation C.K. Ken YangMeetings Bill BidermannMembership Bruce HechtNominations Richard C. JaegerPublications Glenn Gulak

For detailed contact informa-tion, see the Society e-News:www.ieee.org/portal/site/sscs

IEEE Solid-State Circuits Society

Editor’s Column

Executive Director:Anne O’Neill IEEE SSCS-West: 1500 SW 11th Avenue #1801Portland, OR 97201Tel: +1 732 981 3400Fax: +1 732 981 3401Email: [email protected]

Administrator:Katherine OlsteinIEEE SSCS445 Hoes LanePiscataway, NJ 08854Tel: +1 732 981 3410Fax: +1 732 981 3401

For questions regarding Society business, contact the SSCS Executive Office. Contributions for theWinter 2009 issue of the SSCS Magazine must be received by 8 November 2008 at the SSCS Execu-tive Office. A complete media kit for advertisers is available at www.spectrum.ieee.org/mc_print.Scroll down to find SSCS.

Mary Y. Lanzerotti, IBM, [email protected]

continued on page 4


Fall 2008 IEEE SSCS NEWS 3

Photo of Gordon Bell

Fall 2008 Volume 13, Number 4

Editor’s Column . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2President’s Message . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4A Returnee from the US Becomes Entrepreneur in China, Pengfei Zhang, Associate Editor for the Far East . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5Solid-State Circuits Magazine and Redesigned Website to Launch in 2009, Anne O’Neill,SSCS Executive Director . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

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TECHNICAL LITERATUREBell’s Law for the Birth and Death of Computer Classes: A Theory ofthe Computer’s Evolution, Gordon Bell . . . . . . . . . . . . . . . . . . . . . . . . . 8Advances in Ultra-Low Power Design, Joyce Kwong and Anantha Chandrakasan 20Gigasensors for an Attoscope: Catching Quanta in CMOS, Erik H. M. Heijne . 28Microwatt Switched Capacitor Circuit Design: Prepared for a Summer Course at K.U. Leuven, 1981, Eric Vittoz . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

PEOPLEAnkush Goel and Shih-An Yu Receive SSCS Predoctoral Fellowships for 2008-2009, John Corcoran . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49IEEE DL Vojin Oklobdzija Visits Istanbul, Izzet Cem Goknar . . . . . . . . . . . . . . . . . . . . . . . . 50Twenty New Senior Members Elected . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51Tools: Tips for Making Writing Easier, Part 3: Focus on Your Key Message,Peter and Cheryl Reimold . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51

CONFERENCESISSCC 2009 Preview, Anne O’Neill . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .52ISSCC 2009 Student Forum, Anne O’Neill . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .524th Asian Solid-State Circuits Conference – Digital Convergence for a UbiquitousLifestyle, Koji Kito . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .53ICCAD Previews Novel Program, Juan-Antonio Carballo . . . . . . . . . . . . . . . . . . . . . . . .54ICUWB 2009 to Focus on Microwave and Millimeter Wave BandTechnology, Lutz Lampe . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .55

CHAPTER NEWSFirst IEEE COMCAS a Mega Event in Tel Aviv, Mark Ruberto, Shmuel Auster, Barry Perlman . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .56SSCS-Singapore Hosts 90 at ISSCC 2007 Tutorial Replay, Katherine Olstein . . . . . . . . .58SSCS-Taipei Offers Short Course on CMOS Single-chip Radio Design, Eric Tsung-Hsien Lin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .59SSCS DL Stefan Rusu Speaks at Santa Clara Valley Chapter Meeting,Katherine Olstein . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .59SSCS-Scotland Sponsors Technical Meeting, Jim Brown . . . . . . . . . . . . . . . . . . . . . . . .60Leuven Student Branch and SSCS Chapters Organize 2nd SSCS-Benelux Microelectronics Symposium, Cedric Walravens . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .61Preview of EDSSC2008 in Hong Kong, KP Pun . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .61IEEE SSCS Joint Chapter Formed in Penang, Malaysia, Booon Eu Seow . . . . . . . . . . .62Romania SSCS Chapter Formed to Promote Circuit Activities in Eastern Europe,Marcel D. Profirescu . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .63

SSCS NEWSSSCS AdCom Endorses Newsletter-Magazine Conversion in Summer Meeting . . . . .65CEDA Currents: IEEE/ACM MEMCODE Contest Update . . . . . . . . . . . . . . . . . . . . . . . .6665

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President’s MessageWilly Sansen, K. U. Leuven, [email protected]

Vision 2020Some level of happiness and satis-faction was reached around thetable at our AdCom meeting in SanFrancisco on August 18th becauseof the conversion of the Newsletterinto a Magazine.

Although this may seem trivial, itis not. -- The Magazine will havemuch better quality in appearanceand editing and, most important ofall, will be saved from obsoles-cence, since it may be consultedthrough IEEE Xplore.

The Solid-State Circuits Societyhas worked hard to make thishappen. -- It has been in theminds and on the table of AnneO’Neill, Katherine Olstein, and, ofcourse, Mary Lanzerotti. Theydeserve to be complimented fortheir achievement.

Discussions that peered furtherinto our future, however, about thebreathtaking recommendations ofan ad hoc committee formed lastyear to explore how ISSCC mightlook in 2020 were overwhelming.

According to the final report ofISSCC’s Vision 2020 Task Force pre-sented in San Francisco six times inthree days by Dennis Monticelli, theconference may go virtual, and e-papers, an e-digest, and comple-

mentary materials such as an e-jour-nal (whatever that means) may allhave to be defined for a more effi-cient conference. [What is a moreefficient conference? -- Will net-working prevail over technical datatransfer, or vice-versa? What is thecommon content between a confer-ence paper and a journal paper?What is the most efficient way toput together a paper in terms ofinformation transfer? Can the repro-ducibility of the results beenhanced? What can be done todayrather than in 2020?]

Task Force actions taken alreadywill result in four experimentalsatellite conferences that will beheld next year in the Far East, with-in three weeks of the ISSCC. Theywill use the audio/video recordedsessions of the ISSCC and duplicatesome of them within two to threedays for local engineering commu-nities. The same audio/videorecorded sessions are currentlyavailable under ISSCC’s “Replay-on-Demand” program four months afterthe Conference. Its success is slow-ly rising. Whether this product willreduce conference attendance is anopen question. Everybody is alsoanxious to see how successful thesatellite conferences can be, and

also whether they will reduce atten-dance at the ISSCC in February.

The Vision 2020 Task Forcereport was heard in San Franciscoby the Task Force itself, theISSCC Long Range Planning Com-mittee and ISSCC executive com-mittees, the SSCS Meetings Com-mittee chaired by Bill Bidermannand the SSCS Publications com-mittee chaired by Glenn Gulakand, finally, by the AdCom itself.Dennis must be complimentedfor this task. His set of 27 slidesnot only addresses the future ofthe ISSCC but of all SSCS confer-ences, and even conferences ingeneral. This set of slides will beused as a blueprint for a numberof action committees within theSociety. Obviously, they will alsobe used to tune results with rec-ommendations generated byother Societies.

Exciting times, indeed, as notedseveral times by Dick Jaeger, Past-president of the SSCS.

Willy SansenPresident

We also print an original paperby Dr. Eric Vittoz, who was theFeature Author of our Summer ‘08issue, and two additional articlesabout his work: (1) “Advances in Ultra-Low-Voltage

Design,” by Joyce Kwong andAnantha Chandrakasan (MIT);

(2) “Gigasensors for an Attoscope,”by Erik H. M. Heijne (CERN).

(3) E. Vittoz, “Microwatt Switched

Capacitor Circuit Design,”Summer Course on SwitchedCapacitor Circuits, June 9-12,1981, ESAT, Katholieke Uni-versiteit Leuven, Heverlee,Belgium.

With this issue I would also liketo welcome Pengfei Zhang as ournew Associate Editor for the FarEast. Please take this opportunity toread his first column, which appears

in this issue. Dr. Zhang received hisPh.D. degree from Tsinghua Univer-sity in Beijing, China, and was apost-doctoral scientist in the UCLAElectrical Engineering Departmentfrom 1994 to 1996. In 2005, Dr.Zhang co-founded Beken Corpora-tion in Shanghai.

Thank you for reading the SSCSNews! Please send comments andfeedback to [email protected].

Editor’s Column continued from page 2



As I walked out of that confer-ence room in the ShanghaiRiverfront Business Hotel on

23 June, 2008, I was so impressed bythe enthusiasm of the audience of300 or more, and by the quality oftheir questions, that I turned to Prof.Ping Ko, the world’s authority ondevice modeling and a pioneer inChina IC venture investment, whosaid smilingly, “Rather encouragingindeed!”

That was not just another day. OnJune 23rd, most if not all analog ICdesigners, students and engineershad gathered in Shanghai to attenda seminar on “A New TransceiverArchitecture for the 60-GHz Band,”by Prof. Behzad Razavi, a realcelebrity to the Chinese IC designcommunity.

Held at Shanghai’s Zhangjiang Hi-tech Park, one of the best technolo-gy incubators in China, the seminarwas co-sponsored by the ShanghaiAssociation for Science and Technol-ogy (SAST), the Shanghai IntegratedCircuit Industry Association (SICA),and Beken Corporation (www.bekencorp.com), an IC design houseI founded three years ago after mov-ing back to Shanghai from the States.

When I started Beken, recruitingseemed to be a daunting task, as thetalent pool was small at best andwas hunted by an unprecedentednumber of design houses in thecountry. Three years had passedand, judging from the size and cal-iber of the audience in Prof. Razavi’sseminar, I had no doubt that indus-try and academia had both beenproductive in spawning a new gen-eration of analog IC designers.

June 23, 2008 was a special day

to me for yet another reason, asBeken was celebrating the ship-ment of the 10,000,000th piece of itsvery first product -- a 5.8-GHzCMOS transceiver for wireless voiceapplications. Beken's 30-peopleteam had good reason to be proudof what it had achieved within threeyears.

As a returnee entrepreneur lead-ing one of the 500-and-more ICdesign houses in China, needless tosay, I encountered challenges and

A Returnee from the US BecomesEntrepreneur in China Beken Corporation Founder Muses about the IC Community in Shanghai

Pengfei Zhang, Beken Corporation, Shanghai [email protected]

More than 300 engineers -- virtually the entire analog IC design community inShanghai – gathered in June to hear SSCS DL Behzad Razavi speak on “A NewTransceiver Architecture for the 60-GHz Band.”

From left, Prof. Zi Xue, Vice General Secretary of Shanghai’sIntegrated Circuit Association, Prof. Ping Ko, Prof. BehzadRazavi, and Pengfei Zhang.

The author at Beken Corporation.



difficulties constantly, and tastes ofsuccess, too, sometimes with a bit ofluck. It has been an exciting journeythat I am happy that I made thedecision to start. Nothing can com-pare to the excitement of seeingone's own design go into millions ofproducts that could indeed makepeople’s lives easier; this of courseis on top of the sense of fulfillmentthat a great team has been built andtrained.

So that's me. After graduatingfrom Tsinghua University in Bei-jing, China with a Ph. D. in micro-electronics in 1994, I luckily hadthe opportunity to work on shal-low junction formation and SOIdevice modeling as a post doctor-al fellow in Prof. Jason Woo'sgroup at UCLA for two yearsbefore I joined the industry, work-ing for Rockwell SemiconductorSystems, Fujitsu MicroelectronicsInc., and later Resonext Communi-cations, a startup in San Jose striv-

ing to deliver the most cost effec-tive CMOS solution for then newlyemerged IEEE 802.11a WLAN stan-dard. That's where I began myRFIC design career, which led to adesign engineering manager's jobat RF Micro Devices after its acqui-sition of Resonext in 2002. Pursu-ing the dream of being part of therapid development of China’s ICindustry, I returned to Shanghaiwith a group of friends after morethan ten years in the UnitedStates.

Deeply submerged in the world'slargest consumer market, inside afast-growing design community withintensive semiconductor supplychain contacts and an extremelyactive capital market, I plan toreport my first hand observations inmy column for readers of the IEEESSCS News.

In the winter issue of 2009, I willbe looking at various exit optionsfor IC Investment in China, especial-

ly the prospect of a China domesticstock market and, more interesting-ly, a Taiwan stock market (if openedto the mainland – a progressivelygreater possibility, as the newlyelected leader in Taiwan seems tohave more practical views). One ofthe corner stones of the prosperityof China’s IC business is the uniqueecosystem in China’s Pearl RiverDelta -- a topic which will be thefocus of my attention in the 2009Spring issue.

In the Summer of 2009, I plan toshare some observations on productdefinition and marketing strategiesfor an IC design house by focusingon platforms.

In the Fall 2009 issue, I will beexamining the current IC designindustry in China and its competi-tive dynamics, as well as theprospects of the China IC designbusiness.

So stay tuned to the east side ofthe globe!



Solid-State Circuits Magazine andRedesigned Website to Launch in 2009Anne O’Neill, SSCS Executive Director, [email protected]

The SSCS Newsletter will morphinto the IEEE Solid-State Cir-cuits Magazine with the winter

issue of 2009, along with a revampedwebsite that will debut in earlyDecember, 2008.

New Magazine to Prioritize EducationAccording to a survey in 2002, Soci-ety members want more education-al material. The IEEE Solid-State Cir-cuits Magazine will be the deliveryvehicle for achieving that goal.

As the successor of the quarterlySSCS Newsletter, each issue of theMagazine will continue to be a self-contained resource for fundamentaltheories and practical advanceswithin the field of Integrated Cir-cuits (ICs); thanks to Newsletter Edi-tor-in–Chief, Mary Lanzerotti, thefounding fathers of IC fundamentalshave been telling us how it all start-ed. Mary was the driving forcebehind the evolution of the SSCSNews into a full-color, magazine-style publication and will becomeEditor-in-Chief of the Magazine.

Written at a tutorial level and ide-ally in narrative style, it will featurearticles by leaders from industry,academia and government thatexplain historical milestones, cur-rent trends and future develop-ments to provide technical informa-tion to practitioners in the field whootherwise may have insufficientresources for keeping up to date.

Exceeding the format of theNewsletter, the Magazine will offertutorials, special interest pieces, bib-liographies, and distillations of cut-ting-edge work from scholarly pub-lications and technical conferencepapers under the direction of Asso-ciate Editors Dick Jaeger and RakeshKumar. Newly appointed AssociateEditor Pengfei Zhang will providelocal news from the Far East andAustralia (IEEE Region 10), whileAssociate Editor Tony Harker willcontinue to represent Europe, theMiddle East and Africa (IEEE Region8). Katherine Olstein will maintaincoverage of SSCS chapter, member-ship and conference news.

First Issue to be Mailed in FebruaryTo maximize readability and readerinterest in content we’ve alreadycome to appreciate, the award win-ning IEEE Magazine staff has beenengaged to design and produce ournew publication. The print quarterlyMagazine will continue to be mailedto SSCS members at no cost. Thefirst issue will be mailed in earlyFebruary, just in time for the ISSCC.

The Magazine will also be hostedin IEEE Xplore to provide readersthe advantages of searchability, RSSfeeds, and email alerts when issuesare posted.

Non-member subscriptions in2009 will cost $25 for the print pub-lication, $10 for the electronic mag-azine in Xplore, and $30 for both.

Website Redesign Aims at CuttingEdgeThe Society’s new homepage willcarry scrollable windows listing thecontents of the current issue of theSociety’s flagship Journal of Solid-State Circuits and the new Solid-State Circuits Magazine. Best of all,it will be linkable to any recentarticle a user selects from eitherpublication.

One-Stop Shopping for Sponsored-Conference InformationThe Society’s revamped websitewill offer a comprehensive list ofSSCS-sponsored meetings. Derivedfrom the IEEE conference databaseon a regular basis, it will ensureconsistent reporting and provide a“one-stop shop” for conferencedates and locations, manuscript (orabstract) submission deadlines, andlinks to conference home pagesand conference homepages inXplore. Information for conference

organizers will include instructionsfor applying for SSCS technical co-sponsorship and how to use SSCSfor publicity.

Platform for the Latest NewsThe revamped SSCS website willalso feature breaking news aboutchapters, distinguished lectures,and IEEE conference and fieldawards, as well as new IEEE mem-ber programs like Expert Now andIEEE.tv, which offer content bySSCS experts that can be challeng-ing for members and potentialmembers to find. Additional webpages will provide useful “How to”instructions for acquiring SSCSproducts such as ISSCC Replay onDemand DVD’s and other pub-lished conference articles on disk.After the launch of the new web-site, sscs.org will be redirected to anew host at IEEE headquarters butwill retain its name.

Quarterly Email BlastsThe SSCS membership email blastwill continue to provide announce-ments about important upcomingconferences, application deadlines,and member activities on a schedulethat will be revised to maximizetheir timeliness, apart from the Mag-azine’s print calendar. More infor-mation will be announced in anemail blast in January.

FeedbackSSCS is interested in feedback fromthe IC community about our Maga-zine and website plans. Please dis-cuss the changes we have describedwith any AdCom member, or sendemail to the Executive Director,[email protected].

Parallel Processors are the Future Because Smaller Isn’t Cool Just as CPUs are becoming more parallel instead of smaller, so is newsfor the IC community. With the launch of our new Magazine and web-site, everyone will be able to receive email alerts for the Society and printversions of the JSSC and Solid-State Circuits Magazine. Or they can sim-ply check-out the Society website for links to it all.



TECHNICAL LITERATURE

Bell’s Law for the Birth and Death of ComputerClasses: A theory of the Computer’s Evolution1

Gordon Bell, Microsoft Research, Silicon Valley

IntroductionIn 1951, a person could walk inside a computer andby 2010 a single computer (or “cluster’) with millionsof processors has expanded to building size. Moreimportantly, computers are beginning to “walk” insideof us . These ends illustrate the vast dynamic rangein computing power, size, cost, etc. for early 21st cen-tury computer classes.

A computer class is a set of computers in a partic-ular price range with unique or similar programmingenvironments (e.g. Linux, OS/360, Palm, Symbian,Windows) that support a variety of applications thatcommunicate with people and/or other systems. Anew computer class forms roughly each decade estab-lishing a new industry. A class may be the conse-quence and combination of a new platform with anew programming environment, a new network, andnew interface with people and/or other informationprocessing systems.

Bell’s Law accounts for the formation, evolution,and death of computer classes based on logic technol-ogy evolution beginning with the invention of thecomputer and the computer industry in the first gen-eration, vacuum tube computers (1950-1960), secondgeneration, transistor computers (1958-1970), throughthe invention and evolutions of the third generationTTL and ECL bipolar Integrated Circuits (1965-1985),and the fourth generation bipolar, MOS and CMOS ICsenabling the microprocessor, (1971) represents a“break point” in the theory because it eliminated theother early, more slowly evolving technologies.Moore’s Law (Moore 1965, revised in 1975) is anobservation about integrated circuit semiconductorprocess improvements or evolution since the first ICchips, and in 2007 Moore extended the prediction for10-15 more years:

Transistors per chip = 2(t-1959) for 1959 ≤ t ≤ 1975; 216

x 2(t-1975)/1.5 for t ≥ 1975.

In 2007, Moore predicted another 10-15 years ofdensity evolution. The evolutionary characteristics ofdisks, networks, display, and other user interface tech-nologies will not be discussed. However for classes toform and evolve, all technologies need to evolve inscale, size, and performance, (Gray, 2000) though atcomparable, but their own rates!

In the first period, the mainframe, followed by min-imal computers, smaller mainframes, supercomputers,and minicomputers established themselves as classesin the first and second generations and evolved with

the 3rd generation integrated circuits c1965-1990. Inthe second or current period, with the 4th generation,marked by the single processor-on-a-chip, evolvinglarge scale integrated circuits (1971-present) CMOSbecame the single, determinant technology for estab-lishing all computer classes. By 2010, scalable CMOSmicroprocessors combined into powerful, multipleprocessor clusters of up to a million independentcomputing streams will certainly exist. Beginning inthe mid 1980s, scalable systems have eliminated andreplaced the previously established, more slowlyevolving classes of the first period that used intercon-nected bipolar and ECL ICs. Simultaneously smaller,CMOS system-on-a-chip computer evolution hasenabled low cost, small form factor or cell phonesized devices; PDA, cell phone, personal audio (andvideo) device (PAD, PA/VD), GPS and camera con-vergence into a single platform has become theworldwide personal computer, c2010. Dust sizedchips with a relatively small numbers of transistorsenable the creation of ubiquitous, radio networked,implantable, sensing platforms to be part of every-thing and everybody as a wireless sensor networkclass. Field Programmable Logic Array chips with 10s-100s of million cells exist as truly universal devices forbuilding “anything”.

Bell’s Law Origin & Motivation—The Computer His-tory Museum, a By-productIn 1966, after six years as a computer engineer at Dig-ital Equipment Corporation, designing the first com-puters that established the minicomputer industry andthe first timesharing computers, I joined the faculty ofCarnegie Mellon University. While mentoring me forsix years, Allen Newell and I wrote Computer Struc-tures: Readings and Examples (Bell & Newell, 1971)which posited notations to describe computers, theirbehavior, and a taxonomy of computers includingtheir constituent components. Working with Newellstimulated a deep concern about the origin of com-puters, classifying them (e.g. size, function, price, per-formance), and especially their evolution. Several ofus wrote a paper (Bell et al, 1972) that showed com-puters were falling into several different price bandsover time, similar to other manufactured goods e.g.cars, planes and in addition, new computers werebeing introduced in lower price bands afforded by thelogic and memory technology.

On returning to Digital in 1972 as its VP of Engi-neering, I started collecting computer logic and mem-ory technology in my office. Simultaneously, KenOlsen, acquired two historically important MIT com-puters: Whirlwind (c1951), and TX-0 (c1956) that

1 An abridged version of this paper has appeared in the Communications of

the ACM, Vol. 51, No. 1, January 2008.


Fall 2008 © 2008 IEEE IEEE SSCS NEWS 9


should be preserved for history, and that might bepart of some eventual display. In 1975, I curated anexhibit of logic and memory in a converted coat clos-et of Digital’s main office building, Maynard, MA thateventually moved and occupied the lobby of at Marl-boro MA. Maurice Wilkes opened the Digital Com-puter Museum there in 1979.

As head of engineering and curator of a potentialComputer Museum, I first spoke at MIT and else-where (Bell, 1972) about the future of computingbased on logic technology. It also became clear thatonce established, a class stays roughly constant price.I used this basic idea to look back in time to createearly generations: manual (1600-1800), mechanical(1800-1890), electro-mechanical (1890-1930, vacuumtube (1930-1960), transistor (1959-1966), integratedcircuit 1966-1990), microprocessor (1971-present). In1980 I gave a talk at Stanford’s First Forsythe Lecture,“Generating Computer Generations” describing mytheory on computer classes based on structure, tech-nology, need, and actual use that has since beenrefined as I describe.

The museum became a public 501c(3) institutionwhen it opened in Boston in 1983. In 1995 the arti-facts moved to Silicon Valley, as the Computer Histo-ry Museum, Mountain View, CA.

Bell’s LawA computer class is a set of computers in a particu-lar price range defined by: a programming environ-ment e.g. Linux, Windows to support a variety ofapplications including embedded apps; a network;and user interface for communication with otherinformation processing systems including peopleand other information processing systems. A classestablishes a horizontally structured industry com-posed of hardware components through operatingsystems, languages, application programs andunique content e.g. databases, games, pictures,songs, video that serves a market through variousdistribution channels.

The universal nature of stored program comput-ers is such that a computer may be programmed toreplicate function from another class. Hence, overtime, one class may subsume or kill off anotherclass. Computers are generally created for one ormore basic information processing functions– stor-age, computation, communication, or control (seeFigure1 Taxonomy). Market demand for a class andamong all classes is fairly elastic. In 2010, the num-ber of units sold in classes vary from 10s, for com-puters costing around $100 million to billions forsmall form factor devices e.g. cell phones selling forunder $100. Costs decline by increasing volumethrough manufacturing learning curves (i.e. dou-bling the total number of units produced result incost reduction of 10-15%). Finally, computingresources including processing, memory, and net-work are fungible and can be traded off at variouslevels of a computing hierarchy e.g. data can beheld personally or provided globally and held onthe web.

The class creation, evolution, and dissolutionprocess can be seen in the three design styles andprice trajectories and one resulting performance tra-jectory that threatens higher priced classes: anestablished class tends to be re-implemented tomaintain its price, providing increasing perform-ance; minis or minimal cost computer designs arecreated by using the technology improvements tocreate smaller computers used in more special ways;supercomputer design, i.e. the largest computers ata given time, come into existence by competing and“pushing technology to the limit” to meet theunending demand for capability; and the inherentincreases in performance at every class, includingjust constant price, threaten and often subsumehigher priced classes.

All of the classes taken together that form thecomputer and communications industry shown inFigure 2, behave generally as follows:

1. Computers are born i.e. classes come into exis-tence through intense, competitive, entrepre-neurial action over a period of 2-3 years tooccupy a price range, through the confluenceof new hardware, programming environments,

Figure 1. Taxonomy of computer functions (applications)taxonomy divided into personal and non-personal, i.e.institutional infrastructure computers that carry out calcu-lation, record keeping and transaction processing, net-working and personal communication (e.g. word process-ing, email, web), control, personal health, and entertain-ment functions. Note the convergences: personal mediadevice, PDA, camera, cell phone become the Smart Phone;Entertainment devices of TV, Media Centers & Servers.

Figure 2. evolving computer classes based on technologyand design styles: 1. constant price, INcreasing Perfor-mance; 2. sub-class, lower price and performance toextend range; 3. supercomputer – largest computers thatcan be built that extend performance; and 4. new, mini-mal, order of magnitude lowe priced class formationsevery decade.




networks, interfaces, applications, and distribu-tion channels. During the formation period, 10sto 100s of companies compete to establish amarket position. After this formative and rapidgrowth period, 2 or 3, or a dozen primary com-panies remain as a class reaches maturitydepending on the class volume.

2. A computer class, determined by a unique pricerange evolves in functionality and graduallyexpanding price range of 10 maintains a stablemarket. This is followed by a similar lowerpriced sub-class that expands the range anoth-er factor of 5 to 10. Evolution is similar to New-ton’s First Law (i.e. bodies maintain theirmotion and direction unless acted on external-ly). For example, the “mainframe” class wasestablished in the early 1950s using vacuumtube technology by Univac and IBM and func-tionally bifurcated into commercial and scien-tific applications. Constant price evolution fol-lows directly from Moore’s Law whereby agiven collection of chips provide more transis-tors and hence more performance.

A lower entry price, similar characteristicssub-class often follows to increase the class’sprice range by another factor of 5 to 10, attract-ing more usage and extending the market. Forexample, smaller “mainframes” existed within 5years after the first larger computers as sub-classes.

3. Semiconductor density and packaging inher-ently enable performance increase to support atrajectory of increasing price and function

3.1 Moore’s Law single chip evolution, ormicroprocessor computer evolution after1971 enabled new, higher performingand more expensive classes. The initialintroduction of the microprocessor at asubstantially lower cost accounted forformation of the initial microcomputerthat was programmed to be a calculator.This was followed by more powerful,more expensive classes forming includ-ing the home computer, personal com-puter, workstation, the shared micro-computer, and eventually every higherclass.

3.2 The supercomputer class c1960 wasestablished as the highest performancecomputer of the day— however, sincethe mid-1990s supercomputers areformed by combining the largest num-ber of high performance computers toform a single, clustered computer sys-tem in a single facility. In 2010 over amillion processors will likely constitutea cluster. Geographically coupled com-puters including GRID computing e.g.SETI@home are outside the scope.

4. Approximately every decade a new computerclass forms as a new “minimal” computereither through using fewer components or use

of a small fractional part of the state-of-the-artchips. For example, the 100 fold increase incomponent density per decade enables smallerchips, disks, screens, etc. at the same function-ality of the previous decade especially sincepowerful microprocessor cores e.g. the ARMuse only a few <100,000 transistors versus overa billion for the largest Itanium derivatives. Minimal computers design. Building the small-est possible computer accounts for the creationof computers that were used by one person ata time and were forerunners of the workstatione.g. Bendix G-15 and LGP 30 in 1955, but thefirst truly personal computer was the 1962 Lab-oratory Instrument Computer (LINC). LINC wasa self-contained computer for an individual’ssole use with appropriate interfacial hardware(e.g. keyboards, displays), program/data filingsystem, with interactive program creation andexecution software. Digital Equipment’s PDP-1(1961), followed by its more “minimal” PDP-5& 8 established the minicomputer class thatwere predominately designed for embeddedapplications.System-on-a-Chip (SOCs) use a fraction of achip for the microprocessor(s) portion or“cores” to create classes and are the basis offixed function devices and appliances begin-ning in the mid 1990s. These include cameras,cell phones, PDAs, PAD (personal audio &video devices) and their convergence into asingle cell phone sized device (CPSD) or smallform factor (SFF) package. This accounts forthe PC’s rapidly evolving microprocessor’s abil-ity to directly subsume the 1980’s workstationclass by 1990.

5. Computer classes die or are overtaken by lowerpriced, more rapidly evolving general purposecomputers as the less expensive alternativesoperating alone, combined into multipleshared memory micro-processors, and multiplecomputer clusters. Lower priced platformsresult in more use and substantially higher vol-ume manufacture thereby decreasing costwhile simultaneously increasing performancemore rapidly than higher priced classes.

5.1 Computers can be combined to form asingle, shared memory computer. A“multi” or multiple CMOS microproces-sor, shared memory computer displacedbipolar minicomputers c1990 and main-frames c1995, and formed a componentfor supercomputers.

5.2 Scalable, multiple computers can be net-worked into arbitrary large computer toform “clusters “that replace custom ECLand CMOS vector supercomputersbeginning mid 1990s simply becausearbitrarily large computers can be creat-ed. Clusters of multiprocessors werecalled constellations; clusters using lowlatency and proprietary networks are



TECHNICAL LITERATUREMPPs (massively parallel processors).

5.3 Generality ALWAYS Wins! A computerscreated for a particular, specializedfunction e.g. word processing, interpret-ing a language, used for a particularapplication is almost certain to be takenover by a faster evolving, general pur-pose computer. The computer’s univer-sality property allows any computer totake on the function of another, givensufficient memory and interfaces.

5.4 Small form factor devices subsume apersonal computing functionality asthey take on the communications func-tions of the PC (e.g. email and webbrowsing), given sufficient memory andinterfaces. Small form factor devices ortelevision sets or kiosks accessingsupercomputers with large stores, sub-sume personal computing functionality.The large central stores retain personalinformation, photos, music, and video.

The paper will describe how these characteristicsof the classes account for the birth, growth, diminu-tion, and demise of various parts of the computersand communications industry.

Overview of the Birth and Death of the ComputerClasses 1951-2010Figure 1 is a computer function taxonomy based:first on buyers/users and second, by application.The information processing elements i.e. applica-tion functions are: memory or storage for recordkeeping that was the province of IBM and othercard tabulation equipment makers prior to thecomputer’s invention; computation or calculationcharacterizing science and engineering use; net-working and communication that provide theinterconnection infrastructure; control of other sys-tems (e.g. process control); and interface withhumans and other information processing entities.

The taxonomy is divided first into personal andnon-personal or invisible and shared, institutionalinfrastructure systems that would be operatedwithin or for a company, government or institutionas a service. This dichotomy of personal versusshared; invisible versus institutional determinescharacteristics of price and scale, programmingenvironment, user interface, and network. Func-tion though critical, will be neglected.

The named classes and their price range c2010 isgiven in Figure 3. David Nelson, founder of Apollo.and I (Nelson, Bell 1986) posited that the price of acomputer was roughly $200 per pound. Figure 4gives the introduction price and date of the first ordefining computer of a class. Table 1 gives thedefining constituent technologies, operating sys-tems, languages, networks, and interfaces of thevarious classes.

The discussion will use the aspects of Bell’s Lawdescribed above and follow a timeline of the classformations beginning with the establishment of thefirst computer classes (mainframe, supercomputer,shared personal professional computers or worksta-tions, and minicomputers) using vacuum tubes,transistors, and bipolar integrated circuits that con-tinue through the mid 1990s. The MOS micro-processor introduced in 1971 ultimately overtookbipolar by 1990 to establish a single line based onCMOS technology.

The section is followed by the three direct andindirect effects of Moore’s Law to determine classes:

1 Microprocessor transistor/chip evolution c1971-1985 establish: calculators, home computers,personal computers and workstations, andlower (than minicomputer) priced computers.

2 “Minimal” designs establish new classes c1990that use a “fraction” of the Moore number.Microsystems evolution using fractional Moore’sLaw sized SOCs enable small, lower perform-ing, minimal personal computer and communi-cation systems including PDAs, cameras, cellphones, personal audio/video devices.

3 Rapidly evolving microprocessors using CMOSand a simpler RISC architecture appear as the“killer micro” c1985 to have the same per-formance as supercomputers, mainframes,mini-supercomputers, super-minicomputers,and minicomputers built from slowly evolving,low density, custom ECL and bipolar integrat-ed circuits. ECL survived in supercomputersthe longest because of its speed and ability todrive the long transmission lines, inherent inlarge systems. In the end, CMOS density andfaster system clock overtook ECL as shown inFigure 5.

The “killer micro” enabled by fast floating pointarithmetic, first subsumed the workstation followedby the minicomputer especially when combined toform the “multi” or multiple microprocessor sharedmemory computer c1985. “Multis” became the com-ponent for scalable clusters when interconnected byhigh speed, low latency networks. Clusters allow

Figure 3. Computer Classes and their Price Range 2005




arbitrarily large computers that are limited only bycustomer budgets. Thus scalability allows everycomputer structure from a few thousand dollars toseveral hundred million dollars to be arranged intoclusters built from the same components.

In the same fashion that killer micros sub-sumed all the computer classes by combining, itcan be speculated that much higher volume, hun-

dreds of millions, of small form factor devices,may evolve more rapidly to subsume a large frac-tion of personal computing. Finally tens of bil-lions of dust sized, embeddable wirelessly con-nected platforms that connect everything arelikely to be the largest class of all enabling thestate of everything to be sensed, effected, andcommunicated with.



TECHNICAL LITERATUREThe Past: How we got here

The Beginning (1951-1990): mainframe, super-computer, shared personal workstation, andminicomputer classes

By 1970, vacuum tube (50s), transistor (60s), andsmall scale integrated circuit (late 60s) technologiesenabled the establishment of four classes of com-puters that continued almost without change untilthe 80s:

1. Mainframes for commercial, record keeping,etc. and mainframes for Scientific and Engi-neering Computation were the very first com-puters; a sub-class of smaller computersformed that were used in the same fashion.

2. Minimal design, small, shared computers thatwere used directly as personal workstations

3. Minimal computers for process and machinecontrol, communication, and embedded apps

4. Supercomputers constructed at the limits of cir-cuit, interconnect, and architectural complexityutilizing clock speed and parallelism

Eckert and Mauchly, operating as the UNIVACdivision of Remington Rand delivered the UNIVAC 1as the earliest commercial computer in 1951, rough-ly concurrent with the British LEO (Lyons Electron-ic Office) computer, and followed two years later bythe IBM 701 (1953) for scientific applications. Thesefirst computers with delay line and electrostatic(Williams Tube) memories of only a few thousandwords were priced at $1 million or more ($8.5 mil-lion in 2007 dollars) to establish the mainframeclass. By 1955, IBM had introduced both scientific(701, 704) and commercial (702, 705) computersthat were differentiated by their ability to deal withfloating point data of high precision versus the pre-dominately alphanumeric and decimal arithmeticoperations typifying data processing. From thegraph, the mainframe increased to $4 million andcontinued to maintain the price range. A set ofsmaller computers were introduced in the price$0.1- 1 million range e.g. IBM 1401 and 650 fordepartmental and smaller organization use. Thesecould be classified as subclass of mainframes orsuper-minicomputers. During the mainframe’s for-mation, eight US and five? European companiescompeted to establish the class. The US Group wasknown as Snow White and the Seven Dwarfs orBUNCH (Burroughs, Univac now Unisys, NCR, CDC,Honeywell)+ GE & RCA. With IBM’s introduction ofSystem 360 on April 7, 1964, the dominant architec-ture was established and will doubtlessly remain torun legacy applications “forever” – given the tril-lions of dollars of software and data that this ecosys-tem hosts.

Small or minimal computers priced between$60,000 to $120,000 that a person signed up for andused directly for calculation or personal computingat work were introduced beginning in the mid 1950s(Bendix G-15, Librascope LGP-30), as well as thetransistorized IBM 1620 that dominated the class. In1961, the DEC PDP-1 was applied to telegraph linemessage switching as a prelude to computer net-

Figure 4. Introduction price versus date of the first or earlyplatforms to establish a computer class or lower pricedsub-class orginating from the same company or industry.

Figure 5. Faster evolving CMOS microprocessors are ableto overtake and eliminate slowly evolving TTL and ECLbipolar integrated circuit based computer classes includ-ing minicomputers, superminicomputers, mini-supercom-puters, mainframes, and supercomputers. A number ofcompanies built one or more Too many ECL computersincluding CDC, Cray, DEC, Fujitsu, Hitachi, and IBM beforeswitching to ECL.




working, peripheral computers for mainframes (likethe 1401 or CDC 160), and were used as prototypesfor timesharing system.

The PDP-8, introduced in 1965 at a price of $18Kis the first “minicomputer.” It was minimal, designedas both the smallest computer that could be builtand as a component to be used for controlling otherdevices e.g. process control, lab instruments, termi-nal concentrators. On occasion it was used as aworkstation on a personal basis with an operatingsystem that was a pre-cursor to DOS. The PDP-8had a dozen implementations following a minimalcost trajectory with single chip versions beginningin 1975 to both define and increase its marketabili-ty including its use as a dedicated word processorto the early 1980s. During the minicomputer classformation period, 92 companies formed to establishthe minicomputer class with only IBM and HPremaining by 2000 to make computers in this classalbeit with substantially changed architectures.Including DEC VAX in this class, the price rangeincreased to cover a range of $10,000 to $1,000,000servers and covering the entire potential applicationspace of the day. The most expensive VAXen, andVAX clusters competed with IBM smaller System/360class and sub-mainframes.

The reliable and fast transistor circuitry c1960enabled a substantially larger number of compo-nents to be integrated into a unified system, limitedmostly by the maximum feasible selling price, archi-tectural complexity, and interconnection density.Early on, vying for the title of world’s fastest com-puter, were the Manchester Atlas I and the IBM 7030(“Stretch”), both introduced in 1961. Five years later,the CDC 6600 supercomputer was introduced as theculmination of several years of effort by a smallteam led by Seymour Cray. It used about 500,000densely packaged silicon transistors and stunnedthe world with its performance—easily an order ofmagnitude faster than any computer shipping at thetime or even being contemplated. “Cray sytle” com-puters based on parallelism functional units, fol-lowed by vector processors continued relativelyunchallenged for 30 years. In the mid-90s, thingshad changed somewhat architecturally but bipolartechnology still reigned. The fastest machines wereshared memory, vector processors using small scaleECL ICs. Successful challengers at Fujitsu and NECuses the “Cray” formula to build even fastermachines with the NEC Earth Simulator holding thetitle from 2002-2005.

Why Computer Classes Evolve at Constant Price,Increasing PerformanceOnce a computer class forms, several factors deter-mine the price of the “next” evolutionary model.Building the next model in 3-5 years with chips thathave 4 to 6 times more transistors is the natural pre-dicted progression of Moore’s Law.

Increases in processing power and memory sizeare essential for the new data-types such as music,photos, and data-bases. The number of pixels per

camera evolve about as rapidly as Moore’s Law,requiring more memory and speed to handle theimages with constant response. Similarly, disk mem-ories have to evolve rapidly to store the higher res-olution photos, higher quality videos, etc.

Nathan’s Law, also attributed to Bill Gates,explains software’s increasing demand forresources:

1. Software is a gas. It expands to fill the con-tainer it is in.

2. Software grows until it becomes limited byMoore’s Law.

3. Software growth makes Moore’s Law possiblethrough the demand it creates; and

4. Software is only limited by human ambitionand expectation.

“Marketing” nominally fueled by user feedbackfor more functionality, forms the critical link in sup-port of Nathan’s Law that minimalist refer to as fea-turitis, bloat, etc. enabling upgrades to support peri-odic obsolescence.

We might expect to buy a new computer in threeyears at 1/4 the price of today’s computer usingchips that are 1/4 the size of an earlier model per-haps from the same manufacturer. Why not? Newmicroprocessors sell at the same or even a pricepremium because they have 4x the transistors, fasterclock speed and deliver more performance. Forexample, Intel and AMD are not inclined to buildmicroprocessors with less transistors and lower costbecause they don’t see such a market – and as suchdo not participate in establishing the new, lowerprice classes. Also, a computer is made of otherparts e.g. metal and power supplies that mayincrease in price and act to hold the system priceconstant with only system manufacturing learningcurves left to decrease price.

The “numbers” support a next generation productof constant price and increasing performance, notone of decreasing prices and constant performance.Assume the total cost of ownership is at least 3x thecomputer’s sales price, and for a computer of per-formance = 4.

performance/total cost = 4/4 Assume a new, constant price, double perform-

ance computer performs at 4 x 2 or 8, then Performance/total cost = 8/4 or 2. Contrast this

with a constant performance computer of 4, whoseprice is just 3/4, giving a total cost of 3.75

Performance/Total cost = 4/3.75 or 1.07The final and most important incentive to hold

price constant and provide more capability is toretain a user’s substantial investment in legacyapplications and data that have been created togeth-er with the implied user and organizational learning.The value of data is most likely to be 10-100 timesthe hardware cost. A user retains an old computerunless it is unreliable, or there is a substantialincrease in functionality – as long as the new modelaccepts legacy apps and data. The cost to switch toanother computer, even with the same capability isso high that the incentive must result in a significant



TECHNICAL LITERATUREbenefit as the above numbers show.

Finally, most goods e.g. cars, construction materi-al, energy, and food not subject to CMOS integra-tion, increase in price with inflation (Table 2). How-ever, computers have defied inflation -- the 1984, 9”monochrome 128 Kbyte, single floppy, integrated$2495, Apple Macintosh costs $1500; in 2007, thesame, as a 13” color portable with 1 GB memoryand 80 GB disk.

Table 2. Consumer Price Index showing Buying Power sincethe introduction of computers in 1951 Versus $1 in 2007.

1950 1960 1970 1980 1990 2000 20078.5 6.9 5.3 2.5 1.6 1.2 1

Microprocessors 1971: The Technological Force forNew Classes in the Second PeriodFigure 6 shows the microprocessors derived directlyfrom the growth of transistors/chip beginning in 1971.It shows the trajectory of microprocessors from a 4-bitdata path through, 8-, 16-, 32-, and 64-bit data pathsand address sizes. The figure shows a second path –the establishment of “minimal” computers that use lessthan 50 thousand transistors for the processor, leavingthe remainder of the chip for memory and other func-tions e.g. radio, sensors, analog I/O enabling the com-plete SOC. Increased performance, not shown in thefigure, is a third aspect of Moore’s Law that allows the“killer micro” formation to subsume all the other, highperformance classes that used more slowly evolvingbipolar TTL and ECL ICs (Figure 5). The final sectionwill discuss the challenge of having a single chip withbillions of computing elements (functional units,processors, computers, wireless links and other I/O).

Microprocessor Evolution c1971-1985: Personal Com-puting (Calculators, Home Computers, Personal Com-puters, Workstations, and Game Console Platforms)Calculators, home computers, personal computers,and workstations were established as classes as theprocessor on a chip evolved to have more transistorswith wide data paths and large address spaces asshown in Figure 6.

In 1971, Intel’s 4004 with 4 bit data path and abili-ty to address 4KB was developed and programmed tobe the Busicom Calculator; instead of developing aspecial chip as had been customary to implement cal-culators, a program was written for the 4004 for it to“behave” as or “emulate” a calculator. The 4004 witha 4 bit data path was not suited for storing text andlarger numbers other than in a serial fashion, althoughit was used for numerous applications and to spawnan “embedded computer” market just as the mini-computer had done a decade earlier.

In 1972, Intel introduced the 8008 microprocessorcoming from the Datapoint terminal requirement,with 8 bit data path and ability to access 16 KB thatallowed R2E’s Micral computer (France) and Scelbi tobuild limited, programmable computers followed bymore powerful 8080-based systems that M.I.T.S. usedto introduce its “Atltair” personal computer kit in1975, that incidentally stimulated Gates and Allen tostart Microsoft. The more powerful and upward com-patible Zilog Z80 was useful in helping to establish apersonal computing platform. In 1977, the 16-bit 6502microprocessor and higher-capacity memory chipsenabled personal computers for use in the home orclassroom built by Apple, Commodore and RadioShack—computers that sold in the tens of millionsbecause people bought them to use at home versuscorporate buyers. By 1979, the VisiCalc spreadsheetran on the Apple II establishing it as a “killer app” forpersonal computers in a work environment. Thus thetrajectory went from a 4-bit data path and limitedaddress space to a 16-bit data path with the ability toaccess 64KB of memory. This also demonstrates theimportance of physical address as an architecturallimit. In the paper on DEC’s VAX (Bell, Strecker 1975),we described the importance of address size on archi-tecture: “There is only one mistake that can be madein a computer design that is difficult to recover from– not providing enough address bits for memoryaddressing and memory management…” The8086/8088 of the first IBM PCs had a 20-bit, or 1MBaddress space, the operating system using the remain-ing 384KB.

Concurrent with the introduction of the IBM PC,professional workstations were being created thatused the Motorola 68000 CPU with its 32-bit data andaddress paths (4GB of maximum possible memory).Apple Computer used the Motorola “68K” in its Lisaand Macintosh machines. IBM’s decision to use thelntel architecture with limited addressing, undoubt-edly had the effect of impeding the personal com-puter by a decade as the industry waited for Intel toevolve architecture to support a larger address andvirtual memory space. Hundreds of companies start-

Figure 6. Moore’s Law that provides more transistors perchip, has resulted in creating the following computer class-es: calcultaors, home computers, personal computers, work-stations, “multis” to overtake minicomputers, and clustersusing multiple core, multi-threading to ovetake mainframesand supercomputers.




ed up to build Personal Computers (“PC-clones”)based on the IBM PC reference design c1981. Dozensof companies also started to build workstations basedon a 68K CPU running the UNIX operating system.This was the era of “JAWS” (Just Another WorkSta-tion) to describe efforts at Apollo, HP, IBM, SGI, SUNand others based on 32-bit versus 16-bit micro-processors and including specialized systems forWord Processing (Wang, Xerox), Market Analysis(Metaphor), CAD (Intergraph, Daisy, Valid), andhigh-level programming (Lisp Machines and Symbol-ics). Virtually all of these “workstations” were elimi-nated by simple economics as the Personal Comput-er--based on massive economies of scale and com-moditization of both the operating system and allconstituent hardware elements) evolved to have suf-ficient power and pixels.

“Minimal” CMOS Microsystems on a Chip c1990Establish New Classes Using Smaller, Less Expen-sive, ChipsIn 2007, many systems are composed of microproces-sor components or “cores” with less than 50,000 tran-sistors per microprocessor core at a time when theleading edge microprocessors chips have a billion ormore transistors cf Figure 6. Such cores using lowercost, less than the state-of-the-art chips and highly-effective, rapid design tools allow new, minimal class-es to emerge allow new, minimal classes to form.PDAs, cameras, cell phones, and personal audio &video devices have all been established using this“minimal” computer design style based on small“cores”. In 1990, the Advanced RISC Machine (ARM)formed from a collaboration between Acorn andApple as the basis for embedded systems that areused as computing platforms and achieve two billionunits per year in 2006. Other higher volume microsys-tem platforms using 4-, 8-…64-bit architecturesincluding MIPS exist as core architectures for buildingsuch systems as part of the very large “embedded”market.

Rapidly Evolving “Killer CMOS Micros” c1985 Over-take Bipolar ICs to Eliminate Established ClassesIn the early 1980s, the phrase “killer micro” wasintroduced by the technical computing community asthey saw how the more rapidly evolving CMOS microwould overtake bipolar based minis, mainframes,and supers if they could be harnessed to operate asa single system and operate on a single program orworkload.

In the Innovator’s Dilemma, Christensen describesthe death aspect basis of Bell’s Law by contrastingtwo kinds of technologies. Sustaining technologyprovides increasing performance enabling improvedproducts at the same price as previous models usingslowly evolving technology; disruptive, rapidly evolv-ing technology provides lower priced, products thatare non-competitive with higher priced sustainingclass to create a unique market space. Over time, theperformance of lesser performing, faster evolving

products eventually overtake the established, slowlyevolving classes served by sustaining technology.

From the mid 1980s till 2000, over 40 companieswere established and wiped out attempting to exploitthe rapidly evolving CMOS microprocessors by inter-connecting them in various ways. Only Cray, HP, IBM,SGI and SUN remain in 2007 to exploit massive par-allelism through running a single program on a largenumber of computing nodes.

Let’s look at two potentially disruptive technolo-gies, establishing new classes:

The OLPC (One Laptop Per Child) project ofNicholas Negroponte aimed at a $100 PC (costingabout $188 in 2007) is quite likely disruptive as a“minimal” PC platform that relies on the internet forstorage of programs and data. Cost reduction isachieved by substituting 500 MB of flash memoryfor disk, reduced screen size, small main memory,and built in mesh networking to reduce infrastruc-ture cost. An expected selling price of $200 with a$188 cost that is about half the price of the leastexpensive PCs in 2007, is characteristic of a newsub-class. OLPC will be an interesting developmentsince Microsoft’s Vista requires almost an order ofmagnitude more system resources.

The evolving small form factor devices such ascell phones are likely to have the greatest impacton personal computing, effectively creating aclass. For perhaps most of the 4 billion non-PCusers, it becomes their personal computer andcommunicator, wallet... map, etc. since the mostcommon and often only use is of personal com-puters is for email and web browsing – both state-less applications.

Application of Bell’s Law-- Planning VAX and theVAX StrategyIn 1975 when VAX was in the planning stage, I usedthe theory of classes to posit a compatible line ofcomputers that had the same instruction set and pro-gramming environment that could be used in a rangeof uses including personal computers, process control, departmental timesharing, and clusters for largescale apps. The planning was based on the differentsized memories resulting in different prices accordingto the following pricing model:

System Price = 5 x 3 x .04 x memory size/ 1.26 (t-1972) K$

Where 5x: Memory is 20% of cost; 3x: DEC markup;.04x: $ per byte; 26%: price change

Figure 7 shows the prices for systems of varioussized memories. The large price declines were infact one of the root causes of the demise of Digitalin the late 90s. In effect, the large memoriesrequired to maintain pricing in a price bandrequired larger amounts of processing that wereserved by clusters of microprocessor based comput-ers connected as clusters. Another cause at DEC wascontinuing with ECL at a time when CMOS overtookit in speed and especially exorbitant cost whennearly zero cost, microprocessors were outperform-ing ECL.




The Challenge of Constant Price, 10-100 BillionTransistors per Chip, Multi-threaded, Multi-proces-sors, for General Purpose ComputingThe future is not at all clear how such large, leadingedge chips will be used in general purpose comput-ers as used at the desk top. As ever, the resilient andcreative supercomputing and large scale service cen-ter communities will exploit the largest multi-core,multi-threaded chips. There seems to be no upperbound these systems can utilize!

However, without high volume manufacturing, thevirtuous cycle is stopped -- in order to get the costand benefit for clusters, a high volume personal com-puter market must drive demand to reduce cost. In2007, the degree of parallelism for personal comput-ing in non-gamer desktop systems such as Linux andVista is nil either reflecting the impossibility of thetask or our lack of creativity.

Several approaches for very large transistor counti.e. 10 billion transistor chips with more than a few(e.g. 2-10) processors could be, in order of difficulty:

1. Small chips with only as many processors thatcan be gainfully employed e.g. 2-4 processorssystem with primary memory on a chip for sub-stantially reduced lower priced systems andgreater demands that either require or imply pro-portionally lower cost software

2. Graphics processing, currently handled by spe-cialized chips is perhaps the only well-definedapplication that is clearly able to exploit orabsorb unlimited parallelism in a scalable fash-ion for the most expensive PCs e.g. gaming,graphical design. In effect, this just cost reducesthe system by eliminating graphics chips.

3. Dedicated functional processing for networking,

improved user interface including speech pro-cessing for text to speech and spoken commands

4. Multi-core and multi-threaded processor evolu-tion for large, high performance scientific sys-tems that are carefully programmed using FOR-TRAN-MPI, as FORTRAN turns 50.Remodel thedesktop architectures at the language level to beable to highly parallelize apps using the vector-ization and parallelization that has proven appli-cability in the multi-vector processor machines,betting on the need

5. Develop image processing enabling “computersto see” and be controlled by motion and emo-tion using hands and face. The Nintendo Wiiseems to have something here.

6. A BKA or “BIG KILLER APP” that exploits thesestructures, EVERYONE needs, and compatiblewith our PC environment.

7. Something BIG, based on a dramatic new way toprogram e.g. Transactional Memories, FunctionalProgramming, block structured dataflow requir-ing changes in language, tools, training, and newapplications. Systems are being introduced suchas Microsoft’s F# to test this approach, and if suc-cessful imply a change akin to the introductionof objects. Software objects, requiring new appli-cation architectures may be alternative way ofthinking versus the FORTRAN-MPI model.

8. Abandoning general purposeness using FPGAsthat are programmed using inherently parallelhardware design languages like parallel C or Ver-ilog that could provide universality that we havenever before seen, and

Independent of how the chips are programmed,the biggest question is whether the high volume per-

Figure 7. Original VAX Planing model Computer Prices versus time from 1975 showing different memory sizes and result-ing prices 1964-1986. In 1998, the model was reviewed retrospecively. The price changes, though accurate, were so rapidto be unbelievable and hardly actionable.




sonal computer market can exploit anything otherthan the first three paths, and even those require care-ful programming beyond 2007 operating systems.

Let’s apply the Carver Mead 11 year rule – the timefrom discovery and demonstration till use. Perhapsthe introduction of a few transactional memory sys-tems have started the clock using a programmingmethodology that claims to be more easily under-stood. A simpler methodology that can yield reliabledesigns by more programmers is essential in order toutilize these multiprocessor chips.

In a way, the opportunity or rather need for paral-lelism is reminiscent of the 1982 Japanese Fifth Gen-eration research effort based on parallelization, AI,and PROLOG. (The Denelcor HEP was also installedthen.) This time, it’s not research. The problem needsa tractable solution. Without it, Moore’s Law slows.

Will Small Form Factor Devices Impact PersonalComputing?Users are likely to switch classes when the perform-ance and functionality of a lesser priced class is ableto satisfy their needs and still increase functionality.Since the majority of PC use is for communication andweb access, evolving a small form factor device as asingle communicator for voice, email, and web accessis quite natural. Two things will happen to acceleratethe development of the class: people who have neverused or are without PCs will use the smaller, simplerdevices and avoid the PC’s complexity; and existingPC users will adopt them for simplicity, mobility, andfunctionality e.g. wallet for cash, GPS, single device.We clearly see these small personal devices withannual volumes of several hundred million unitsbecoming the single universal device evolving fromthe phone, PDA, camera, personal audio/videodevice, web browser, GPS and map, wallet, personalidentification, and surrogate memory.

With every TV, becoming a computer display, acoupled SFF becomes the personal computer for theremaining applications requiring large screens. Cablecompanies will also provide access via this channel asTV is delivered digitally.

Ubiquitous Wireless. WiFi, Cellular Services, andWireless Sensor NetsUnwiring the connection around the computer andperipherals, TV set, etc. by high speed radio links isuseful but the app is unwiring, and not platform cre-ation. Near Field Communication (NFC) using RF ormagnetic coupling offers a new interface that can beused to communicate a person’s identity that couldform a new class for wallets and identity. However,most likely the communication channel and biometrictechnology taken together just increase the function-ality of small devices.

Wireless Sensor Nets: New Platform, Network, andApplications Ubiquity: combining the platform, wireless networkand interface into one to integrate with other systems

by sensing and effecting is clearly a new class that hasbeen forming since 2002 with a number of new com-panies that are offering – “un wiring”, and hencereduced cost for existing apps e.g. process, building,home automation and control. Standards surroundingthe 802.15.4 link that competes in the existing unli-censed RF bands with 802.11xyz, Bluetooth, andphone are being established.

New applications will be needed for wireless sen-sor nets to become a true class versus just unwiringthe world. If, for example, these chips become part ofeverything that needs to communicate in the whole IThierarchy, a class will be established. They carry outthree functions when part of a fixed environment ora moving object: sense/effect; recording of the state ofa person or object (things such as scales, appliances,switches, thermometers and thermostats) including itslocation and physical characteristics; and communica-tion to the WiFi or other special infrastructure net-work for reporting. RFID is part of this potentiallyvery large class of trillions. Just as “billions of clientsneeded millions of servers” a trillion dust wirelesssensing devices will be coupled to a billion othercomputers.

SummaryBell’s Law explains the history of the computingindustry based on the properties of computer classesand their determinants. The paper posits a generaltheory for the creation, evolution, and death of vari-ous priced-based computer classes that have comeabout through circuit and semiconductor technologyevolution from 1951. The exponential transistor den-sity increases forecast by Moore’s Law (1965,1975)being the principle basis for the rise, dominance, anddeath of computer classes after the 1971 micro-processor introduction. Classes evolve along threepaths: constant price and increasing performance ofan established class; supercomputers – a race to buildthe largest computer of the day; and novel, lowerpriced “minimal computers”. A class can be sub-sumed by a more rapidly evolving, powerful, lessexpensive class given an interface and functionality.In 2010, the powerful microprocessor will be thebasis for nearly all classes from personal computersand servers costing a few thousand dollars to scala-ble servers costing a few hundred million dollars.Coming rapidly are billions of cell phones for per-sonal computing and the tens of billions of wirelesssensor nets to unwire and interconnect everything. In1951, a man could walk inside a computer and by2010 a computer cluster with millions of processorshas expanded to building size. More importantly,computers are beginning to “walk” inside of us2.

AcknowledgementsJim Gemmell, Jim Gray , Robert Hasbun, and ChuckThacker of Microsoft; John Gustafson, Craig Mudge,Dag Spicer, Computer History Museum, and DoronSwade, British Science Museum.

2 Courtesy of Dag Spicer, Curator, Computer History Museum



TECHNICAL LITERATUREBibliography[1] Bell, C.G., A. Newell, “Computer Structures: Read-

ings and Examples” McGraw-Hill, 1971.

[2] Bell, C. G., R. Chen and S. Rege, "The Effect ofTechnology on Near Term Computer Structures,"Computer 2 (5) 29-38 (March/April 1972).

[3] Bell, C. G. On the Future of Computers. http://research.microsoft.com/~gbell/Mit288.asx A 1972 talk at M.I.T.describing a model for future computers, includingcomputer classes based on logic technology evolution.

[4] Bell, C. G., "The Mini and Micro Industries", Com-puter (17) no. 10, pp. 14-30 (October 1984).

[5] Bell, C. G., "Multis: A New Class of MultiprocessorComputers", Science, Vol. 228, pp. 462-467 (April26, 1985).

[6] Bell, G., W. Strecker, "Computer Structures: WhatHave We Learned from the PDP-11" IEEE ComputerConference Proceedings, Florida (November 1975).

[7] J. Gray, P. Shenoy, “Rules of Thumb in Data Engi-neering,” Proc ICDE200, San Diego, March 1-4,2000. IEEE press.

[8] Christensen, C.M. The Innovator’s Dilemma, Har-vard Business School Press, 1997, pp 225.

[9] Moore, Gordon E. Cramming more componentsonto integrated circuits, Electronics, Volume 8, No.39 April 19, 1965. Article predicted transistor dou-bling annually; revised 1975: 18 months doubling.

[10]Nelson, D. L., C. G. Bell “The Evolution of Work-stations”, IEEE Circuits and Devices Magazine,July 1986, pp 12-15.

About the AuthorGordon Bell has been a principalresearcher at Microsoft Research, since1995, researching the lifetime captureand storage of everything for an indi-vidual. Previous roles include VP ofR&D, Digital Equipment Corp. (1960-1983); professor, Carnegie-Mellon Uni-versity (1966-72); founding assistant

director of NSF’s Computing and Information Sciencesand Engineering (CISE) Directorate (1986-1988);chairman, cross agency committee (FCCSET) for cre-ating the Internet(1987-1988); advisor /investor in100+ start-up companies; and a founding trustee ofthe Computer History Museum, Mountain View, CA.

Since 1987 he has sponsored the Association forComputing Machinery’s (ACM) Gordon Bell Prizes forparallelism awarded annually at Supercomputing. Hehas bachelor and master of science degrees from MIT(1956-57), is a University of New South Wales Ful-bright Scholar (1957-58), has an honorary doctorate inEngineering from Worchester Polytechnic Institute(WPI) (1993), and is a fellow of the American Acade-my of Arts and Sciences (AMACAD), Assoc. for Com-puting Machinery (ACM), the Institute of Electricaland Electronics Engineers (IEEE), and the NationalAcademies of Engineering (NAE) and Science (NAS).Awards include: ACM-IEEE Eckert-Mauchly Award;the IEEE’s Computer Pioneer and McDowell Awards;the IEEE’s Von Neumann Medal; the Computer Histo-ry Museum Fellow Awards; the American ElectronicsAssociation (AEA) Inventor Award for the economiccontribution to New England; the IEEE 2001 Kara-petoff Eminent Member's Award of Eta Kappa Nu;and the 1991 National Medal of Technology "for hiscontinuing intellectual and industrial achievements inthe field of computer design and for his leading rolein establishing…computers that serve as a significanttool for engineering, science, and industry."




Ultra-Low-Power Electronics and Sub-thresholdOperationIn the near future, a number of systems will be pow-ered using energy scavenging technologies, enablingexciting new applications such as medical monitoring,toxic gas sensors and next-generation portable videogadgets. Energy harvesters typically provide outputpower in the range of 10 – 100μW, setting a constrainton the average power that can be consumed by theload circuitry for self-powered operation. This willrequire the electronic circuits to operate with utmostenergy efficiency while performing the required func-tionality. Energy minimization requires a system-levelapproach optimizing not only the signal processing andinterface circuits but also the energy processing func-tion. A major opportunity to reduce the energy con-sumption of digital circuits is to scale supply voltagesbelow 0.5V driving them to sub-threshold operation.

The idea of exploiting weak-inversion operation forlow power circuits was pioneered by Dr. Eric Vittozin the 1960’s and some history associated with thedevelopment of these circuits is featured in the Sum-mer 2008 issue. Weak-inversion circuits as proposedby Dr. Vittoz [1] have had a major impact on thedesign of micro-power integrated circuits and sys-tems. This includes not only wristwatch circuits andcalculators, but also a number of mixed-signal appli-cations such medical electronics and sensors. Thespecial MOS models developed by Dr. Vittoz and hiscolleagues were crucial for ultra-low-voltage opera-tion and weak inversion analog circuits. The earlywork was later extended to the well-known EKVmodel [2] specifically designed for low-voltage andlow-current analog circuit analysis. Based on thismodel, Dr. Vittoz developed expressions for static anddynamic behavior of sub-threshold logic in [3]. Anoth-er critical early development was the work of Swan-son and Meindl [4], which derived the minimum sup-ply voltage at which CMOS digital circuits can func-tion, and demonstrated inverter VTC down to 0.2V.

Today, sub-threshold operation provides a com-pelling solution for a number of emerging energy-constrained systems implemented in scaled CMOStechnologies. This article outlines some of the recentadvances and challenges associated with sub-thresh-old circuit design. This includes the design of newlogic and memory circuits, support circuitry (e.g., DC-DC converters) and the use of redundancy.

Minimum Energy Digital LogicThe concept of aggressive VDD scaling has beenexplored to minimize energy dissipation. An impor-tant question involves finding the optimal VDD andthreshold voltage (Vt) which minimize the energy

consumed by a digital circuit. To this end, authors in[5] examined energy and performance contours of acharacterization circuit as VDD and Vt are varied. Thecontours showed the existence of an optimum VDDand Vt which minimizes energy. Importantly, theoptimum VDD does not necessarily occur at the low-est voltage at which the circuit functions. For circuitsthat require higher performance than is possible atthe minimum energy point, the contours give the(VDD, Vt) which lead to the lowest energy consump-tion at the required performance. Effects of varyingthe circuit activity factor and temperature were alsoinvestigated.

For a system where Vt is fixed (i.e. no body bias-ing), Figure 1 shows how energy varies with VDD scal-ing, using a 65nm ALU as an example. As VDDdecreases from 1.2V, the energy per clock cycle firstreduces, then reaches a minimum at around 0.3V, andfinally increases again. This trend occurs because of atrade-off between the active switching and leakagecomponents of energy. At high supply voltages, activeswitching energy (EACT = CVDD

2) dominates. There-fore, as VDD decreases, the circuit energy is reducedquadratically, as shown in Figure 1 for VDD > 0.5V.

However, as VDD is lowered to sub-threshold levelsthe propagation delay increases exponentially, sincedevice currents depend exponentially on both VDDand Vt in weak inversion. Now, the leakage energyper clock cycle (ELEAK), which equals the leakagepower integrated over one clock period, also goes upexponentially and eventually dominates the totalenergy. This is seen in Figure 1 for VDD < 0.3V.

ELEAK=∫

OPILEAKVDDdt

These two opposing trends imply that the totalenergy (ETOT = EACT + ELEAK) reaches a minimum

Advances in Ultra-Low-Voltage Design Joyce Kwong, Anantha P. Chandrakasan, Massachusetts Institute of Technology,[email protected]; [email protected]

Figure 1: Energy versus VDD curve of 65nm ALU, showingtrends in active, leakage, and total energy.



TECHNICAL LITERATUREpoint. The VDD which minimizes energy (minimumenergy point, or MEP) depends on the relative con-tributions of active and leakage energy components[5], [6], [7]. If a circuit has high activity factor (i.e. alarge portion of the circuit switches in any givencycle) and relatively large proportion of EACT, thenthe decreasing trend in EACT dominates until VDDbecomes very small. In this case, the MEP occurs ata low supply voltage. Conversely, if a circuit has lowactivity factor or a relatively large ELEAK component,then the MEP occurs at a higher voltage. For mostsystems, the MEP occurs in or near the sub-thresholdregion, since ELEAK begins to increase rapidly whenVDD decreases and approaches Vt.

Process technology scaling provides smaller switch-ing capacitance. However, leakage current in recenttechnology generations have increased substantially,in part due to decreasing threshold voltages to main-tain performance while the nominal supply voltage isscaled down. Figure 2 examines the net effect of thesetrends on the energy of a 32-bit adder simulated withpredictive models [8] and interconnect parasitics. TheW/L of devices in the adder is kept constant as thelengths are scaled to the 65nm, 32nm, and 22nmnodes. At nominal VDD (0.8V-1V), the reduction inactive energy with process scaling is apparent. Impor-tantly, the MEP occurs at a higher voltage at thedeeply scaled nodes, due to the larger relative contri-bution of leakage energy. Nevertheless, for this par-ticular circuit, the MEP still occurs in the sub-thresh-old region.

Challenges in the Ultra-Low-Voltage RegimeReduced ION/IOFFWe have seen that aggressive voltage scaling affordssignificant energy benefits. However, ultra-low-volt-age design must address two key challenges whichimpact circuit functionality. In sub-threshold, drivecurrent of the on devices (ION) is several orders ofmagnitude lower than in strong inversion. Corre-spondingly, the ratio of active to idle leakage currents(ION/IOFF) is much reduced. In digital logic, thisimplies that the idle leakage in the off devices coun-teract the on devices, such that the on devices may

not pull the output of a logic gate fully to VDD orground. This is especially apparent in circuits wheremany parallel leaking devices fight one or severalactive devices in series, for example in the tiny XORgate [9] or in register files [10]. To address this, [10]derived analytical models for the output voltages andinput requirements of such circuits, as well as theirminimum operating voltage.

Process VariationProcess variation can further skew the relativestrengths of devices to adversely affect the functional-ity of logic gates. Global variation affects all deviceson a chip equally and causes device characteristics tovary from one chip to the next. In sub-threshold logic,its main effect is seen at skewed P/N corners withstrong PMOS and weak NMOS, or vice versa [9]. Indeeply scaled technology nodes, local variation,which affects devices on the same chip differently,has become a significant concern. In sub-threshold,the dominant source of local variation is randomdopant fluctuation (RDF) [11], in which placementand number of dopant atoms in the device channelcause random shifts in Vt. Correspondingly, both IONand IOFF in sub-threshold are exponentially affectedby these Vt shifts. In 65nm, for example, a ±4σ Vt shiftfrom RDF can cause the drain current to change bythree orders of magnitude.

The compound effects of reduced ION/IOFF andprocess variation are illustrated by the voltage trans-fer curve (VTC) of a two-input NAND in Figure 3. Atthe strong-PMOS weak-NMOS global corner, the VTCis shifted towards the right. Additionally, local varia-tion causes random perturbations in the VTC, in somecases significantly degrading the output logic levels.This implies that even the static CMOS logic style doesnot provide guaranteed functionality. To designrobust sub-threshold circuits, it is no longer sufficientto consider only the nominal case or the global cor-ners; we should also account for the statistical effectsof local variation.

In addition to affecting functionality, process varia-tion increases uncertainty in circuit delays. At low volt-ages, increased sensitivity to local variation causes thedelay distribution to widen. Figure 4(a) shows the

Figure 2: Trend in minimum energy point of 32b adderwith technology scaling using predictive models [8].

Figure 3: Impact of global and local variation on NANDgate VTC.




delay distribution of a 65nm logic timing path at 0.3V(sub-threshold) and 1.2V (nominal). To compare thedispersion around the mean, both distributions arenormalized to their sample means, highlighting theorder-of-magnitude larger variability at 0.3V. This issimilarly illustrated in Figure 4(b), by the comprehen-

sive simulation of 30000 timing paths in a 0.3V micro-controller under local variation [12]. Each horizontalcross section represents the delay distribution of onetiming path. Note that adjacent paths with similarmeans can exhibit substantially different variances, asreflected by the lengths of the distribution tails.

Conventionally, methodologies to verify setup/holdtime constraints in a logic circuit treat logic gatedelays as deterministic, taking points at the tails of thedelay distribution to represent the maximum and min-imum delays under process variation. However, veryfew gates exhibit delays found at the tails and most ofthe gates lie in the middle of the distribution. Conse-quently, conventional approaches give unrealisticresults when applied to sub-threshold circuits. As withlogic gate design, statistical methodologies such asthose described in [13] are necessary for robust ultra-low-voltage operation.

SRAM DesignSRAMs typically form a dominant portion of the areaand power of a system. Therefore, energy and leak-age power reduction through low-voltage operation ishighly desirable. However, the traditional 6-transistor(6T) SRAM cell relies on ratioed device sizing to setthe relative device strengths required for reading andwriting. Since sizing changes current linearly while Vtvariation has an exponential impact in sub-threshold,variation can easily overwhelm the effect of sizing tocause bit-cell failures.

Data retention in a 6T SRAM bit-cell is determinedby the cross-coupled inverters M1-M4 shown in Fig-ure 5(a). By superimposing VTC of one inverter onthe inverse VTC of the other, we form a butterfly plotwhich can be used to determine if a bit-cell is bi-sta-ble (i.e. if it can hold data). The presence of two bi-stable intersection points in the butterfly plot indicatesthat the bit-cell can support “0” and “1” logic levels,and thus proper data retention. The static noise mar-gin (SNM) indicates the maximum amount of noisethat can be applied to the storage nodes of the bit-cellbefore the state of the cell is destroyed. The SNM ismeasured as the edge length of the smaller of the two

Figure 4: (a) Delay distribution of timing path at 1.2V and0.3V under local variation. Both histograms contain 1ksamples. (b) Delay distributions of 30k microcontrollertiming paths [12] at 0.3V, fast global corner. Each horizon-tal cross-section represents distribution of one path.

Figure 5: (a) Hold SNM and (b) read SNM of 6T SRAM cell. (c) 8T cell with two-transistor read buffer. (Courtesy of N.Verma)



TECHNICAL LITERATUREinscribed square in the butterfly plot [14]. If variationcauses both VTCs to be shifted by more than thisamount, the butterfly plot would no longer have bi-stable intersection points, indicating failure of the bit-cell to hold a required data state.

In the 6T cell, the read operation is performed byprecharging the bit-lines (BLC/BLT in Figure 5(b)) andthen asserting the word line (WL) to turn on theaccess transistors M5 and M6. The storage node whichstores a “0”, for instance NT, causes the bit-line BLTto discharge. However, since the bit-line is initiallyprecharged, M5 tends to pull NT high while M1attempts to pull it low. The fight between M1 and M5raises the voltage at NT. Accordingly, the butterflyplot for a 6T cell during read is squashed on one end,as illustrated in Figure 5(b).

As VDD is decreased, both read and hold SNM cor-respondingly become smaller. Further, process varia-tion can shift the VTCs in the butterfly plot to causebit-cell instability. As is apparent from Figure 5, theread SNM is considerably smaller than hold SNM, andthus limits low-voltage operation.

An alternative 8T bit-cell avoids the read SNM lim-itation with the use of a two-transistor read buffer.Shown in Figure 5(c), this read buffer M7-M8 isolatesthe internal storage node from the read bitline (RDBL)so that it is not disturbed during a read. Since dataretention in the 8T cell now depends on the largerhold SNM, VDD can be lowered further down to sub-threshold. This bit-cell, along with other peripheralcircuitry to assist sub-threshold writing and toimprove bit-line integration, was demonstrated in a65nm, 256kb SRAM functional down to 350mV [15].

Redundancy is another powerful technique formanaging variation in ultra-low-voltage systems. Indesigning SRAM sense amplifiers, we are faced with atrade-off between their statistical offset and area. Theoffsets of sense amplifiers exhibit a distribution due toprocess variation, whose standard deviation relatesinversely to the areas of the input devices. However,instead of upsizing the input devices to reduce offset,consider putting N redundant sense amplifiers withinthe same area as one full-size circuit, and then select-ing the one with the smallest offset. Although eachcopy has smaller devices and thus larger individualprobability of error (defined as |offset| > 25mV inFigure 6), the error probability in the sensing networkis now the chance that all N sense amplifiers fail.Therefore, PERR, total = (PERR, N)N, where PERR, N is theerror probability of one of the N redundant senseamplifiers. As shown in Figure 6, even a small amountof redundancy (N=2) significantly improves the errorprobability [15].

Tracking Circuits and DC-DC ConvertersMinimum Energy Tracking LoopPowering sub-threshold memory and logic circuitsrequires energy delivery circuitry that can efficientlyconvert a battery supply to sub-threshold voltages atmicrowatt load power levels. Moreover, since theminimum energy point (MEP) of a circuit changeswith workload, temperature, and other environmental

conditions, the ability to track the MEP is crucial tomaximize energy savings. Figure 7 shows the archi-tecture of such a tracking loop [16] which automati-cally adjusts its output voltage to the minimum ener-gy point of the load circuit. The energy sensor circuitand the energy minimization algorithm set the refer-ence voltage (Vref) of the DC-DC converter. The DC-DC converter, in turn, will adjust its output (VDD) tomatch Vref, thereby enabling the load circuit to oper-ate at its MEP.

The energy sensor circuitry senses the energy perclock cycle consumed by the load circuit in a digitalmanner. By avoiding high-gain amplifiers and analogblocks, this scheme significantly reduces the overheadpower. As illustrated in Figure 7, the voltage on thestorage capacitor Cload is first stored on C1. Duringenergy sensing, the DC-DC converter is disabled.Therefore, voltage on Cload droops to V2 after N oper-ations of the load circuit, and is subsequently stored

Figure 6: Redundancy significantly reduces overall errorprobability in SRAM sensing network [15].

Figure 7: Architecture of minimum energy tracking loopand energy sensor circuitry [16].




on C2. The energy per operation of the load circuit isgiven by Eop = Cload(V1

2-V22)/2N. Further, if V2 is suf-

ficiently close to V1, (V1 + V2) ≈ 2V1, and hence Eop isapproximately proportional to V1 (V1 – V2). V1 is thereference voltage to the DC-DC converter and isknown digitally. (V1-V2) can also be found digitally bydischarging C1 using a current sink while a fixed fre-quency clock drives a counter. The fixed frequencyclock, together with the constant current sink thatdrains C1, quantizes voltage into time steps. The num-ber of fixed frequency clock cycles required for C1 todroop down to V2 is directly proportional to (V1-V2).From this, the digital representation of Eop is calculat-ed and is then used by a slope descent algorithm toarrive at the MEP.

Since the MEP usually lies in sub-Vt where loadpower demands are very low, the DC-DC converter inthe MEP tracking loop is designed to supply low volt-ages (0.25V-0.7V) at microwatt power levels. The con-verter employs a synchronous rectifier buck convert-er design with external passives. The all-digital con-trol circuitry is optimized for minimal power over-head, enabling the DC-DC converter to achieve >80%efficiency down to 1μW load power levels.

Switched Capacitor DC-DC ConverterMinimizing the number of external components ishighly desirable in embedded applications such asbiomedical implants. For micro-power applications, aswitched capacitor DC-DC converter design is attrac-tive since the power conversion circuitry can be com-pletely integrated on-chip. Figure 8 shows a switchedcapacitor converter [17] which can provide variablesupply voltages and achieve >70% efficiency whilesupplying from 1μW up to 1mW load power. Theconverter uses an all-digital pulse frequency modula-tion (PFM) mode of control to regulate the outputvoltage. In this type of control, the converter staysidle until the load voltage VL falls below the referencevoltage (VREF), at which point a clocked comparatorenables the switch matrix to transfer one charge pack-et to the load. The PFM mode of control is essentialto achieving high efficiency while providing extreme-ly low power levels to the load circuits.

The switch matrix partially shown in the inset ofFigure 8 contains the charge transfer switches and thecharge transfer capacitors. Importantly, the totalcharge transfer capacitance can be arranged in fivedifferent gain settings to help minimize linear con-duction loss, which is a major efficiency-limitingmechanism in switched capacitor converters [17].Generally the maximum efficiency is limited by theratio of the voltage supplied to the load circuit (VL) tothe output voltage of the converter with no load (Vno-

load). Accordingly, the converter contains multiplegain settings to provide different levels of Vno-load.When we wish to supply very low VL (e.g. 0.3V to asub-Vt SRAM), we can choose the suitable gain settingwith a small Vno-load to maximize the achievable effi-ciency. The two gain settings shown in Figure 8, forinstance, are suitable for supplying VL < VBAT/2 and VL< VBAT/3.

Demonstration SystemsEmerging micro-power applications have generatedmuch interest in sub-threshold circuits. In the pastfew years, researchers have demonstrated a variety ofsystems functioning at very low voltages. For exam-ple, a sub-threshold DLMS filter was designed for ahearing-aid application, and an 8x8 carry save arraymultiplier test-chip was fabricated in 0.35μm [18].This test-chip published in 2003 explored adaptivebody biasing and operated down to 0.3V. In 2004, an180mV FFT processor in 0.18μm was demonstrated in[9]. The processor, pictured in Figure 9, featured anenergy-aware scalable architecture supporting vari-able bit precision and FFT length. Device sizingstrategies for logic gates accounted for global processvariation, and the register file design employed amultiplexer-based hierarchical-read-bitline scheme toaddress weak ION/IOFF. Combining the energy bene-fits of sub-Vt operation with Dynamic Voltage Scaling(DVS), [19] presented an Ultra-Dynamic Voltage Scal-ing test-chip with a 32b Kogge-Stone adder in 90nm.In this technique, we can operate the circuit at itsMEP during periods of very little activity, and dynam-ically raise VDD when short bursts of high perform-ance are needed. The test-chip showed 6800X per-formance scaling as VDD is varied from the MEP of330mV to 1.1V, and provided 9X energy savings oversingle-VDD operation.

Systems with constant throughput constraints canalso benefit from substantial VDD reduction by lever-aging extreme parallelism to compensate for speeddecrease. For example, a 400mV baseband radioprocessor [20] was able to support 500M samples/sthroughput by distributing computations to many par-allel hardware blocks.

A 200mV, 0.13μm sub-threshold sensor processorwas demonstrated in [21] and features an 8b ALU, 32baccumulator, and 2kb SRAM. The standard cell libraryto implement the processor was carefully selected toexclude cells with a fan-in more than 2 as well aspass-transistor logic. Another sub-200mV processor in0.13μm examined the effectiveness of body biasing inFigure 8: Switched capacitor DC-DC converter architecture

[17], [12].




mitigating variation and several logic gate sizingstrategies for performance tuning [22].

Looking forward, technology scaling enablesreduced CVDD

2 energy and increased density, butpresents heightened process variation. Most recentlyin 2008, a 320mV 411GOPS/Watt motion estimationaccelerator in 65nm [23] employed optimized data-path circuits to address variation and weak ION/IOFF,as well as to improve performance. [12] presented a65nm system-on-a-chip which features a 16b micro-controller, a 128kb 8T SRAM, and an on-chip switchedcapacitor DC-DC converter (Figure 10). The systemdemonstrated approaches for library design and tim-ing analysis, as well as circuit techniques to enablesub-threshold operation down to 300mV.

In the mixed-signal domain, an ADC functioningdown to 200mV has been demonstrated in [24]. Thishighly digital 6b flash ADC removes the need for aresistor string reference voltage ladder by buildingvoltage offsets directly into each dynamic, regenera-tive comparator through sizing. As comparator andreference voltage offset compensation is difficult in

the analog domain at voltages below 500mV, com-parator redundancy and reconfigurability areemployed to tolerate large comparator offsets (> 1LSB) and improve linearity.

Current mode logic in weak inversion was present-ed in [25]. To operate at low bias currents, a novelPMOS load device was proposed to provide highresistance and large voltage swing.

Published work on sub-threshold SRAMs hasexplored a range of bit-cell and peripheral circuitdesigns. The survey here is organized according toprocess technology. At the 0.13μm node, authors of[26] demonstrated a 512x13b SRAM with a register-file-based cell, a multiplexed read scheme, and self-timed keepers to achieve functionality at 216mV.The 0.2V, 480kb SRAM [27] used a 10T bit-celldesigned to eliminate data-dependent bit-line leak-age. Access devices are lengthened to take advan-tage of reverse short channel effects and improvesub-Vt writability. A virtual ground replica shifts thetrip point of the inverter-based sensing circuit toimprove sensing margin. [28] explored use of a 6Tcell modified for single-ended read and improvedreadability. This came at the cost of reducedwritability, which was recovered by allowing thebit-cells’ virtual VDD and ground rails to droop dur-ing a write. The 2kb SRAM array was fully function-al from 1.2V to 193mV.

At the 65nm node, local variation becomes moreprominent. A 256kb SRAM [29] employed a 10T bit-cell to eliminate the read SNM limitation as mentionedin the SRAM section. Stacked devices in the read-buffer reduced bit-line leakage and improved bit-lineintegration, while floating the cell supply voltageassisted sub-Vt writes. The SRAM was able to fullyread and write at below 0.4V. The 8T designdescribed previously [15] featured peripheral assistcircuitry to enable functionality in sub-Vt. During awrite, the cell supply voltage is reduced by a writedriver, to ensure that PMOS devices are weakened rel-ative to access devices. During a read, the feet of allunaccessed read buffers are pulled to VDD, eliminat-ing their sub-Vt leakage currents which would other-wise degrade the read bitline voltage.

Next StepsSignificant advances have been made in the recentyear related to sub-threshold circuit design. Importantissues such as device variability have been addressedthrough circuit design and system architecture. Totransition these concepts to products, it will be criticalto develop design methodologies and CAD tools toencapsulate variation-aware methodology (e.g., statis-tical timing tools compatible with low-voltage design).A number of exciting new applications can leverageultra-low-voltage operation to dramatically reduceenergy consumption. This includes sensor networks,medical electronics and multimedia devices.

AcknowledgementsThe authors thank DARPA for funding, and TexasInstruments and National Semiconductor for chip fab-

Figure 9: Die micrograph of 180mV FFT Processor [9].

Figure 10: Die micrograph of 65nm sub-Vt microcontroller[12].




rication. J. Kwong is supported by the Texas Instru-ments Graduate Woman’s Fellowship. The authors aregrateful to Dimitri Antoniadis, Yu Cao, Eric Wang, andWei Zhao for help with the predictive models used inthis article.

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[24] D. C. Daly, A. P. Chandrakasan, “A 6b 0.2-to-0.9Vhighly digital flash ADC with comparator redun-dancy,” IEEE International Solid-State CircuitsConference, pp.554-555, Feb. 2008.

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[28] B. Zhai, D. Blaauw, D. Sylvester, S. Hanson, “Asub-200mV 6T SRAM in 0.13μm CMOS,” IEEEInternational Solid-State Circuits Conference,pp. 332-333, Feb. 2007.

[29] B. H. Calhoun, A. Chandrakasan, “A 256kb sub-threshold SRAM in 65nm CMOS,” IEEE Interna-tional Solid-State Circuits Conference, pp. 2592-2593, Feb. 2006.

About the AuthorsJoyce Kwong received a Bachelor ofApplied Science at the University ofWaterloo in 2004 and a master’s degreein Electrical Engineering at the Massa-chusetts Institute of Technology in 2006.She is currently working towards a Ph.D.at MIT. She is the recipient of the TexasInstruments Graduate Woman’s Fellow-

ship for Leadership in Microelectronics and theNSERC Postgraduate Fellowship. Her research inter-ests include sub-threshold design methodology andsystem implementation.

Anantha P. Chandrakasan receivedthe B.S, M.S. and Ph.D. degrees in Elec-trical Engineering and Computer Sci-ences from the University of California,Berkeley, in 1989, 1990, and 1994respectively. Since September 1994, hehas been with the Massachusetts Insti-tute of Technology, Cambridge, where

he is currently the Joseph F. and Nancy P. KeithleyProfessor of Electrical Engineering.

He was a co-recipient of several awards includingthe 1993 IEEE Communications Society's Best Tutori-al Paper Award, the IEEE Electron Devices Society's1997 Paul Rappaport Award for the Best Paper in anEDS publication during 1997, the 1999 DAC DesignContest Award, the 2004 DAC/ISSCC Student DesignContest Award, the 2007 ISSCC Beatrice WinnerAward for Editorial Excellence and the 2007 ISSCCJack Kilby Award for Outstanding Student Paper.

His research interests include low-power digital inte-grated circuit design, wireless microsensors, ultra-wide-band radios, and emerging technologies. He is a co-author of Low Power Digital CMOS Design (Kluwer Aca-demic Publishers, 1995), Digital Integrated Circuits(Pearson Prentice-Hall, 2003, 2nd edition), and Sub-threshold Design for Ultra-Low Power Systems (Springer2006). He is also a co-editor of Low Power CMOSDesign (IEEE Press, 1998), Design of High-PerformanceMicroprocessor Circuits (IEEE Press, 2000), and Leakagein Nanometer CMOS Technologies (Springer, 2005).

He has served as a technical program co-chair forthe 1997 International Symposium on Low PowerElectronics and Design (ISLPED), VLSI Design '98,and the 1998 IEEE Workshop on Signal ProcessingSystems. He was the Signal Processing Sub-committeeChair for ISSCC 1999-2001, the Program Vice-Chair forISSCC 2002, the Program Chair for ISSCC 2003, andthe Technology Directions Sub-committee Chair forISSCC 2004-2008. He was an Associate Editor for theIEEE Journal of Solid-State Circuits from 1998 to 2001.He served on SSCS AdCom from 2000 to 2007 and hewas the meetings committee chair from 2004 to 2007.He is the Technology Directions Chair for ISSCC 2009.He is the Director of the MIT Microsystems Technol-ogy Laboratories.




Silicon Takes the Stage in Particle Physics ExperimentsThe gigantic experiments at CERN, the elementaryparticle accelerator laboratory in Geneva, Switzerlandrely on custom-designed CMOS for much of theirfunctioning. Close to a million CMOS chips, silicon-based sensors and other sensitive material, such asscintillating crystals or liquid argon, fill the space inand around a superconducting magnet, the size of a6-stories building. The chips have to process smallelectrical signals, typically 10 to 20 thousand elec-trons, generated by the ionizing particles in the sen-sor elements. Silicon is sensitive to light, but verythick diode structures also deliver signals that areproportional to the energy loss of swift particles thatpass through. The sensor cells have been connectedin a fully parallel approach to their integrated read-out amplifiers and further signal processing, becausethe 'snapshots' of the successive interactions areuncorrelated, and take place every 25 ns: 40 millionpictures per second. These massively parallel detec-tor systems with close to 109 sensor cells havebecome possible only by exploiting the miniaturiza-tion of electronics.

The CERN experiments are situated deep under-ground along the 27 km circular accelerator called the‘Large Hadron Collider’ LHC. Figure 1 gives an idea ofsuch a collider detector, still under construction.

The experiments study the fundamental physicsprocesses between elementary particles at the highestmomenta on earth. Particle beams circulating inopposite directions with thousands of bunches of pro-tons are accelerated to 7 TeV, and then made to col-lide head-on in 4 crossing points. The experimentalset-up around an interaction point consists of succes-sive shells of different detectors in which one recordsall the effects in the miniature explosions that resultwhen quarks inside these protons occasionally fusetogether. Figure 2 illustrates the variety of reactionproducts in a rare, sought-after type of collision.

Only a tiny ‘needle’ fraction of the ‘events’ repre-sent new physics phenomena, and these have to befiltered out from the majority 'haystack' of uninterest-ing data. A particle or quantum with 1 TeV energy hasan equivalent wavelength of one attometer (10-18m),compared to a micrometer for visible light, and soone can say that these experiments in the TeV energyrange act as 'attoscopes' rather than microscopes,when they look at the properties of these energeticquanta on the atto-scale.

The introduction of silicon chips in particle physicsexperiments went by steps, and in this article I tracesome of the history of silicon detectors and readoutchips for tracking detectors. These form the innershells of the equipment. As shown in Figure 2, theyrecord the trajectories of the ionizing particles in a

Gigasensors for an Attoscope: Catching Quanta in CMOSErik H.M. Heijne, CERN, [email protected]

Fig. 1 Part of the Atlas team assembled in between the end-caps, in the underground cave. Several thousand scientists andtechnicians have worked on the Atlas construction. The bluecylinder is a shielding block that surrounds the entry/exit ofthe not yet installed beam pipe. The magnet and the main bar-rel are to the left, invisible here. Photo CERN/Atlas.

Fig. 2 Simulated interaction in the Atlas detector with alloutgoing reaction products traversing the successiveshells of the detector. The central region where most par-ticles are colored red, represents the inner tracker detec-tors. The surrounding heavy calorimeters provoke show-ering around the absorbed particles. The yellow track tothe right is an escaping muon. The scale of the figure is~10m across. Photo CERN/Atlas.




somewhat similar way as cloud chambers, sparkchambers or bubble chambers did in the earlier times.Although providing fewer measurement points alonga track, the main advantage of the silicon tracker sys-tems is the fully electronic operation and the ns col-lection time of the signals in the silicon layers.Already in 1976 at the EPFL, the Swiss Federal Tech-nical University in Lausanne, during a workshop 'Lim-its on Miniaturization' my colleague Pierre Jarron andI became enthusiastic to apply developments inmicroelectronics for detection of particles. As shownin the next section, segmentation is the key to the sil-icon trackers, and in 1980 we introduced the silicondiode 'microstrip' detector with full parallel readout,following a visit at the nuclear physics institute IKO inAmsterdam. Then the design of custom chips for sil-icon detector readout was started at SLAC in 1981 andat CERN in 1986. Now, 25 years later a community ofdesigners and users supply the various integrated cir-cuits for detection and signal processing in the exper-iments at CERN, at Fermilab near Chicago, at the Stan-ford linear accelerator SLAC, and other facilities world-wide. The most recent development with ‘ultimate’segmentation for particle tracking, ~ 1995, was the true2D silicon pixel detector, for which Eric Vittoz and hiscoworkers in CSEM and at the EPFL contributed sig-nificantly, with advice, designs and training.

Segmentation of Sensors, Serial or Parallel ReadoutThe use of a contiguous array of segmented diodeson monolithic silicon for nuclear particle detection, asfar as I know, was first proposed ~1961 by Leo Koertsfrom Philips/IKO in Amsterdam. Their ‘checker board’detector with Schottky barrier strips on the front andorthogonal ohmic strips on the rear, both with 1.2 mmpitch, was described by Hofker in 1966 [1]. This wasthe device that Jarron and I took as the example forour silicon diode ‘microstrip’ detectors, with muchsmaller segmentation at 200 µm [2] and later at 50 µmpitch. The readout of the checker board was not yetfully parallel, but it had single analog amplifier chan-nels, for front and rear of the sensor, together with aseries of pick-up transformers for position determina-tion along the diode array. The full system ‘BOL’ with8000 'pixels' [3], operational 1968-1974, needed sever-al cubic meters of electronics for this readout. It isinteresting to remember that around this time mono-lithic 2D matrix approaches for imaging of visiblelight also were studied at Philips and at Bell Labs.Within a few years these proposed respectively BBD[4] and CCD [5] for imaging, and both approachesused serial signal readout.

The earliest system with fully parallel readout for asizeable array of sensing elements was the Multi-WireProportional Chamber (MWPC) for particle positionmeasurement in 1968 [6] which earned GeorgesCharpak a Nobel prize in 1992. A separate amplifierconnects to each wire and with a typical distancebetween wires of ~5mm, this electronics could be fab-ricated with the discrete components of the time. Forthe 'microstrip' detectors, made on kΩcm Si wafers bySchottky barriers and later by ion-implantation [7] at

first also discrete components were used for readout,but the need for integrated circuits now was obvious.Several teams initiated analog design work: Hyams,Parker and Walker started at Stanford with an NMOSchip, called Microplex [8]. Their design used aswitched capacitor feedback amplifier and evolvedlater, thanks to Kleinfelder [9], Spieler [10] andcoworkers at Lawrence Berkeley Lab into a family ofCMOS chips, used still now at Fermilab in the CDFand D0 Tevatron collider experiments. In Germany,a team of the Munich Heisenberg Laboratory and theDuisburg Microelectronics Institute, with Lutz andButtler, together with Manfredi et al. at the Universityof Pavia, developed a 128 channel CMOS circuit withJFET frontend transistors [11]. Later this chip wascalled CAMEX and was used in the electron colliderexperiment Aleph at CERN, from 1989 to 2001. Allthese circuits used a front-end amplifier with switch-ing feedback and double correlated sampling, con-trary to the continuous feedback in 'Amplex' that Iwill discuss in the next section.

But first more on the ‘ultimate’ segmentation: forthe planned proton collider experiments in the USAand Europe, with their large number of simultaneousparticles, from the early 1980's we at CERN wanted topush towards parallel sensor cells of micrometerdimensions in a true 2D matrix, using photolithogra-phy [12]. Damerell had shown the power of 2D meas-urements by using CCD [13] but the serial readoutrestricts this method to particular situations of lowrepetition rate or experiments where the beam can bestopped after an interesting interaction, such as in alinear accelerator. The question was, if we couldimplement conventional, ns signal processing and fullparallel readout on a microscopic area with reason-able power dissipation. We approached Eric Vittozwith this question in 1986. For the first Workshop onPixel Detectors in Leuven [14] Vittoz analyzed thisproblem, and he summarized some parameters inTable 1. Also he sketched the signal processing chainin Figure 3, and came with positive conclusions on




power and noise. Such small pixels pinpoint positionsof the particles in space with much better precision,but also have the pleasant characteristics of lowcapacitance and reduced dark current.

This allows low electronic noise, and recent matri-ces achieve ~ 100 e- r.m.s.equivalent, at the input ofthe signal processing circuit, even with ~100ns signalshaping. The signal generated in the Si sensor by ion-izing quanta is typically between 2000 and 20000 elec-tron-hole pairs, so that one has a comfortable sig-nal/noise ratio. In 1987 I dubbed these devices‘micropattern’ detectors, because I imagined thateventually they would be able to recognize usefulinteractions from pre-defined patterns in the image.In practice the name ‘pixel’ detectors has nowbecome the standard. In the English language, con-trary to the French, there is an ambiguity between‘detector of patterns’ and ‘detector with patterns,’ andthe latter meaning has more recently been adopted inthe field of gaseous devices.

The Earliest ‘Micropattern’ Pixel DetectorsIn 1988, after the Workshop in Leuven, the designwork started on a first prototype of a 9x12 pixeldetector matrix, by Smart Silicon Systems, a startupfrom the EPFL, with Christian Enz and François Krum-menacher as designers, Eric Vittoz as adviser and theCERN team as the critical customers and users. Witha future particle collider in mind some design choices

were made, such as a latched input circuit, in order toobtain low power dissipation. By Christmas the lay-out was ready, the chip was processed in the 3 µmSACMOS technology at Faselec AG in Zurich. Withself-aligned contacts (SAC) this technology offeredincreased density, allowing a small pixel area of 200µm x 200 µm. In June 1989, after dicing at CSEM wemade the microphoto of Figure 4, which shows onecorner of the matrix with 8 input contacts and read-out cells.

Michael Campbell and I made the first measure-ments over the summer, and our late paper wasaccepted for presentation at the 1989 Nuclear ScienceSymposium near San Francisco. The chip worked well,with noise below 500 e- rms, detection threshold~3000 e- and power of 30 µW/pixel, all well below thedesign goals. But then some strange problems besetthe first publication. The Symposium was cancelledbecause of the 17 October San Francisco earthquake.Despairing, we submitted the paper to Nuclear Instru-ments and Methods [15]. The Conference eventuallywas rescheduled in a different, undamaged hotelwhere Michael Campbell presented the paper only inJanuary 1990 for a small audience. We also found thatthe planned bump-bonding could not be madebecause of a mm wide guard ring that is neededaround the active sensor area, and this would obscurethe wirebond pads on the electronics readout chip.

We initiated the design for a next chip, now aimingat an asynchronous input amplifier and a large, morepractical matrix of 16 columns and 63 rows. The 64throw was dedicated to a provision for dark currentcompensation. Each pixel of 75µmx500µm contained~80 transistors. The chip was again manufactured inthe SACMOS3 technology, and after bump-bondassembly at GEC-Marconi in Caswell, the first particletracks were measured at CERN on 20 October 1991.These measurements were presented at the 1991Nuclear Science Symposium in Santa Fe [16], twoyears after those of the first chip. In the scientificcommunity, with relatively modest resources longiteration times are typical, also because the designteams are involved in the development and testing ofthe full application system. Indeed, the following,third chip in this series was the LHC1/Omega3 [17],which became available early in 1995, nearly fouryears later. This chip with a 16x128 matrix of cellsused the SACMOS 1µm technology, which represent-ed at the time a submicron component density incomparison with normal CMOS. The smaller pixelarea of 50µmx500µm could now contain as many as400 transistors. I wonder if we can call this a 'hyper-active' pixel, after Eric Fossum just before [18] hadclaimed the term 'active pixel sensor' if each pixelcontains at least one transistor. It may also be worthmentioning that the Faselec/Philips SAC1 process,although developed in Zurich, in 1994 just was trans-ferred to the Taiwan Semiconductor ManufacturingCompany TSMC, with the Swiss technology specialistJ. Solo making many trips between Zurich and Taipei.That technology was never actually implemented any-more at the Zurich foundry of Faselec, illustrating the

Fig. 4 Corner of the first pixel readout chip, showing 8pixels with input contacts for bump bonding and someoutput pads for wirebonds. Design and layout by FrançoisKrummenacher and Christian Enz, Dec 1988. Made in SAC-MOS3 technology. Photo CERN.

Fig. 3 Schematic by Eric Vittoz for the analog front end foran integrated pixel detector[14].



TECHNICAL LITERATUREswift worldwide concentrations in microelectronicsmanufacturing. Only 10 years earlier, there still wereseveral MOS factories in Switzerland, serving the localhigh-tech industries, described in the SummerNewsletter dedicated to Eric Vittoz.

Active Feedback Compensates Dark CurrentIn semiconductor diode detectors, systematically onehas to cope with the dark leakage current at reversebias and often the input is AC coupled, in order to

avoid baseline shift and amplifier saturation. For high-ly segmented devices, external filtering networksbecome impractical and these have to be implement-ed on the silicon sensor itself. DC interconnectionswould be preferable, but then a scheme is needed toaccommodate varying and sometimes large currentsat the inputs of the front-end amplifiers. Sometimeshundreds of nA have to be compensated, even moreafter extended irradiation, although the current isstrongly reduced by the sensor segmentation. For thegaseous detectors this is not an issue, because the gasremains a perfect isolator, even at kV bias.

At CERN, Pierre Jarron and I started in 1986 workon CMOS chip design for the segmented Si detectorswith a training course in the INVOMEC division at thejust founded IMEC centre in Leuven, Belgium. Jarronfollowed the nuclear electronics tradition, and imple-mented a continuous feedback scheme using a longtransistor, as shown in Figure 5 [19].

With direct connection, the sensor dark current atthe input modulates the effective resistance of thefeedback, so that the operational level at the outputcan be maintained, at the cost of a slight reduction ofamplification. A current up to 450 nA per segment canbe compensated. The 16-channel AMPLEX chip [20]was produced in 1987 in the 3um CMOS technologyof MIETEC in Belgium. By chance this AMPLEX chiphappened in 1989 to become the first integrated cir-cuit to be actually operational in a beam colliderexperiment: the inner silicon array in the UA2 proton-antiproton experiment at CERN [21] was used a yearbefore the vertex detector at the MARKII in SLAC wastaking data in July 1990 [22] although the Microplex

chip for SLAC had been designed some years earlier.The UA2 silicon detectors had a surface area of morethan 1 m2, and this was at the time the largest silicondetector ever.

For the silicon pixel detector with their thousandsof sensor cells and amplifiers, the DC coupling is theonly practical possibility and a current compensationhas to be implemented, on the small area available.In the Omega2 matrix Michael Campbell replicatedthe currents from a row of reference pixels. FrançoisKrummenacher proposed in 1990 a damped feedbackillustrated in Figure 6 [23].

This can be implemented in each pixel, without theneed for reference cells. The transistor M2 can sinkthe leakage current Ileak, and with proper choice of Cand gm2 the tolerated Ileak can be much larger than thebiasing current Ip With thousands of pixels, in practi-cal implementations a dark current as high as 1mAper cm2 can be handled with this approach, and cur-rent fluctuations are slowly but automatically fol-lowed pixel by pixel.

Massively Parallel 2D Gigasensor ArrayThe heart of three of the CERN LHC experiments isformed by several layers of true 2D pixel matrixdetectors, which record at 40 MHz the positions andtiming of all particles that pass through. Every singleparticle, representing a quantum of energy above thedetection threshold of ~ 5 keV is registered by thesedevices. The CMOS chips that are attached to thesensor matrix not only record the signals, but storethese in local memory for up to ~4 µs, until a requestfor readout is received. Optical links could transmita large fraction of the data but the off-detector dataprocessing is designed for analysis of ~kHz eventrates, corresponding to expected numbers of interest-ing interactions. The actual sensitive area of the innersilicon pixel arrays ranges from 0.22 m2 and 1200chips in ALICE, to 1 m2 with 16000 chips in CMS and1.8 m2 with 28000 chips in ATLAS. A much larger

Fig. 5 Schematic diagram of the connection of segmenteddiode elements to an Operational TransconductanceAmplifier (OTA) with a feedback that restores the operat-ing point if there is a large current Idark at the input [19].

Fig. 6 Schematic diagram of the front end by Krummen-acher with sinking of dark current via M2. This schemecan be implemented in each pixel [23].




area, up to 400 m2, is covered in the next shells with1D silicon microstrip detectors. Also these detectorsemploy tens of thousands of CMOS chips for the sig-nal readout and data processing. At the start of theLHC the overall number of pixels per experiment isnot quite 109 yet. It is expected that a higher beamintensity in a couple of years will bring a need forupgrades with more pixel layers, to replace the cur-rently installed layers of 1D silicon microstrip detec-tors. If the particle density in each beam crossing isincreased, the projective 1D detectors can not copewith the ambiguities between several coincident par-ticles anymore, and true 2D detectors are necessary.

It is not possible here to describe in detail allaspects of these complex systems, such as the datareadout systems, the power distribution (~ 50 kW forthe inner silicon detectors) and the cooling. Figure 7gives an impression of the pixel detector for ATLAS,showing half of the barrel under final construction.

This device will sit tightly around the beam pipe,detect millions of particles per second and undergo alarge amount of radiation over the planned lifetime of~10 years. The survival of the CMOS as well as thesilicon sensors has been studied and the use of stan-dard technologies has been found acceptable. Theunavoidable increase of sensor dark current and thechanges of material properties can be mitigated byoperating the detector well below 0 degree C. Withthe installation completed, the number of dead sensorelements is still below 1%, and the 'giga' detectors arepractically ready to take beam.

Some Future DevelopmentsThe increased density in CMOS allows to integrateever more functionality in each pixel while keepingdimensions of some tens of µm. This can improveprecision in space and time for particle experiments.Eventually, trigger selectivity may profit if signaturesfor useful interactions could be determined. In otherfields of science various new applications of particledetectors begin to appear. For example, pixel arraysare now used for X-ray imaging with individual pro-cessing of each incoming photonic quantum. This

allows selection of energy bands and representationof the image in different “colours.'’ Thresholding elim-inates various types of background and long expo-sures can be made, such as needed with low intensi-ty, nanofocus X-ray sources. Our group at CERN, withMichael Campbell as team leader, has designed thefamily of 'Medipix' imagers [24], building on theexpertise in ionizing particle detectors. Figure 8shows the layout of a pixel in the Medipix3 readoutchip [25], the first particle detector where each pixelcommunicates in real time with all of its neighbours,to compare and add up coincident signals that belongto the same incident radiation quantum.

The Medipix chips are 3-side buttable, and the con-struction of a large area array will be needed to allowfor use in medical applications. For a CT scanner adetector array of ~m2 may be required. With ~ 50 000pixels per cm2 then such a device also will presentclose to 109 sensor cells, another gigasensor.

In conclusion, CMOS chips in conjunction with sil-icon diode matrices are now used on a large scale forionizing particle imaging. They are catching quantain physics experiments as well as in X-ray imaging.Eric Vittoz has been instrumental in guiding the earlydevelopments leading to these gigasensors. Not onlycomputing and consumer electronics but also variousbranches of science can profit from the progress inmicroelectronics.

References[1] W.K. Hofker, D.P. Oosthoek, A.M.E. Hoe-

berechts, R. van Dantzig, K. Mulder, J.E.J. Ober-ski, L.A.Ch. Koerts, J.H. Dieperink, E. Kok andR.F. Rumphorst, The checker board counter: asemiconductor dE/dx detector with positionindication, IEEE Trans. Nucl. Sci. NS-13 (June1966) 208

[2] E.H.M. Heijne, L. Hubbeling, B.D. Hyams, P. Jar-ron, P. Lazeyras, F. Piuz, J.C. Vermeulen and A.

Fig. 7 Final assembly work on the Atlas pixel barrel (half).One can see the modules along the ladders. The whitestubs are connecting tubes for the cooling channels, onefor each ladder. Photo CERN/Atlas.

Fig. 8 Layout for the Medipix3 chip of a 55µm pixel cell in a130 nm CMOS technology. Preamplifier, shaper and com-parators, resp. 1, 2 and 3 form the analog part, while 3-7 arethe control logic, counters, configuration and arbitration cir-cuits. This pixel has more than 1080 transistors [25].



TECHNICAL LITERATUREWylie, A silicon surface barrier microstrip detec-tor designed for high energy physics, Nucl. Instr.Meth. 178 (1980) 331

[3] L.A.Ch. Koerts, K. Mulder, J.E.J. Oberski and R.van Dantzig, The 'BOL' nuclear research project,Nucl. Instr. Meth. 92 (1971) 157 and followingarticles in the issue

[4] F.L.J. Sangster and K. Teer, Bucket - brigade elec-tronics - New possibilities for delay, time-axisconversion, and scanning, IEEE J. Solid-State Cir-cuits SC-4 (1969) 131

[5] W.S. Boyle and G.E. Smith, Charge coupledsemiconductor devices, Bell Syst. Techn. J. 49(1970) 587

[6] G. Charpak, R. Bouclier, T. Bressani, J. Favierand C. Zupancic, The use of multiwire propor-tional counters to select and localize chargedparticles, Nucl. Instr. Meth. 62 (1968) 262

[7] J. Kemmer, P. Burger, R. Henck and E. Heijne,Performance and applications of passivated ion-implanted silicon detectors, IEEE Trans. Nucl.Sci. NS-29 (1982) 733

[8] J.T. Walker, S. Parker, B.D. Hyams and S.L.Shapiro, Development of high density readoutfor silicon strip detectors, Nucl. Instr. Meth. 226(1984) 200 (3rd Munich Symposium1983)

[9] Stuart A. Kleinfelder, William C. Carithers Jr.,Robert P. Ely Jr., Carl Haber, Frederick Kirstenand Helmuth G. Spieler, A flexible 128 channelsilicon strip detector instrumentation integratedcircuit with sparse data readout, IEEE Trans.Nucl. Sci. NS-35 (1988) 171

[10] H. Spieler, Analog front-end electronics for theSDC silicon tracker, Nucl. Instr. Meth. A342(1994) 205 Hiroshima STD Symposium

[11] G. Lutz, F. Maloberti, P.F. Manfredi, V. Re, V.Speziali, W. Buttler and H. Vogt, on the design ofa JFET-CMOS front-end for low noise data acqui-sition from microstrip detectors, Nucl. Instr.Meth. A264 (1988) 391

[12] Erik H.M. Heijne and Pierre Jarron, Developmentof silicon pixel detectors: an introduction, Nucl.Instr. Meth. A275 (1989) 467 (1st Leuven Work-shop)

[13] C.J.S. Damerell, R.L. English, A.R. Gillman, A.L.Lintern, F.J. Wickens, G. Agnew and S.J. Watts,CCDs for vertex detection in high energyphysics, Nucl. Instr. Meth. A253 (1987) 478 (4thMunich Symp)

[14] Eric A. Vittoz, Tradeoffs in low-power CMOSanalog circuits for pixel detectors, Nucl. Instr.Meth. A275 (1989) 472 (1st Leuven Workshop)

[15] M. Campbell, E.H.M. Heijne, P. Jarron, F. Krum-menacher, C.C. Enz, M. Declerq, E. Vittoz and G.Viertel, A 10 MHz micropower CMOS front-endfor direct readout of pixel detectors, Nucl. Instr.Meth. A290 (1990) 149 (CERN/EF 89-21, 7Nov.1989)

[16] F. Anghinolfi, P. Aspell, K. Bass, W. Beusch, L.Bosisio, C. Boutonnet, P. Burger, M. Campbell, E.Chesi, C. Claeys, J.C. Clemens, M. Cohen Solal, I.Debusschere, P. Delpierre, D. Di Bari, B. Dier-

ickx, C.C. Enz, E. Focardi, F. Forti, Y. Gally, M.Glaser, T. Gys, M.C. Habrard, E.H.M. Heijne, L.Hermans, R. Hurst, P. Inzani, J.J. Jæger, P. Jarron,F. Krummenacher, F. Lemeilleur, V. Lenti, V. Man-zari, G. Meddeler, M. Morando, A. Munns, F.Nava, F. Navach, C. Neyer, G. Ottaviani, F. Pelle-grini, F. Pengg, R. Perego, M. Pindo, R. Potheau,E. Quercigh, N. Redaelli, L. Rossi, D. Sauvage, G.Segato, S. Simone, G. Stefanini, G. Tonelli, G.Vanstraelen, G. Vegni, H. Verweij, G.M. Vierteland J. Waisbard , A 1006 element hybrid siliconpixel detector with strobed binary output, IEEETrans. Nucl. Sci. NS-39 (1992) 654 also:CERN/ECP 91-26

[17] E.H.M. Heijne, F. Antinori, D. Barberis, K.H.Becks, H. Beker, W. Beusch, P. Burger, M.Campbell, E. Cantatore, M.G. Catanesi, E. Chesi,G. Darbo, S. D'Auria, C. DaVia', D. Di Bari, S. DiLiberto, T. Gys, G. Humpston, A. Jacholkowski,J.J. Jaeger, J. Jakubek, P. Jarron, W. Klempt, F.Krummenacher, K. Knudson, J. Kubasta, J.C. Las-salle, R. Leitner, F. Lemeilleur, V. Lenti, M.Letheren, B. Lisowski, L. Lopez, D. Loukas, M.Luptak, P. Martinengo, G. Meddeler, F. Meddi, P.Middelkamp, M. Morando, P. Morettini, A.Munns, P. Musico, F. Pellegrini, F. Pengg, S.Pospisil, E. Quercigh, J. Ridky, L. Rossi, K.Safarik, L. Scharfetter, G. Segato, S. Simone, K.Smith, W. Snoeys, C. Sobczynski, J. Stastny andV. Vrba, LHC1: a semiconductor pixel detectorreadout chip with internal, tunable delay provid-ing a binary pattern of selected events, Nucl.Instr. Meth. A383 (1996) 55 Hiroshima SympCERN ECP/96-3

[18] Sunetra K. Mendis', Sabrina E. Kemeny and EricR. Fossum, A 128 x 128 CMOS Active Pixel ImageSensor for Highly Integrated Imaging Systems,Digest of technical papers 1993 IEEE Interna-tional Electron Devices Meeting IEDM paper22.6, p.583

[19] Erik H.M. Heijne and Pierre Jarron, A low noiseCMOS integrated signal processor for multi-ele-ment particle detectors, Proc. ESSCIRC'88 Conf.,p.66 UMIST, Manchester, UK

[20] E. Beuville, K. Borer, E. Chesi, E.H.M. Heijne, P.Jarron, B. Lisowski and S. Singh, AMPLEX, a low-noise, low-power analog CMOS signal processorfor multi-element silicon particle detectors, Nucl.Instr. Meth. A288 (1990) 157 (5th Munich Sym-posium 1989)

[21] R. Ansari, E. Beuville, K. Borer, P. Cenci, A.G.Clark, A. Federspiel, O. Gildemeister, C.Gössling, K. Hara, E.H.M. Heijne, P. Jarron, P.Lariccia, B. Lisowski, D.J. Munday, T. Pal, M.A.Parker, N. Redaelli, P. Scampoli, V. Simak, S.L.Singh, T. Vallon-Hulth and P.S. Wells, The silicondetectors in the UA2 experiment, Nucl. Instr.Meth. A279 (1989) 388 (Como 1988)

[22] C. Adolphsen, R.G. Jacobsen, V. Lüth, G. Gratta,L. Labarga, A.M. Litke, A.S. Schwarz, M. Turala,C. Zaccardelli, A. Breakstone, C.J. Kenney, S.I.Parker, B.A. Barnett, P. Dauncey, D.C. Drewer




and J.A.J. Matthews, The MARK II silicon stripvertex detector, Nucl. Instr. Meth. A313 (1992)63

[23] F. Krummenacher, Pixel detectors with localintelligence: an IC designer point of view, Nucl.Instr. Meth. A305 (1991) 527 (2nd Leuven Work-shop)

[24] M. Campbell, E.H.M. Heijne, G. Meddeler, E.Pernigotti and W. Snoeys, A readout chip for a 64x 64 pixel matrix with 15 - bit single photoncounting, IEEE Trans. Nucl. Sci. NS-45 (1998)751 also CERN-ECP/97-010

[25] R. Ballabriga, M. Campbell, E. H. M. Heijne, X.Llopart and L. Tlustos, The Medipix3 Prototype,a Pixel Readout Chip Working in Single PhotonCounting Mode with Improved SpectrometricPerformance, IEEE Nucl Science Symp. Confer-ence Record 2006, p 3557

About the authorErik Heijne (F '77) studied physics atthe University of Amsterdam, where heassisted in projects on hydrogen/deuteri-um in palladium (1969) and on quantumeffects in thin silicon films (1970). Hecame to CERN in Geneva in 1973, towork on silicon detectors for the moni-

toring of the neutrino beams. In 1980 the introductionof the silicon microstrip detector opened new ways forcharm and beauty physics. A stay in Leuven (B) in1984 led to the start of a microelectronics design groupat CERN. Learning through different contacts in theIEEE, around 1995 he introduced at CERN the ideas forradiation hardness by design, which eventuallybecame the basis for widespread use of CMOS in col-lider experiments. He is a Fellow of the IEEE and in1999 received the Merit Award of the IEEE Nuclear andPlasma Sciences Society.




Eric A. Vittoz was born on 9 May 1938 inLausanne, Switzerland. He obtained a Dipl.Ing. degree in 1961 from the Ecole Poly-technique de l’Université de Lausanne(EPUL) and a Ph.D. degree in 1969 fromthe Swiss Federal Institute of Technology inLausanne (EPFL), both in Electrical Engi-

neering. After spending one year at EPUL as a researchassistant, he joined the Centre Electronique Horloger S.A.(CEH), Neuchâtel, in 1962, where he participated in thedevelopment of the first electronic wristwatch. Heworked out various possible approaches for very low-power crystal oscillators and frequency dividers in bipo-lar technology, and co-published the first low-voltageCMOS integrated frequency divider in 1969.

In 1971, Dr. Vittoz was appointed vice-director ofCEH, supervising and working on advanced develop-ments in electronic watches and other micropower sys-tems. While developing CMOS frequency dividers thatbecame the standard in Swiss watches, he introduced thefirst true single-clock logic circuits. He later pioneeredseveral new techniques for low-power and low-voltageCMOS analog design. These include circuits based onweak inversion operation (that he first applied to thewatch crystal oscillators), bipolar-operated MOS transis-tors and pseudo-resistive circuits. These techniques wereprogressively applied to other low-power systemsincluding biomedical devices, hearing aids, pagers, sen-sor interfaces and various portable instruments.

Together with several colleagues and students atCEH and EPFL, Dr. Vittoz progressively developed amodel of the MOS transistor applicable to low-currentand low-voltage circuit design, which later becameknown as the EKV model. He recently co-authored abook on this original model with Christian Enz.

In 1984, he joined the newly created Swiss Center forElectronics and Microtechnology (CSEM) in Neuchâtel,

where he was appointed Executive Vice-President, respon-sible for Integrated Circuits and Systems from 1991 to 1997and for Advanced Microelectronics later. While pursuinghis work on very low-power systems, he championed theidea of biology-inspired collective processing by means ofanalog VLSI; his team has since developed several inte-grated vision systems based on this concept. From 1999 to2004, he was partially retired from CSEM, with the positionof Chief Scientist. He is now fully retired from CSEM.

In 1975, Dr. Vittoz introduced the first course on ICdesign at EPFL, emphasizing low-power devices andcircuits. Becoming Professor in 1982, he lectured andsupervised undergraduate and graduate student proj-ects in analog circuit design until his retirement in2004. He is still connected with EPFL as an invitedprofessor, co-supervising some Ph. D. student proj-ects. He has participated and still participates innumerous post-graduate and summer courses there,and in many countries around the world.

A Life-Fellow of IEEE, he has published more than 140papers and holds 26 patents, receiving the Gold Medalfrom the Swiss Society of Chronometry and three ESS-CIRC best paper awards. He is an ESSDERC/ESSCIRC Fel-low, after contributing to the organization of these Euro-pean conferences for more than 25 years. He was also amember of the European Program Committee of ISSCCfrom 1977 to 1989. As European representative to theIEEE Solid-State Circuits Council from 1987 to 1989, heparticipated in the creation of the SSC Society as one ofthe first AdCom members, and gave lectures for manyyears as a SSCS Distinguished Lecturer. He was the recip-ient of the 2004 IEEE Solid-State Circuits Award “For pio-neering contributions to low-power modeling and CMOScircuit design.”

Besides enjoying life with his family, Dr. Vittoz stillpursues technical activities in teaching, writing and spo-radically consulting in low-power circuits and systems.



PEOPLE

Ankush Goel of USC andShih-An Yu of ColumbiaUniversity have won the

Solid-State Circuits Society Predoc-toral Fellowship for 2008 - 2009.Their advisors are Hossein Hashe-mi and Peter Kinget, respectively.

This year the Society had ninevery qualified nominees, sevenfrom U.S. Universities and oneeach from China and India. Thenominations were reviewed andranked by a team of four profes-sors from leading universities.(None of these universities hadnominees in the running for thisyear’s awards.)

According to the reviewingteam, Ankush and Shih-An “standout through their excellent aca-demic records combined with animpressive list of high-quality jour-nal and conference publications.”In addition, they said “the researchof the two recipients is very inno-vative and has the potential tohave significant impact on the fieldof solid-state circuits.” Please joinus in congratulating Ankush andShih-An for their achievements andfor receiving this year’s Fellowshipawards.

Ankush Goel received theB.Tech. degree in electrical engi-neering from the Indian Institute ofTechnology-Madras, Chennai, Indiain 2003. He was the recipient of theProf. Achim Bopp EndowmentPrize for best undergraduate hard-ware project. He received the M.S.degree in electrical engineeringfrom the University of Southern Cal-ifornia (USC), Los Angeles with aGPA of 4.0 in 2006. Earlier that year,he received an award from USC foroutstanding academic achievement.He is currently pursuing his Ph.D.degree at USC and is a researchassistant in the Electrical Engineer-ing - Electrophysics Department.

From 2003-2004, he was anAnalog Design Engineer withTexas Instruments, India. While hewas there, he designed a slew-ratecontrolled pad driver in digitalCMOS process for USB 2.0.

Mr. Goel is a recipient of the 2007USC Annenberg Graduate Fellow-ship. During the summer of 2008 hewas an intern at IBM T.J. WatsonResearch Center, NY, and workedon the design of a compact, low-power, low phase-noise, widebanddigitally controlled oscillator.

At USC, his research has focusedon analyzing nonlinear systemsexhibiting multiple modes of opera-tion and exploiting them for the

implementation of multi-mode multi-antenna reconfigurable radios. He hasdesigned and developed the theory ofconcurrent dual-frequency oscillators,dual-loop phased-locked loops andconcurrent phased-arrays. He haspublished two MTT papers and onein JSSC related to that work. Duringhis Ph.D. studies, he also workedon design and theory of sub-dBnoise-figure, high-gain, widebandLNA.

Shih-An Yu received the B.S.and M.S. degrees in electrical engi-neering from National Taiwan Uni-versity (NTU), Taipei, Taiwan in1999 and 2001, respectively. Forhis M.S. research, he worked onwideband amplifiers with multiplefeedback loops, and 5GHz VCOand image rejection receiverdesigns for ISM band applications.From 2001 to 2003, he designedself-calibrated fractional-N frequen-cy synthesizers and mixed-modeanalog baseband circuits for multi-standard mobile phone and WLANtransceivers at VIA TechnologiesInc., Taiwan. From 2003 to 2005,he was a research assistant at NTUand did research on quantizationnoise suppression in fractional-Nfrequency synthesizers. He alsodesigned the baseband circuits foran energy-efficient transceiver forlong-term wireless bioactivity mon-itoring applications, presented atthe ISSCC in 2006.

Since 2006, he has been work-ing towards his Ph.D. degree atColumbia University in New York,NY under the guidance of Prof.Peter Kinget. His research focuseson highly scalable design tech-niques for RF frequency synthesiz-ers addressing ultra-low supplyvoltage challenges, robustnessissues and area scaling challengesin extremely scaled CMOS tech-nologies. He has designed a 0.65V

Ankush Goel and Shih-An Yu Receive SSCSPredoctoral Fellowships for 2008-2009John Corcoran, SSCS Awards Committee, [email protected]

Ankush Goel

Shih-An Yu


PEOPLE


fractional-N 2.4GHz frequencysynthesizer that was presented atISSCC 2007. He was also part ofthe student team designing a 0.6Vhighly integrated receiver for2.4GHz applications in 90nmCMOS that was presented at ISSCC2008. His latest results on a0.042mm2 fully integrated dualband 2.5/5.0GHz analog PLL in a45nm CMOS technology will bepresented at ESSCIRC 2008. Thisultra-compact PLL incorporates acustomized stacked capacitor-inductor structure that overlays thetank inductor over the loop filtercapacitor, achieving a significantreduction of the active area. He isalso investigating architectures for

ultra wide-band, multi-standardfrequency synthesizers for soft-ware-defined radio applications.At Bell Laboratories, Alcatel-Lucent, Murray Hill, NJ, he is par-ticipating in the design of a frac-tional-N frequency synthesizeroperating from 50MHz to 8GHz.

Mr. Yu was the recipient of the2008 Outstanding Student DesignerAward presented by AnalogDevices, Inc. He has publishedeight papers in conferences and fivepapers in journals. He has one U.S.patent application under review.

The Solid-State Circuits Societygrants Predoctoral Fellowships eachyear to two deserving graduate stu-dents in the field of Solid-State Cir-

cuits. These Fellowships provide a$15,000 stipend and up to $8,000 intuition and fees for the student, andan additional $2,000 for the stu-dent's department. The awards aregranted to students who showpromise for outstanding doctoralresearch, and who have shownconcrete evidence of achievementearly in their graduate careers.Nominations are typically due byMay 1 of each year; see //sscs.org/awards/predoctoral.htm for moredetails on qualifications and theapplication process.

To view a list of prior Fellow-ship winners see //sscs.org/awards/predoctoral.htm#Pastrecip-ients.

IEEE DL Vojin Oklobdzija Visits Istanbul in May Focuses on Low Power Digital Design in Talks at Two Universities

IEEE Distinguished Lecturer Prof.Vojin Oklobdzija of UC Davisdelivered two talks on low power

digital design in Turkey, one on themorning of 29 May, 2008 at IstanbulTechnical University (ITU) and theother later that day at Bogazici Uni-versity (BU), also in Istanbul. Eachlecture attracted about 25 participantsfrom within the institution and fromneighboring universities, design com-panies, and research centers. Prof.Oklobdzija focused on the problemof increasing power consumption byhigh-complexity digital integrated cir-cuits, what prospects lie in the future,how power efficiency can bedefined, the effect of some parame-ters such as power supply and device

size on power efficiency, and somedesign suggestions to reduce powerconsumption. A long discussion fol-lowed each lecture. Prof Oklobdzijawas delighted by the contributions ofthe attendees, who in turn enjoyedand profited immensely from his talk.

ITU and BU are two of the lead-ing universities in Turkey. BU hasan active IC Design laboratory withcompetence in analog integratedcircuit design, CAD tool develop-ment, and low power design; ITUis becoming a center for IC design,with several national microelec-tronics-based studies and projectslocated at its VLSI Laboratory,which holds Europractice member-ship. Data converters, RF ICs, con-

tinuous-time filters and increasinglychaotic circuits with digital designare ITUís main areas of interest.

The IEEE Turkey Section is oneof the most rapidly developing sec-tions in Region 8, with around 15chapters and more than 40 studentbranches; both universities havevery strong competing IEEE Stu-dent Branches. At Dogus Universityan IEEE student branch organizesan annual student project contestentitled “PROJISTOR,” sponsoredby IEEE-Region 8, the IEEE TurkeySection, and local companies.

Izzet Cem GöknarCAS Professor, IEEE Fellow

IEEE-CAS Turkey Chapter

SSCS DL Prof. Vojin Oklobdzija lectured on 29 May, 2008 at Istanbul’s Bogazici University (left) and at Istanbul TechnicalUniversity (right).



PEOPLE

Daniel Brookshire Dallas SectionDorin Calbaza Toronto SectionJames Chu Atlanta SectionFrank Dunlap San Francisco SectionLuiz Franca Neto Santa Clara Valley SectionPrince Francis Toronto SectionKhosrow Ghadiri Santa Clara Valley SectionSteven Gillig Chicago SectionAlireza Kaviani Santa Clara Valley SectionRonald Kubacki Santa Clara Valley Section

C. Andrew Lish New Hampshire SectionChao Lu Santa Clara Valley SectionWing Luk New York SectionRon Maltiel Santa Clara Valley SectionMohammad Monzer Mansour Lebanon SectionJoo Tham Santa Clara ValleyAntonio Mondragon Torres Dallas SectionVladislav Potanin Santa Clara Valley SectionMohammad Shakiba Toronto SectionRoger Sheppard Oregon Section

Congratulations New Senior Members20 Seniors Elected in May, June and July and August

Tools: Tips for Making Writing EasierPart 3: Focus on Your Key Message

Peter and Cheryl Reimold, www. Allabout communication.com

In the last two columns we dis-cussed quick ways to structureyour writing to ensure that you

tell your readers what they want toknow in a format they can easily fol-low. Now we come to the writingitself: putting one word after theother. To choose the best words andplace them in the most readableorder, focus on your message. Whatexactly are you trying to say? If youfind yourself getting tangled up infuzzy words and complicated struc-tures, stop and ask yourself just that:What am I trying to say? Don’t writea thing until you are satisfied withyour answer. Then try the followingsuggestions.

Trust your voice. Don’t just trust it—use it. Say your sentences to yourself(quietly!) before you commit them tothe paper or screen. Mouth them,whisper them; utter them any wayyou choose but do not put them onpaper until you have heard them.After a while you will find that youhear them in your mind as you writethem. Then you can dispense withthe embarrassing mumbles.

This is the most important rule forclear and simple writing. Almost allthe puffy polysyllabic verbiage peo-ple produce in the name of businessor technical writing would neverarrive to torture its readers if the writ-ers had been forced to say the mes-sage out loud first. Can you imagineyourself saying, “Per our discussion,enclosed are copies of the docu-ments referenced in our conference

paper”? Of course not! You wouldprobably say, “Here are the threearticles you requested,” and then listthe titles, thus giving the reader moreinformation in much easier language.Don’t worry about sounding tooinformal if you trust your voice. Inap-propriate or inelegant words willjump out at you as you read overyour piece (which you must alwaysdo). In the example you might havesaid, “Here are the three articles youasked to see.” Although this is stillnot nearly as bad as the originalpompous statement, it could besmoother. Check your action words.If you find strings of small words(like asked to see), try to substitute asingle verb (like requested).

Put your main thought in themain parts of the sentence: thesubject, verb, and object. Becausewe tend to think and speak directly,you will usually follow this rule ifyou trust your voice. Overcomplicat-ed, wordy writing almost always vio-lates it. It is an easy rule to test, andit can clarify your sentences mostwonderfully. Here is an example.The fact that we rewarded all ideasin the brainstorming meeting hadthe effect of inducing more solu-tions. Here the subject is fact, theverb had, and the object effect. Theresult— fact had effect—is meaning-less. Let’s try a rewrite. Rewarding allideas in the brainstorming meetingproduced more solutions. Here thesubject is rewarding, the verb pro-duced, and the object solutions. The

result—rewarding produced solu-tions—captures the essence of thesentence.

Put the most important wordsat the end of the sentence.In English, the last words get the mostemphasis. To get the reader to focuson the main point of your sentence,try to put it there. Consider somefamous sentences: To be or not to be,that is the question (Shakespeare).When you come to a fork in the road,take it (attributed to Yogi Berra). Eitherthat wallpaper goes, or I do (said to bethe last words of Oscar Wilde). Nowlook what happens if we reverse theorder: The question is whether to beor not to be. Take a fork in the roadwhen you come to it. Either I go orthat wallpaper does. Enough said.

Cheryl and Peter Reimold havebeen teaching communication skills toengineers, scientists, and business peo-ple for more than 20 years. Their firm,PERC Communications (+1 914 7251024, [email protected]), offers busi-nesses consulting and writing services,as well as customized in-house courseson writing, presentation skills, and on-the-job communication skills. Visittheir Web site at http://www.allabout-communica tion.com.This article isgratefully reprinted with permissionfrom the authors as well as permis-sion from the IEEE ProfessionalCommunication Society NewsletterEditor. This article is reprinted fromthe July/August 2003 issue, Volume47, Number 4, page 10 of the IEEEPCS Newsletter.


CONFERENCES


As the world’s leading forum for the presenta-tion of advances in solid-state circuits and sys-tems-on-a-chip, the International Solid-State

Circuits Conference offers a unique opportunity forengineers working at the cutting edge of IC designand use to maintain technical currency and to net-work with leading experts.

Here are some highlights of the Society’s flagship SanFrancisco-based conference as of the time of print; cor-rections and details may be found in the official AdvanceProgram published in November. The web site for con-ference registration will open at the end of November.www.isscc.org/isscc. Forums, Tutorials, and the ISSCCShort Course require special registration.

In 2009 there will be four plenary presentations,approximately 250 technical papers and nine eveningpanels/special evening sessions, with panelists to beannounced; all are included in the registration price.The schedule and details of the all-day Short Courseon “Low-Voltage Analog and Mixed-Signal CMOS Cir-cuit Design,” the eight circuit design forums, and the

ten 90-minute tutorials still under development will bepublished on the conference site.

Theme: Adaptive Circuits and SystemsAlong with the numerous topics that registrants and read-ers have come to expect from the ISSCC, many papersamong the 250 in 2009 will focus on the theme “Adap-tive Circuits and Systems.” Contributions were encour-aged from researchers and designers who have demon-strated novel adaptive circuits and system techniques inthe subject.

Technology scaling is enabling the integration of vastsystems, encompassing billions of transistors on a singlesilicon chip. Along with opportunities for integration,sub-50nm technologies present new challenges ofdevice variability, reliability, and low voltage operation.Environmental constraints on power consumption andcooling are further complicating the design space.Adaptive circuits and systems offer the potential todynamically optimize operating parameters such as per-formance and power.

ISSCC 2009 Feb 8-12 Preview Anne O’Neill, SSCS Executive Director, [email protected]

ISSCC Student Forum 2009Anne O’Neill, SSCS Executive Director, [email protected]

ISSCC’s Student Forum features the highly acclaimedcommunications challenge for hi-tech, the 5-minutepresentation. It will return to ISSCC in 2009 on Sun-

day afternoon, February 8 and extend into the eveningwith poster presentations.

The objective of the ISSCC Student Forum is to pro-vide a networking venue for students to exchangeideas at an early stage in the graduate educationprocess. The presentation opportunity exposes stu-dents to ISSCC quality and encourages future papersubmissions. The five minute limit on presentationsprovides a challenge that improves communicationskills and will continue this year with shorter and morefocused dialogs during the evening poster sessions.

Speakers for the Student Forum will be selectedbased on a brief recommendation letter from the advi-sor (1 paragraph) and research results (a 200 to 250-word abstract and 4 to 6 Power Point slides). Work in

progress is expected, and results with actual siliconimplementation are highly encouraged. Papers thathave been accepted at ISSCC will not be considered forthe Student Forum. However, papers that significant-ly extend an ISSCC publication will be considered.Submission will be via the ISSCC web site and arelimited to one per faculty advisor. There will be 30to 40 presentations selected with effective regionalbalance in mind.

Presentations at the Student Forum are not consid-ered ISSCC papers; they will not be published or ref-erenced as a paper, and do not constitute prepub-lication.

For details about submission see www.isscc.org/isscc/studentforum/ (The deadline is October 31,2008). Please contact Professor Anantha Chandrakasan(Student Forum Chair) at [email protected] , TEL:617-258-7619, if you have any questions.



CONFERENCES

4th Asian Solid-State Circuits Conference - DigitalConvergence for a Ubiquitous LifestyleMore than 100 Papers Selected for Meeting on 3 – 5 November, Fukuoka, Japan

Koji Kito, A-SSCC 2008 Organization Committee Chair, [email protected]

The fourth Asian Solid-State Circuits Conferencewill be held on November 3 - 5, 2008, in Fukuo-ka, Japan, at the JAL Resort Seahawk Hotel locat-

ed on the scenic waterfront of the city. Sponsored bythe IEEE Solid-State Circuits Society, this annual confer-ence has travelled around major Asian countries includ-ing Taiwan (2005), China (2006), and Korea (2007). Itoffers a unique opportunity for engineers, researchersand business leaders to come together on-site toexplore the future of circuit design technologies and tofeel the influence of Asian countries in the rapidly glob-alizing IC industry. The theme of this year’s conferenceis “Digital Convergence for a Ubiquitous Life Style.”

Plenary TalksThree plenary talks will be presented by distin-guished leaders in the IC industry:

The first speaker, Mr. Yoshiaki Kushiki, Senior Fel-low of Panasonic (Japan) will give a speech entitled“Aiming for an Environmental-Oriented CE Platform.”

The second speaker, Dr. Young Hwan Oh, Presi-dent and CEO of Dongbu HiTek Semiconductor(Korea) will talk on “Foundry- Fabless Collaborationfor Semiconductor SoC Industry in Korea.”

The last speaker, Dr. Bill Krenik, CTO of TI (USA)will give a talk on “4G Wireless Technology: Whenwill it Happen? What does it Offer?”

Submissions Represent 26 CountriesA-SSCC 2008 received 309 paper submissions, ofwhich 116 were selected for presentation. The papersubmission distribution is: Taiwan 68, Japan 53, China51, Korea 42, USA 22, India 14, Iran 11, Singapore 11,Canada 6, Vietnam 5, Sweden 4, Belgium 3, Australia2, Finland 2, Hong Kong 2, Poland 2, Switzerland 2,Austria 1, Egypt 1, Germany 1, Malaysia 1, Netherlands1, Portugal 1, Spain 1, Romania 1, United Arab Emi-rates 1. Since the TPC consist of a balanced mix ofexperts from both industry and academia, the finaltechnical program covers the interests of attendeesfrom most IC product segments.

Four Tutorial Sessions and Two PanelsTutorials on November 3rd are “Design of Femto-jouleEnergy Efficient ADCs in CMOS,” ”Advanced SiPDesign,” “Economic and Design Choices for Nano-scaleElectronic Systems,” and “Advanced Clock DistributionSystems.” The two panel discussions on 4 November areentitled ”SiP2.0: What, When, and How?” and “DigitallyAssisted Analog and RF Circuits: Potentials and Issues.”

Industrial ProgramIn A-SSCC’s unique “Industry Program,” speakers pres-ent cutting-edge product chips, not only in a detailedchip or circuit description but also through demonstra-tions and evaluation results to show how customershave improved their performance by using the chips.

Student Design ContestAuthors of the eight outstanding chip designs acceptedfor the conference program will offer demonstrationsand commentary at the conference site. The studentdesign that best reflects the high research standards ofAsian academies will be selected from the eight.

I am looking forward to seeing you in Novemberin Fukuoka, and hope that you will enjoy an excel-lent meeting and warm hospitality at the conference.

For more detailed information about A-SSCC,please visit the web site: www.a-sscc.org

Mr. YoshiakiKushiki

Dr. Young HwanOh

Dr. Bill Krenik


CONFERENCES


Already past its 25th anniversary, the Internation-al Conference on Computer-Aided Design(ICCAD) continues to evolve with an outstand-

ing technical program in 2008. Offering high qualitytechnical papers, interactive panels, networking recep-tions, and embedded and stand-alone tutorials, ICCADwill also open its doors to new external workshops,which will be collocated with the conference and willleverage the professional management for which it isknown.

Outstanding Keynotes and Special Talks in Emerg-ing FieldsIn the opening session, a keynote address by MaryLou Jepsen, founder and CEO of Pixel Qi and chiefhardware architect and first CTO of the “One Laptopper Child” project will focus on innovating computingplatforms for emerging low-income geographies. Dr.Jepsen will also speak on CAD for displays.

Our second keynote will feature the world-renowned Dmitri “Mitya” Chklovskii, of Janelia Farm,Howard Hughes Medical Institute, whose research ison the human brain and how it relates to conven-tional computers.

During lunch on Tuesday, November 11, Giovannide Micheli, a distinguished EDA (Electronic DesignAutomation) veteran will discuss exciting new fron-tiers in biology and environmental engineering.

World Class Technical and Non-technical ProgramICCAD continues to be the ideal place for discover-ing top design technology innovation and staying on

top of emerging design fields. This year’s meetingoffers superb papers and tutorials within a venue formaintaining and growing one’s network and touch-ing base with all aspects of the electronic designautomation sector.

From 458 worldwide submissions, a 90-strong tech-nical program committee selected 122 outstandingpapers for presentations split into 40 sessions overthree days. ICCAD will also feature four half-day tuto-rials plus three embedded tutorials and two specialdesigner sessions providing additional broad per-spectives. To enable registrants to attend tutorials andcollocated workshops, tutorials will run in parallelwith technical sessions, while workshops will be heldon Sunday and Thursday.

Recognizing the increasing value of networking,ICCAD will host numerous social events and meetingsdesigned to keep attendees in touch with like-mind-ed colleagues. These events include ICCAD’s tradi-tional Monday evening panel on the future of tech-nology plus numerous meetings for CEDA, SIGDA,DATC, and other organizations.

About ICCADThe International Conference on Computer-AidedDesign (ICCAD) is the world’s premier conference inelectronic design technology and has served EDA anddesign professionals for the last 25 years by high-lighting new challenges and breakthrough innovativesolutions for integrated circuit design technologiesand systems. To learn more, please visit the ICCADwebsite at www.iccad.com.

The International Conference on Computer AidedDesign (ICCAD) Previews Novel ProgramExternal Workshops will Collocate with ICCAD on 10-13 November in San Jose

Juan Antonio Carballo, ICCAD Publicity Chair, [email protected]



CONFERENCES

ICUWB 2009 to Focus on Microvaveand Millimeter Wave Band TechnologyIEEE International Conference on Ultra-Wideband Will Meeton 9–11 September 2009 in Vancouver

Lutz Lampe, General Chair, 2009 IEEE ICUWB, [email protected]

The IEEE International Conference on Ultra-Wideband (ICUWB) of 2009 will center aroundthe general topic of UWB transmission in

micro-wave and millimeter wave bands and overpower lines.

Continuing a series of annual international UWBconferences held in Baltimore (2002), Reston-VA(2003), Oulu (2003), Kyoto (2004), Zurich (2005),Waltham-MA (2006), Singapore (2007), and Hannover(2008), it will focus on the latest advances in UWBtechnology, current and future applications rangingfrom UWB communication for personal area and sen-sor networks to UWB-based localization and posi-tioning systems to UWB vehicular radar and imagingsystems, and standardization and regulation for UWBtransmission.

The conference venue is the Hyatt Regency Vancou-ver, located in the heart of the city. Main technical andsocial functions will be held at the Hyatt’s PerspectivesLevel on the 34th floor, from which ICUWB attendeeswill have a stunning picture-postcard view of Vancou-ver and its surrounding scenery. The social programincludes a welcome reception, luncheons, and the galaconference banquet,

ICUWB has evolved since 2002 into the leadingannual conference solely dedicated to UWB technol-ogy, bringing together more than 200 researchers andengineers from academia, industry, government andstandardization organizations, as well as vendors and

customers of UWB technology. The ICUWB programof 2009 will feature invited plenary sessions and sym-posia by international experts and new product dis-plays by market leaders in the field.

The technical program will extend over three fulldays and include topics in • UWB Hardware Architecture and Implementation

(RF modules, circuits and systems, low power con-sumption techniques, pulse generation and detec-tion, OFDM implementations, integrated circuitsdesigns, and system architectures)

• Antennas and Propagation (UWB antennas and arrays,channel measurements and modeling, field trials)

• UWB Cognitive and Cooperative Systems (energyefficient cross-layer design, spectrum sensing anddynamic spectrum sharing)

• Communication and Signal Processing (coding andmodulation, ranging, localization and positioning)

• Applications (wireless personal/body area net-works, sensing and medical imaging, home net-working, radar, consumer electronics)

• Standardization and Regulation (spectral manage-ment, co-existence, emerging wireless standardiza-tions).Prospective authors are invited to submit technical

papers until 23 February 2009. All accepted papers willbe published by the IEEE and included in IEEE Xplore.

For more information visit the 2009 ICUWB web-site www.icuwb2009.org.


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The annual meeting of theIsraeli Chapter of the Solid-State Circuits Society took

place at the Hilton Hotel in Tel Avivon 13-14 May, 2008 within theframework of the first IEEE Confer-ence on Microwaves, Communica-tions, Antennas, Solid-State Circuitsand Electronic Systems (IEEE COM-CAS 2008).

Building on the yearly IEEEIsrael AP/MTT & AES ChaptersSymposium, this exciting, two-day conference and expositionwas organized as a multidiscipli-nary forum for internationally rec-ognized scientists and engineersand students from various com-plementary disciplines to meetand discuss subjects of commoninterest.

Last year’s very successful 21stIEEE AP/MTT&AES Chapters Sym-posium, with over 500 participants

from many companies and R&Dinstitutions, encouraged andinspired the organizers to workwith other IEEE societies to takeon the challenge of organizing aneven greater event with the help ofthe larger IEEE and global techni-cal community. The three addition-al IEEE societies, namely the Solid-State Circuits Society (SSCS), theCommunications Society (Com-Soc), and the ElectromagneticCompatibility Society (EMCS)joined forces with the MicrowaveSociety (MTT-S), Antennas andPropagation Society (AP-S), andAerospace & Electronic SystemsSociety (AES-S) to create thismega-event.

COMCAS 2008 delivered on thepromise of attracting the globalcommunity to Israel, with over 700participants, 146 papers, 15 techni-cal sessions, five parallel meeting

rooms and a large professionalexhibition with 62 booths. Theprogram offered a very impressivelist of speakers, including expertR&D engineers, top scientists andmanagers from Asia, the US,Europe, Latin America, the Far Eastand Israel.

The disproportionately largenumber of solid-state circuit con-tributions required the extensionof the original, one day SSCS ses-sion to two full days. On the first,Tuesday, May 13, there wereeight papers in Analog/MixedSignal and five papers on VLSI/SoC/Sensors. On Wednesday,May 14, there were four paperson VLSI/SoC/Sensors, 14 paperson RFICs, and three papers on SiMEMS.

There were two keynote speak-ers: The first was Raviv Melamed,General Manager, Mobile Wireless

First IEEE COMCAS a Mega Event in Tel AvivSSC Sessions Span Two Days

Mark Ruberto, IEEE Israel Chapter Chair of the Solid-State Circuits Society, [email protected],Shmuel Auster, COMCAS Conference Chair, [email protected],Barry Perlman, COMCAS Technical Program Chair, [email protected]

Group lunch at COMCAS 2008 on the MediterraneanCoast of Israel.

62 exhibitors operated booths at COMCAS 2008.



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Group, Intel Corp., Haifa, Israel.The title of his talk was “FutureWireless Applications and Tech-nologies.” The second keynotespeaker was Prof. Linda Katehi,Provost, University of Illinois, USAwhose talk was entitled “AdvancedComponent Architectures.” Bothkeynote addresses were very wellreceived.

Other conference sessions hadan interesting breadth of technicalpapers, from leading edgemicrowave devices, ingeniousarchitectures, advanced analogand mixed-signal circuits to cleverantenna technology, and informa-tion on new and old RADAR andcommunication systems. Manylocal practitioners, engineers anddecision makers from the technol-ogy, communication, radar andelectronic systems communitiesparticipated and many presentedpapers on technology, circuits, sys-tem aspects and innovations inthese fields. Fascinating up-to-datetopics were also presented toenrich the microwave, antenna,communication, EMC, solid-statecircuits (RFIC) and electronic sys-tems communities with knowl-edge, ideas, applications and chal-lenges. Emphasis was on applica-tions-oriented research and devel-opment, from devices and compo-nents to circuits and systems, toantennas, communications andnetworking, sensors and radar andsoftware, on a variety of subjectsincluding• FICs• Low Power Solid-State Circuits• Microwave Plasmonics and Nano-

meta materials• Novel Antennas and Spectrum

Data Base Issues• Phased Arrays, Communications

Networking• C3/C4 modeling and simulation,

and analysis (MS&A)• RF Propagation to MMW Wave-

lengths• High Power Amplifiers• Advanced Devices for Commu-

nications• RF Filters, Modeling for EMC,

MEMs• Ultra-wide Band Technology• Metrology and Parameter Extrac-

tion• Space-time Adaptive Processing• Cognitive Radios/Radar and

Spectral ProcessingCOMCAS 2008 was chaired by

Shmuel Auster of Elta Systems. TheTechnical Program Chair was Dr.

Barry Perlman, U.S Army Commu-nications-Electronics RD&E Center(CERDEC) and incoming MTT-SPresident. SSCS Technical Sessionswere organized by Mark Ruberto,SSCS Israel Chapter Chair, DavidGidony, and Miki Moyal, all fromthe Israel Design Center of IntelCorporation.

The full technical program canbe seen on the conference web-page at www.comcas.org, andpapers from the conference arenow available in IEEE Xplore. It isthe intent of the Israel SSCS Chap-ter to participate annually in sub-sequent COMCAS conferences asthe main venue for its annual tech-nical meeting, and to encourage alarger foreign participation as well.

COMCAS 2008 keynote speakers were Linda Katehi and Raviv Melamed.

Mark Ruberto (center), a COMCAS 2008 Technical Session organizer, receivinga certificate of appreciation from COMCAS Chair Shmuel Auster (left) and BarryPerlman, COMCAS Technical Program Chair.


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To encourage submissions toISSCC from industry in Asia,SSCS-Singapore hosted an

ISSCC 2009 promotional event inAugust featuring a replay of the2007 Conference tutorial “Continu-ous-time Sigma-Delta Data Con-verters” by Yiannos Manoli.

Spearheaded by Prof. Yong PingXu., Singapore Chapter Treasurer,in cooperation with the Departmentof Electrical and Computer Engi-neering of the National Universityof Singapore, the event was open toacademics and students and attract-ed 24 from industry. Admission wasfree and light refreshments wereserved. Dr. Xu also moderated thereplay of the Manoli tutorial as wellas a presentation of the audio tuto-rial “Writing a good ISSCC paper,”created by ISSCC Press/AwardsChair Kenneth C. Smith and pastISSCC Program Chair Prof. Jan Vander Spiegel of the University ofPennsylvania, who is SSCS ChaptersChair. It is available at the Societyíswebsite //sscs.org/Chapters/07ChptL-nch/ 07FEBCafe.htm.

SSCS-Singapore expects to holdmore ISSCC 2007 DVD replayevents at Nanyang TechnologicalUniversity and at other sites.

Katherine Olstein, SSCS Administrator,

[email protected]

SSCS-Singapore Hosts 90 at ISSCC 2007 Tutorial inAugustDVD Replay Combined with Colloquium on How to Write an ISSCC Paper

Prof. Yong Ping Xu moderating an ISSCC DVD tutorial replay at the National University of Singapore in August.



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Integrated radios for multi-GHzfrequencies have recentlymigrated to low-cost nanome-

ter-scale CMOS processes. Unfortu-nately, this environment, which isoptimized for digital circuits, isextremely unfriendly for conven-tional RF and analog designs. As aresult, a paradigm shift is occurringthat transforms RF and analog cir-cuit design complexity to the digi-tal domain for wireless transceiversto enjoy the benefits of digitalapproaches, such as process nodescaling and design automation.

In light of this shift, SSCS-Taipeiinvited Dr. Bogdan Staszewski ofTexas Instruments to give a two-day short course on the subject ofCMOS single-chip radio design.

Approximately 45 participantsattended his lecture “Digital RFProcessor (DRPTM) for Single-chipMobile Radios: All-digital PLL, Trans-mitter and Discrete-time Receiver” atNational Chiao-Tung University inHsinchu, and 35 attended the samecourse at National Taiwan University,Taipei, on August 20 and 21, 2008,respectively. Participants fromindustry and academia were aboutequal, an indication that the topicelicited wide interest from the Tai-wanese IC research and develop-ment communities.

Dr. Staszewski began with anintroduction to the DRP approachand explained how it was con-ceived initially. He then describedthe design principles of an all-dig-

ital phase-locked loop (ADPLL).Various aspects of ADPLL design,including theoretical analysis, sys-tem modeling, sub-circuit designs,and simulation considerationswere discussed, including transmit-ter design based on the ADPLL. Dr.Staszewski next presented a direct-sampling discrete-time receiverdesign and several more designexamples.

His course, which included agood mix of theoretical and practi-cal design knowledge, was well-received and considered valuablefor the research of many attendees.

The Taipei Chapter greatlyappreciates the financial supportof the IEEE Solid-State CircuitsSociety for this program.

SSCS-Taipei Offers Short Course on CMOS Single-chip Radio DesignPrograms in Hsinchu and Taipei Funded by SSCS Extra Chapter Subsidy

Eric Tsung-Hsien Lin, IEEE SSCS Taipei Chapter, [email protected]

Dr. Bogdan Staszewski of Texas Instruments presenting his lecture on CMOS single-chip radio design at National Chiao-Tung University, Hsinchu, on August 20, 2008 (left) and at National Taiwan University, Taipei, on August 21, 2008 (right).


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SSCS DL Stefan Rusu Speaks at Santa Clara ValleyChapter Meeting in AugustKatherine Olstein, SSCS Administrator, [email protected]

SSCS DL Stefan Rusu, a SeniorPrincipal Engineer at Intel Cor-poration, addressed the Soci-

ety’s Santa Clara Valley chapter on21 August about “Power and Leak-age Reduction in the NanoscaleEra.” One attendee, HimanshuArora said, “I rate his talk among thetop 1% of presentations that I haveever attended at IEEE local meetings.”The slides that Dr. Rusu used may befound on the chapter website, at//ewh.ieee.org/r6/scv/ssc/index.html.

Lectures by Ali Niknejad of UCBerkeley, Michael H. Perrott ofMIT and Boris Murmann of Stan-ford are planned for the chapter’sSeptember, October and Novem-ber meetings, respectively.

Prof. Niknejad will speak onresearch at the Berkeley WirelessResearch Center (BWRC) related tomm-wave electronics, includingactive and passive design techniques;circuit approaches, and system archi-tecture for short range mm-wave

communication links; and the designof several key building blocks, suchas the LNA, mixer, and PA.

Dr. Perrott (now with SiTime, Sun-nyvale, CA) will discuss the imple-mentation advantages provided bydigital phase-locked loops comparedto their analog counterparts, andexplore the question of whether suchdigital structures can support highperformance applications in which

low jitter and high PLL bandwidth isrequired by discussing techniques forachieving high performance digitalfractional-N synthesizers, includinghigh resolution time-to-digital conver-sion, digital quantization noise can-cellation, and low-jitter divider struc-tures. Prof. Murmann will present“Future Directions in Mixed-Signal ICDesign” in his talk. The Santa ClaraValley Chapter Chair is Dan Oprica.

SSCS-Scotland Sponsors Technical Meeting in SeptemberK. Kundert Speaks on Verification of Complex Analog Circuits

Jim Brown, SSCS-Scotland Chapter Chair, [email protected]

Around 40 people from localindustry and academia gath-ered at the Central Edinburgh

offices of Dialog Semiconductor on28 September, 2008 to hear Dr. KenKundert talk about Verification ofComplex Analog Integrated Circuits.The historic background of Edin-burgh Castle contrasted with a topicwhich is at the leading edge of tech-nology development.

Verification is becoming widelyrecognized as one of the mostimportant issues in designing largecomplex analog and RF mixed-sig-nal circuits. As a result, designmethodologies are starting tochange, mirroring a comparablechange in digital design 10-15years ago. In his presentation, Dr

Kundert showed why the problemhas become so significant, andwhat people are doing to control it.

Dr. Ken Kundert is Presidentand co-founder of Designer'sGuide Consulting, a company thatis guiding the industry towards theadoption of formalized analog ver-ification. He worked previously atCadence and HP, where he createdSpectre, SpectreRF, Verilog-A/MSand HP's (now Agilent's) harmonicbalance simulator. He has writtenthree books on circuit simulationand modeling and created "TheDesigner's Guide Community"website. He received his Ph.D. inElectrical Engineering from UCBerkeley in 1989 and was elevatedto the status of IEEE Fellow in Jan-uary 2007 for contributions to sim-ulation and modeling of analog,RF, and mixed-signal circuits.

From left: SSCS-Scotland members Dr.Sebastian Loeda and Dr. Paul Ham-mond, with Dr. Ken Kundert.

Dr. Stefan Rusu discussed nanoscale power and leakage reduction with mem-bers of SSCS Santa Clara in August.



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After the success of last year’sfirst Microelectronics Sympo-sium, the IEEE-Leuven Stu-

dent Branch and SSCS-Beneluxchapters again put their handstogether to organize a second sym-posium at the Electrotechnical Engi-neering Department of K.U.Leuven.

This year’s meeting set out toinvestigate how industry andresearch institutions cope with thevarious budgets encountered byengineers, in particular how con-straints, such as cost, energy con-sumption, and silicon area drive[or “empower”] them to go beyondthe current state-of-the-art.

Sponsored by On Semiconduc-tor (formerly AMIS) and NXP on 19March, 2008, the event included atotal of five speakers, who pre-sented their views on “Power ofBudget”:• Professor Wim Dehaene (K.U.

Leuven) gave an introductionto Wireless Sensor Networks(WSN) and presented the cur-rent status of the Flemish-fundedIWT-sbo Pinballs research proj-ect that focuses on the in-doorlocalization of ultra-low powerRFID nodes.

• Ramses Valvekens (EASICS) andTim Piessens (ICsense) reportedthe results of the fruitful cooper-ation between their companies,both spin-offs of K.U.Leuven, ona project concerning novel com-mercial RFID applications.

• Professor Willy Sansen (K.U.Leu-ven and SSCS President) elabo-rated on the question of whetherMoore’s Law will save microelec-tronics and whether there is sucha thing as “Moore than Moore.”

• Damien Macq (On Semiconduc-tor) presented an overview ofboth digital and analog commer-cial solutions currently availableto customers world-wide andthe different challenges encoun-tered during their development.

• Raf Roovers (NXP) covered thewhole design process fromresearch to the final developmentof a W-USB product in a wrap-upspeech, and shared his experi-ences in tackling different hurdles.

Leuven Student Branch and SSCS Chapters Organize2nd SSCS-Benelux Microelectronics Symposium Cedric Walravens, IEEE Student Branch, Leuven, [email protected]

From left, Raff Rovers (NXP), Willy Sansen (SSCS President), Damien Mac (OnSemiconductor), Ramses Valve kens (EASICS) and Cedric Walravens (IEEE Leu-ven Student Branch Chair). Missing from this picture are Wimp Deane (K.U.Leu-ven) and Tim Piessens (ICsense).

Preview of EDSSC2008 in Hong KongThree-Day Program in December to Feature 150 Papers and Plenary Talks by SSCS DLs T.Kawahara and I. Young

KP Pun, General Co-Chair, EDSSC'08,[email protected]

The 4th IEEE International Con-ference on Electron Devicesand Solid-State Circuits

(EDSSC 2008) will be held at theRenaissance Kowloon Hotel inHong Kong from 8 to 10, December,2008. The conference hotel is nextto the famous Victoria Harbour,where attendees can enjoy HongKong’s most beautiful night views.

Organized by the IEEE ElectronDevices/Solid-State Circuits HongKong Joint Chapter and sponsored bythe Hong Kong Applied Science and T. Kawahara and I. Young will deliver plenary talks at EDSSC in December 2008.


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Technology Institute and K. C. WongEducation Foundation, EDSSC 2008 isa three-day program covering broadareas in electron devices and solid-state circuits. It is expected that 150technical papers will be presented byauthors both from academia andindustry around the world.

Highlights of the conferenceinclude two plenary speeches by

renowned experts in the ED/SSCfields.

The first is “SPRAM (SPin-trans-fer torque RAM) Technology forGreen IT World,” by Dr. TakayukiKawahara, Chief Researcher, Cen-tral Research Laboratory, HitachiLtd., Japan.

The second is “The SOC trans-formation of the Microprocessor -

Clocking and Analog Circuits inHigh Performance Processors,” byDr. Ian Young, Intel Senior Fellow,and Director of Advanced Circuitand Technology Integration, Tech-nology and Manufacturing Group,Intel Corporation, USA.

Details about the conference canbe found at the conference web-site: www.ee.cuhk.edu.hk/edssc08.

IEEE SSCS Joint Chapter Formed in Penang,MalaysiaYut Hoong, Chow. Chapter Chair, IEEE MTT-ED-SSCS Joint-Chapter, Penang, Malaysia

Boon Eu, Seow. Secretary, IEEE MTT-ED-SSCS Joint-Chapter, Penang, Malaysia

Founded by Dr. Grant A. Ellisin 2005, Penang’s MTT/ED/AP chapter was the first

IEEE chapter in the Bayan LepasFree Industrial Zone, Penang,Malaysia.

A plan to start an IEEE SSCSchapter in Penang was startedby Mr. Boon Eu Seow in 2006,but delayed due to the insuffi-ciency of SSCS members there.Two years later, MTT/ED/APChapter Chair Mr. Yut HoongChow proposed that the AP unitof MTT/ED/AP be replaced bySSCS to better focus on relatedindustries in the Bayan LepasFree Industrial Zone. The groupwas reorganized officially on 15May, 2008 and renamed the IEEEMicrowave Theory and Tech-

niques Society, the IEEE Elec-tron Devices Society and theIEEE Solid-State Circuits Society(MTT/ED/SSC) joint chapter

A website that details the pres-ent and past activities of the chap-ter can be viewed at //ewh.ieee.org/r10/malaysia/mttedssc.

The Penang Chapter MissionThe IEEE Penang chapter hopesto support and accelerate thegrowth of electronic industries inits region by sponsoring andorganizing seminars and lecturesby subject matter experts. In thisregard, IEEE distinguished lectur-ers have been very supportive,delivering many well-receivedand well-attended lectures to ourgroup.

Penang - Malaysia’s “SiliconIsland”

Located in the north of Malaysia,Penang is one of the world’s high-tech manufacturing centers, withmore than 33 years of electronicsindustry activity, begun in 1972with the establishment of the firstFree Trade Zone in the country.

Penang's Bayan Lepas Freeindustrial Zone (FIZ) was started in1972 by YAB Tun Dr. Lim ChongEu, former Chief Minister ofPenang. Bayan Lepas FIZ. At thesize of 1300 acres, it serves as thecountry's free trade zone and hasbeen home for over three decadesto some of the world's top tech-nology companies, such as Intel,Motorola, Agilent Technologies,Robert Bosch, Osram Optosemi-

Map of Penang, courtesy of Penang RF Cluster, www.investpenang.gov.my/PRFC.php



CHAPTERSconductor, Seagate, AMD, Hitachiand Clarion.

Today, more than 700 transna-tional and local companies operatein the industrial parks in Penang,including Penang Biotech Park(also known as Penang SciencePark), Perai Free Industrial Park,Perai Industrial Park, SeberangJaya Industrial Park, Bukit TengahIndustrial Park, Bukit MinyakIndustrial Park and Mak MandinIndustrial Park.

The State, whose economy forover three decades has beenanchored in its manufacturing sec-tor, is now moving upstream toinclude R&D and product develop-ment. Multinational companiesincluding Motorola, Intel, Avago,Agilent, Altera, Renesas and Span-sion have set up significant R&Dcentres to design MMICs, two-wayradios, analog and digital ICs andmeasuring instruments.

Penang’s skilled and knowl-edgeable workers are strongly sup-ported and incubated by the insti-tutions of higher education in thestate, including the University ofScience Malaysia, Wawasan OpenUniversity at George Town, thePenang Skill Development Center(PSDC) at Bayan Lepas, and theMalaysia-Japan Technical Instituteat Bukit Minyak.

SSCS-Penang would like tothank Professor Jan Van derSpiegel of the University of Penn-sylvania and SSCS Administrator,Katherine Olstein for their adviceand support in setting up thechapter.

We would also like to take thisopportunity to thank our chaptersponsors, the Motorola Penang andPenang Skill Development Center(PSDC) for allowing us the use oftheir halls and facilities for ourchapter meetings and seminars.

ISSCC 2007 Short Course DVD Replayed in Penang inAugust, 2008

Attendees at SSCS-Penang’s DVD replay of "RF Transceiver System Design inNanometer CMOS" on 5 August, 2008. SSCS’s new table skirt may be seenon the right.

This presentation reviewed the history of transceiver design, whichhas led to the inclusion of all-CMOS transceivers in handheld phonesas a fast-becoming norm. It also examined the changes in the CMOSenvironment - the side effects of all those shrinking gates that aredriving the trend toward digitally assisted, and sometimes even dis-appearing, analog circuits. It also showed examples of how this trendis making itself felt in the RF arena.

AbstractIn articles, textbooks and research papers we are told again and againthat even as CMOS gate lengths become ever smaller, "the analogdoesn't shrink." But cell phones have gotten smaller somehow, andthe smart money says they will continue to pack more features in thesame or smaller form factor for some time to come.

Many of the secrets behind this apparent contradiction lie in IC sys-tem-level design. The RF transceiver designer is faced with myriaddesign choices that have huge impacts on overall IC performance;choosing the performance targets for the IC is not to be taken lightly.For example, just as in the digital and traditional mixed-signaldomains, a goal of minimizing die area as opposed to minimizing cur-rent draw can lead to a vastly different set of choices for the LNA,Mixer, baseband filter, and data converter parameters. Likewise, thoseever-shrinking gate lengths do indeed lead one to make sharp turnsalong the path toward the final block specifications.

Romania SSCS Chapter Formed to Promote CircuitActivities in Eastern EuropeMarcel Profirescu, Chapter Chair, [email protected]

After the. IEEE Romania Sec-tion was established in 1986,and EDS-Romania formed in

1992, I had the idea of founding an

SSCS Chapter for quite some timeto stimulate local activities in cir-cuits, and to promote circuit activi-ties in Eastern Europe. The con-

sensus among my colleagues, pro-fessors from other universities, andexperts from design houses wasthat a local SSCS chapter would


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help to support SSCS’s 30 membersin Romania and foster a strongerconnection between the academicand industrial circuit designresearch communities and theRomanian EDS Chapter. With theencouragement of Professors JanVan der Spiegel, SSCS ChapterChair, and Cor Claeys, EDS Presi-dent, I formed the chapter about ayear ago. It was the right moment toset up a solid-state circuits forum toenhance the influence of SSCS inthe area.

Shortly afterward, I attended thefirst SSCS pan-European ChapterChair Meeting in Munich on theoccasion of ESSCIRC 2007, where Italked to IEEE Region 8 officials,SSCS officers and European lead-ers. Of great help were ProfessorRichard Jaeger, then SSCS Presi-dent, Professor Jan Van derSpiegel, Anne O’Neill and Kather-ine Olstein, SSCS staff, and alsoProfessor Cor Claeys, EDS Presi-dent, and William Van Der Vort,Executive Director of EDS.

In October 2007, EDS and theemerging SSCS Chapter organizedNADE- (Nanoelectronic Devices),a very well attended mini-colloqui-um in Sinaia reported in the EDSNewsletter of January 2008, where15 well known internationalspeakers presented papers on nan-odevices and nanocircuits, Thismini-colloquium was organized onthe occasion of the 30th anniver-sary of the CAS-International Semi-conductor Conference, the equiva-lent of the ESSDERC/ESSCIRC con-ference in Eastern Europe. A firstmeeting of SSCS members was alsoheld in Sinaia. The chapter wassubsequently approved by SSCS,IEEE Region 8 and RAB, thanksto. the prompt help of JeanGabriel Remy, Region 8 Directorand Professor Willy Sansen, SSCSPresident.

The new SSCS-Romania Chap-

ter will respond to the interestsand needs of the local industrialand academic communities: Uni-versities with advanced researchtopics in IC design are spread allover Romania. In the past tenyears, many design houses havebeen established and their num-ber is expected to increase. Theshort range goals of the chapterinclude:• inviting distinguished lecturers

to local technical events;• co-sponsoring local conferences,

workshops and seminars;• increasing the number of SSCS

members;• fostering collaboration and the

cross fertilization of ideas amongSSCS and ED members;

• paying special attention to SSCSstudent activities to fulfill theneeds of the already demandingIC circuit and system designnational labor market.In the long run, the new SSCS

chapter is expected to increase thevisibility of IEEE and SSCS inRomania and to consolidate itscontacts with the international sci-entific communities.

Romania’s origins in semicon-ductor devices and ICs, both inacademic/research and design/manufacturing predates 1960. Atthe beginning of the 1960’s, a syn-ergetic interaction between thealready-consolidated academictrack and the newly launchedsemiconductor industry tookplace. A semiconductor schoolwas founded in Romania by Pro-fessor Mihai Draganescu, a bril-liant visionary who wrote a fun-damental book on ElectronicProcesses in Semiconductor Devicesand Circuits in 1962. It was a nat-ural out growth of the electronicsand telecommunications schoolestablished before the secondworld war by Professor TudorTanasescu, and of the Faculty of

Electronics and Telecommunica-tions at the University Politehnicaof Bucharest, established in 1953.There has always been a closetwo-way interaction between aca-demia, research and industry; Pro-fessor Roman Stere was CTO ofthe first foundry in Romania. Pro-fessor Draganescu founded ICCE,a semiconductor research institu-tion which continues today as theNational Institute of Microtechnol-ogy. Many generations of localsemiconductor college graduatesare now spread all around theworld.

About the Author

Marcel D. Profirescu graduatedfrom the Electronics and Telecom-munications Department of theUniversity Politehnica of Bucharestin 1964 and received a Ph.D. fromUniversity College, London in1974. He teaches ElectronicDevices and Circuits and TCAD,and heads two research centers inMicro and Nanoelectronics, re-spectively in ICT, and a Microelec-tronic Design company in Bucharest.Dr. Profirescu is an IET Fellow,IEEE Senior Member nominatedfor FIEEE, EDS Distinguished Lec-turer, ED and SSCS Romania Chap-ters Chair, the EDS SRC Vice Chairfor Europe, Africa and Middle Eastand the ED/LEO South AfricaChapter Partner.



SSCS NEWS

In a formal motion at its biannualmeeting on 19 August, 2008 inSan Francisco, the SSCS AdCom

endorsed the tone, scope, adminis-

trative structure, and budget of theIEEE Solid-State Circuits Magazineapproved by the IEEE TechnicalActivities Board (TAB) in June. It

also heard a work in progress reportfrom the ISSCC 2020 Task Force.

Launching in January 2009 as anofficial migration of the SSCSNewsletter, which had alreadygrown into a magazine, the IEEESolid-State Circuits Magazine willhave formal Editorial and AdvisoryBoards and expand upon the SSCSNews with the addition of regionalAssociate Editors, Technology Sur-veys, and Tutorials. For moreinformation about the conversionof the SSCS News into the Solid-State Circuits Magazine, pleaseread Anne O’Neill’s ExecutiveDirector column on page 7 of thisissue.

ISSCC Task Force Proposes Far-Seeing InnovationsCommissioned in 2007 to build along-term vision for the confer-ence, the ISSCCC 2020 Task Forcehas focused on broadening theconference venue beyond SanFrancisco and on migrating printmaterials to electronic formats,beginning with the conferencedigest.

Satellite Conference ProgramTo Maximize Global Attendanceand Minimize Travel CostsAccording to Task Force spokes-man Dennis Monticelli, ISSCC hasbeen structured for nearly half acentury as a must-attend yearlyevent in San Francisco in Febru-ary. The new satellite confer-ences are envisioned as a set, orsets, of regional events, eachbuilt around a collection of out-standing ePapers, and an eDigestfrom the mother conference, withlocally determined forums, work-shops, and social events, and alocally-determined admissionspolicy and business model tai-lored to the needs of the specificregion.

The satellite program promisesto “differentiate ISSCC from thecrowd” in the 21st century,” said

SSCS AdCom Endorses Newsletter-MagazineConversion in Summer MeetingISSCC Task Force Previews Ground-Breaking Initiatives

Katherine Olstein, SSCS Administrator, [email protected]

SSCS Staff Honored SSCS Executive Director Anne O’Neill and SSCSAdministrator Katherine Olstein were honored atthe AdCom’s Executive Committee meeting on19 August, 2008 for the excellence of their workon the Society’s enhanced newsletter and theirvision during its conversion to Magazine status.

SSCS Past President Richard C. Jaeger (left) and President Willy Sansen pre-sented SSCS Executive Director Anne O’Neill (third from left) and Adminis-trator Katherine Olstein with plaques in recognition of their work on theSSCS News and magazine migration.

At the meeting, Ms. O’Neill was presented with a plaque by Presi-dent Willy Sansen and Past President Dick Jaeger citing her foresightand leadership:

“The SSCS AdCom recognizes the outstanding vision and leadershipof Anne O’Neill in the elevation of the SSCS Newsletter to a Magazine.Her experience and coordination among IEEE staff and volunteersthroughout the world have been crucial to the continuing develop-ment of the publication.”Ms. Olstein was presented with a plaque recognizing her attention

to detail and outstanding management of the SSCS News: “The SSCS AdCom recognizes the outstanding execution and atten-tion to detail of Katherine Olstein in the elevation of the SSCSNewsletter to a Magazine. Her acquisition of Society news, editing,and interactions with authors, volunteers, and the IEEE staff hasbeen crucial to the continuing development of the publication.”It is wonderful to work with both Anne O’Neill and Katherine

Olstein as we migrate the SSCS News to the IEEE Solid-State CircuitsMagazine, debuting in Winter 2009.

Mary Yvonne Lanzerotti, Editor-in-Chief



Monticelli. Four SSCS chapters inAsia selected as beta sites for earlyMarch 2009 will be “a litmus testfor delivering our value to emerg-ing regions,” he said. SSCS Task-force members are Willy Sansen,C.K. Wang, Anantha Chan-drakasan, Yoshi Hagihara, andNicky Lu. Details about the ISSCCSatellite program will be reportedin the new Solid-State CircuitsMagazine and Society emails, andon the SSCS website.

In an additional AdCom announce-ment, Awards Committee ChairJohn C. Corcoran reported thatelected AdCom member Tom Leehas agreed to serve as the Society’srepresentative to the NationalInventors Hall of Fame, which willrank nominees for recognition in2009, the 50th anniversary of theintegrated circuit.

SSCS NEWS

CEDA Currents: IEEE/ACM MEMOCODE Contest Update Patrick Schaumont, Virginia Tech, Krste Asanovic, UC, Berkeley, James C. Hoe, Carnegie MellonUniversity

The second annual IEEE/ACM-MEMOCODE Hardware-Soft-ware Codesign Contest con-

cluded successfully on 9 March,2008. This annual contest was con-ceived for the ACM-IEEE Interna-tional Conference on Formal Meth-ods and Models for Codesign(//memocode-conference.com)tohelp highlight the issues distinct tohardware-software codesign and toexpand the conference’s emphasison design and practice. On 8 Febru-ary, 2008, a ‘‘secret’’ design probleminvolving the AES (AdvancedEncryption Standard) algorithm andsorting was revealed on the contestwebsite. Contestants were givenone month to produce workinghardware-software codesigned solu-tions, which would be judged onthe basis of performance and ele-gance of design. Eleven finalists suc-cessfully completed the design,from 27 original teams drawn fromdiverse geographic regions in theUS, Europe, and Asia. A panel ofjudges evaluated the final design

entries, and the winners were for-mally announced at this year’sMEMOCODE on 5-7 June, 2008 inAnaheim, California, which was col-located with the Design AutomationConference (DAC).

This year’s contest will award

two $1,000 cash prizes in the cat-egories of the Highest Perfor-mance Design and the Most Effi-cient Design. In addition, Xilinxis sponsoring a special $1,000cash prize for the best entryemploying a high-level designmethodology. Along with thethree of us (who organized thisyear’s contest), the panel ofjudges also includes Kees Vissers(Xilinx) and Satrajit Chatterjee(Intel). This year’s contest issponsored by Nokia, Xilinx, Blue-spec, and CEDA. To see a

description of the design problemand the contest rules, go to rijn-dael.ece.vt.edu/memocontest08. Formore information, please contactPatrick Schaumont [email protected]).

CEDA Honors Richard Brayton CEDA hosted a luncheon on 10June, 2008 at this year’s DAC tohonor Robert Brayton, winner ofthe 2007 Phil Kaufman Award, forhis impact on the field of electron-ic design through contributions inEDA. Brayton gave a lecture high-lighting his career path and chal-lenges, and shed light on some ofthe turning points he has wit-nessed while working in industryand academia. In addition to thislecture, EDA award recipients(IEEE Fellow, IEEE Technical FieldAwards, and others) were recog-nized for their accomplishments.

IEEE Annual Honors Ceremony The annual Honors Ceremony,considered to be the EEE’s most



prestigious event, recognizesexceptional contributions that havemade a lasting impact on technol-ogy, society, and the engineeringprofession. The program honorsachievements in industry, research,education, and service. Seventeeninstitute-level award recipientswere recognized at this year’s cer-emony, which was held on 20 Sep-tember, 2008 in conjunction withthe IEEE Sections Congress inQuebec, Canada.

This year’s IEEE Honors Ceremo-ny started at 6:00 pm, with a dinnerand afterglow reception immediatelyfollowing. The event was hosted by2008 IEEE President and CEO LewisTerman. The theme was “Innovatingto Meet the World’s Challenges.’’ Allthose attending the Sections Con-gress were invited. For further infor-mation, please see ‘Awards News’ onthe IEEE web site or contact WilliamJoyner ([email protected]).

Perspective: NoCs and EDA ToolsImprove MP SoC Designs Many multiprocessor SoCs (MPSoCs)are used in devices where low-energy operation of the system iscritical. As technology advances,wire scaling is not on par withtransistor scaling. Moreover, thenumber of communicating compo-nents in the chip, along with theirspeed of operation, is increasing.Because of these factors, the com-munication between the cores iscausing a major bottleneck forsystem performance and energyconsumption. With architecturesbecoming more interconnect-dom-inated, achieving an energy-effi-cient on-chip interconnect archi-tecture tailored to the needs of theapplications running on the chip isan important challenge thatdesigners face.

In recent years, researchers haveaddressed this challenge in twoways: by developing methods andCAD tools to achieve an energy-efficient design and by developingscalable micro network-based

architec-tures, or simply networkson chips (NoCs). CAD tools allowan exploration of the interconnectdesign space early in the designcycle and automate the building ofefficient application-specific inter-connect architectures. The NoCparadigm results in a structured,modular interconnect design withimproved performance and energyefficiency.

The main goal is to let designersexplore trade-offs in interconnectdesign—for example, betweenband-width, power, reliability, andcost. State-of-the-art methods existto solve some of the most impor-tant, time-intensive problemsencountered during interconnectdesign, such as interconnect topol-ogy synthesis, core mapping,crossbar sizing, route generation,resource reservation, and RTLcode and layout generation. Appli-cation-specific inter connect opti-mization can lead to significantimprovements in all relevant costmetrics. Improvements by factorsof 2 to 5 are not uncommon, andbecome even greater with technol-ogy and architectural complexityscaling. Design automation sup-port is essential to guarantee thatthese custom-fit solutions can bereadily deployed, tested, and veri-fied. Although the state of maturityof these tools is not perfect, resultsare promising, and automatedinterconnect design is poised tobecome an essential component inenergy-aware SoC design and vali-dation flows.

Direct any questions and com-ments about this report to SrinivasanMurali ([email protected]).

Upcoming CEDA Events IEEE CEDA currently sponsors orcosponsors ten conferences andworkshops, and two additional con-ferences in which it is in technicalcooperation with other societies.Our conferences provide excellentopportunities for those interested in

learning about the latest technicaltrends in electronic design andautomation and to being engagedwith a community of volunteers. Ifyou are interested in participating orhave an idea about new topics ofinterest for our conferences, pleasecontact William Joyner ([email protected]), CEDA vice president ofconferences.

3rd International Conference onNano-Networks (Nano-Net)15-17 September, 2008, Bostonwww.nanonets.org

18th International Workshop onPower and Timing Modeling Opti-mization and Simulation (PATMOS)10-12 September, 2008, Lisbon,Portugal www.fpl.uni-kl.de/con-ferences/patmos/patmos.html

16th IFIP/IEEE International Con-ference on Very Large Scale Inte-gration (VLSI-SOC)13-15 October, 2008, RhodesIsland, Greece//vlsi.ee.duth.gr/vlsisoc-2008

Embedded Systems Week(ESWEEK)19-24 October, 2008, Atlantawww.esweek.org

IEEE/ACM International Confer-ence on Computer-Aided Design(ICCAD)10-13 November, 2008, San Jose,Californiawww.iccad.com/2008/index.html

Formal Methods in ComputerAided Design (FMCAD)17-20 November, 2008, Portland,Oregon//es.fbk.eu/events/fmcad08

CEDA Currents is a publicationof the IEEE Council on ElectronicDesign Automation. Please sendcontributions to Jose Ayala ([email protected]) or Anand Raghu-nathan ([email protected]).

SSCS NEWS


445 Hoes Lane Piscataway, NJ 08854

SSCS SPONSORED MEETINGS2008 Asian Solid-State Circuits Conferencewww.a-sscc.org/3-5 November, 2008Fukuoka, JapanContact: Secretariat of A-SSCC2008E-mail: [email protected]

2009 ISSCC International Solid-StateCircuits Conferencewww.isscc.org8– 12 February 2009 San Francisco, CA, USAPaper deadline: 22 Sept. 2008Contact: Courtesy Associates,[email protected]

2009 Symposium on VLSI Circuits www.vlsisymposium.org16-18 June, 2009Paper deadline: 14 Jan 2009Contact: Phyllis Mahoney, [email protected]

2009 Organic Microelectronics Workshopwww.mrs.orgJuly 6-9, 2009 San Francisco, CA 94103Contact: Edwin A. Chandross,[email protected]

2009 Custom Integrated Circuits Conferencewww.ieee-cicc.org/20–22 September 2009San Jose, CA, USAPaper deadline: TBDContact: Ms. Melissa Widerkehr, Conference Manager [email protected]

SSCS PROVIDES TECHNICAL CO-SPONSORSHIP Sensors Conferencewww.ieee-sensors2008.org26-29 October 2008

Lecce, Puglia, ItalyPaper due date : PassedContact: [email protected]

2008 International Conference on Computer AidedDesign (ICCAD)www.iccad.com/9-13 November 2008San Jose, CAPaper due date : PassedContact: Kathy MacLennan, Conference [email protected]

Conference on VLSI Designvlsiconference.com/vlsi2009/5-9 January 2009New Delhi, IndiaPaper Deadline: Passed

IEEE International Conference on MicroelectronicTest Structureswww.see.ed.ac.uk/ICMTS/30 Mar – 2 Apr 2009Oxnard, CAPaper Deadline: PassedTechnical Chairman: Richard [email protected]

Design Automation and Test in Europe (DATE)2009www.date-conference.com/20-24 April 2009Paper Deadline: PassedNice, Alpes-Maritime, France

VLSI -TSA/DATvlsitsa.itri.org.tw/2009/General/27-30 April 2009Hsinchu, TaiwanPaper deadline: 18 Oct 2008VLSI-TSA Contact : Clara [email protected] Contact: Ms. Elodie HO [email protected]

2009 Radio Frequency Integrated CircuitsSymposiumwww.rfic2009.org/7-9 June 2009Boston, MAPaper deadline: 6 Jan 2009Contact: Larry Wicker, [email protected]

2009 Design Automation Conferencewww.dac.com27-31 July 2009San Francisco, CAPaper deadline: 19 Nov 2008Contact: Kevin Lepine, Conference [email protected]

Hot Chipswww.hotchips.orgAugust, 2009 Stanford, CA

ISLPED International Symposium on Low PowerElectronics and Designwww.islped.org/ 2009 Date TBD Contact: Diana Marculescu, [email protected]

2009 IEEE Integrated Circuit Ultra-Wide BandICUWBwww.icuwb2009.org9-11 Sep 2009Vancouver, CanadaPaper deadline: 23 Feb 2009Contact: Lutz Lampe, Chair, [email protected]

ESSCIRC/ESSDERC 2009- 39th European SolidState Circuits/Device Research Conferenceswww.esscirc2007.org 14 - 18 Sep 2009 Athens, GreeceAbstract deadline: 4 Apr 2009Contact Cor Claeys, IMEC, [email protected]

SSCS EVENTS CALENDARAlso posted on www.sscs.org/meetings

SSCS IEEE SOLID-STATE CIRCUITS SOCIETY NEWS is published quarterly by the Solid-State CircuitsSociety of The Institute of Electrical and Electronics Engineers, Inc. Headquarters: 3 Park Avenue, 17thFloor, New York, NY 10016-5997. $1 per member per year (included in society fee) for each member ofthe Solid-State Circuits Society. This newsletter is printed in the U.S.A and mailed Periodicals Postage Paidat New York, NY and at additional mailing offices.Postmaster: Send address changes to SSCS IEEE Solid-State Circuits Society News, IEEE, 445 Hoes Lane,Piscataway, NJ 08854. ©2008 IEEE. Permission to copy without fee all or part of any material without acopyright notice is granted provided that the copies are not made or distributed for direct commercialadvantage and the title of publication and its date appear on each copy. To copy material with a copy-right notice requires specific permission. Please direct all inquiries or requests to IEEE Copyrights Man-ager, IEEE Service Center, 445 Hoes Lane, Piscataway, NJ 08854. Tel: +1 732 562 3966.

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