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SSCSSSCSSSCSSSCSIEEE SOLID-STATE CIRCUITS SOCIETY NEWS

The Origins of the Integrated Circuit

Robert Noyce Jack Kilby

Spring 2007 Vol. 12, No. 2 www.ieee.org/sscs-news

sscs_NLspring07 4/9/07 9:51 AM

Welcome tothe Spring2007 issue

of the Solid-State Cir-cuits Society Newslet-ter! We appreciate allof your feedback on

our first two issues that present TheTechnical Impact of Moore's Law andThe Impact of Dennard’s ScalingTheory. Thank you for your supportof our efforts! Please refer to the twoLetters to the Editor in this issue forcomments from our readers. This

Spring 2007 issue is the second offour issues that SSCS plans to pub-lish annually (one each in Winter,Spring, Summer, and Fall).

The goal of each issue is to be aself-contained resource with back-ground articles (that is, the ‘originalsources’) with current articles byexperts who describe the currentstate of affairs in technology and theimpact of the original papers and/orpatents.

This issue contains two Highlightsarticles:

(1) “0-60 GHz in Four Years: 60GHz RF in Digital CMOS,” byAli Niknejad, Associate Profes-sor of Electrical Engineeringand Computer Sciences at theUniversity of California atBerkeley, CA.

(2) “Out of the Park Home Runs:Legendary Digital Circuits thatTracked Technology Scaling,”by Kerry Bernstein, SeniorTechnical Staff Member at IBMT. J. Watson Research Center inYorktown Heights, NY;

The theme of this issue is “TheOrigins of the Integrated Circuit.”Two feature articles discuss thistheme:(1) “The (Pre-) History of the Inte-

grated Circuit: A RandomWalk,” by Thomas Lee at Stan-ford University;

(2) “Crystal Fire: The Invention,Development, and Impact ofthe Transistor,” by Michael Rior-dan at the University of Califor-nia at Santa Cruz and LillianHoddeson at the University ofIllinois at Urbana-Champaign.

We reprint these original patentsin this issue:(1) W. Shockley, “Semiconductor

Amplifier Patent.” U. S. Patent2,502,488 (page 1 and first figure);

(2) J. Bardeen et al., “Three-Elec-trode Circuit Element UtilizingSemiconductive Materials,” U.S. Patent 2,524,035 (page 1 andFigs. 1, 1A, 2, 10, 11, 12);

(3) R. N. Noyce, “SemiconductorDevice-and-Lead Structure,” U.S. Patent 2,981,877;

(4) J. A. Hoerni, “Method of Manu-facturing Semiconductor Devices,’U. S. Patent 3,025,589 (page 1and Figures 1-10.

(5) J. S. Kilby, “Miniaturized Elec-tronic Circuits,” U. S. Patent3,138,743.

Thank you for taking the time toread the SSCS News. We appreciateall of your comments and feed-back! Please send comments [email protected].

2 IEEE SSCS NEWS Spring 2007

President:Richard C. JaegerAlabama Microelectronics CenterAuburn University, [email protected]: +1 334 844-1888

Vice President:Willy SansenK. U. LeuvenLeuven, Belgium

Secretary:David A. JohnsUniversity of TorontoToronto, Ontario, Canada

Treasurer:Rakesh KumarTechnology Connexions Poway, CA

Past President:Stephen H. LewisUniversity of CaliforniaDavis, CA

Other Representatives:Representative to Sensors Council

Darrin YoungRepresentative from CAS to SSCS

Domine LeenaertsRepresentative to CAS from SSCS

Un-Ku Moon

Newsletter Co-Editors:Mary Y. LanzerottiIBM T.J. Watson Research [email protected]: +1 914 945 1358

Lewis TermanIBM T. J. Watson Research Center [email protected]

Fax: +1 914 945-4160Elected AdCom Members at LargeTerms to 31 Dec. 07:

Bill BidermannDavid JohnsTerri FiezTakayasu SakuraiMehmet Soyuer

Terms to 31 Dec. 08:Wanda K. GassAli HajimiriPaul J. HurstAkira MatsuzawaIan Young

Terms to 31 Dec. 09:John J. CorcoranKevin KornegayHae-Seung (Harry) LeeThomas H. LeeJan Van der Spiegel

Region 8 Representative:Jan Sevenhans

Region 10 Representative:CK Wang

Chairs of Standing Committees:Awards David HodgesChapters Jan Van der SpiegelEducation CK Ken YangMeetings Bill BidermannMembership Bruce HechtNominations Stephen H. LewisPublications Bernhard Boser

For detailed contact information, see the Soci-ety e-News: www.ieee.org/portal/site/sscs

For questions regarding Society business, contact the SSCS Executive Office.

Contributions for the Summer 2007 issue of the Newsletter must be received by 8 May 2007 at the SSCS Executive Office. A complete media kit for advertisers isavailable at www.spectrum.ieee.org/mc_print. Scroll down to find SSCS.

Anne O’Neill, Executive Director IEEE SSCS445 Hoes LanePiscataway, NJ 08854Tel: +1 732 981 3400Fax: +1 732 981 3401Email: [email protected]

IEEE Solid-State Circuits Society AdCom

Editor’s Column

Katherine Olstein, SSCS Administrator IEEE SSCS445 Hoes Lane, Piscataway, NJ 08854 Tel: +1 732 981 3410 Fax: +1 732 981 3401Email: [email protected]


Spring 2007 IEEE SSCS NEWS 3

Photo of Robert N.Noyce (left) courtesy

of Intel.

Photo of Jack Kilbycourtesy of Texas

Instruments.Spring 2007 Volume 12, Number 2

Editor’s Column . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2

Letters to the Editor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4

Corrections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .74

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RESEARCH HIGHLIGHTS0-60 GHz in Four Years: 60 GHz RF in Digital CMOS . . . . . . . . . . . . . . . . . . . . .5“Out-of-the-Park Home Runs” Legendary Digital Circuits that Tracked Technology Scaling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11

TECHNICAL LITERATUREThe (Pre-) History of the Integrated Circuit: A Random Walk . . . . . . . . . . . .16Crystal Fire: The Invention, Development and Impact of the Transistor . . .24

PATENTSSemiconductor Amplifier (U.S. Patent No. 2,502,488) . . . . . . . . . . . . . . . . . . . . . . .30Three-Electrode Circuit Element Utilizing Semiconductive Materials(U. S. Patent No. 2,524,035) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32Semiconductor Device-and-Lead Structure (U. S. Patent No. 2,981 ,877) . . . . . . . .34Method of Manufacturing Semiconductor Devices (U. S. Patent No. 3,025,589) 41Miniaturized Electronic Circuits (U. S. Patent No. 3,138, 743) . . . . . . . . . . . . . . . . . .44

PEOPLEAsad Abidi, Mark Horowitz and Teresa Meng Elected to U. S. National Academy of Engineering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .55Yannis P. Tsividis and Hugo De Man Receive IEEE Field Awards at ISSCC . . . . . . . . .56SSCS Nominees Recognized at ISSCC Plenary for Elevation to Fellow . . . . . . . . .57Huijsing, Makinwa, and Pertijs Receive JSSC 2005 Best Paper Award . . . . . . . . . .60Best Student Design Awards Presented at ISSCC 2007 . . . . . . . . . . . . . . . . . . . . . .62Lanzerotti Honored by IEEE Women in Engineering Society of New York . . . . . . . .64New Senior Members . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .64Tools: How to Write Readable Reports and Winning Proposals . . . . . . . . . . . . . . .65

CHAPTER NEWSNew SSCS Chapters in Tainan and South Brazil . . . . . . . . . . . . . . . . . . . . . . . . . . .66A Chapter is Born in Southern Taiwan . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .67

CONFERENCESClassic Books Remain Best Sellers at ISSCC 2007 . . . . . . . . . . . . . . . . . . . . .69Digital and Analog Designers Spar at ISSCC Evening Panel Session . . . . . . .71VLSI Circuits Symposium Celebrates 20th Anniversary in June . . . . . . . . . . .72Persico and Streit to Speak at RFIC Symposium in Honolulu . . . . . . . . . . . .75

NEWSIEEE ABET Accreditation Criteria and Procedures in Spanish . . . . . . . . . . . . . . . .10IEEE History Center Adds 75 Oral Histories to Web Site . . . . . . . . . . . . . . . . . . . . . .16IEEE Expert Now Courses Available to Members Through IEEE Xplore . . . . . . . . .29CEDA Currents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .76IEEE SSCS Focuses on Strategic Planning in 2007 . . . . . . . . . . . . . . . . . . . . . . . . . .77Call for Nominees for SSCS Administrative Committee Election . . . . . . . . . . . . . .79IEEE Partners with Knowledge Master, Inc. to Offer Microelectronics in Mandarin Chinese . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .80Call for Nominations: SSCS Predoctoral Fellowships 2007-2008 . . . . . . . . . . . . . . .81Presubmission Professional Editing Services for IEEE Authors . . . . . . . . . . . . . . . . .82

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Letters to the EditorDear Mary Lanzerotti and Lew Terman,

I got copies of the SSCS newsletter (the first two full colorprinted versions of SSCS newsletter: Vol. 20 (3), Sept 2006and Vol. 21 (1), Winter 2007) from the 2007 ISSCC confer-ence site in San Francisco. When I returned to my office, theWinter 2007 issue was also waiting for me on my office desk.I read both of these two full color issues. I really enjoyed myreading. I have to say this is the best newsletter in many pro-fessional societies I have ever read! Congratulations! Maryand Lew, you really did a great job for members of SSCS. Iread most of the articles and news for many hours duringmy whole holiday period of Chinese Lunar New Year.

I have found some mistakes in the newsletter, whichI would like to feed back to you for your information:

[1] On the cover and page 3, the winter issue of 2007should be Vol. 21 instead of Vol. 12? Since the Sept2006 issue is Vol. 20.

Editor’s Note: The September 2006 issue should havebeen Vol. 11.

[2] In the Editor's Column of both issues, Mary told usthat the newsletter will be issued 4 times per yearfor the first time in 2007, but in the back cover,there is a pink block, in there it is still said thenewsletter is published 3 times per year. I thinkstarting from this first issue, this should be updat-ed as Editor’s Column claimed.

Editor’s Note: The back cover has been corrected toreflect our quarterly schedule.

Thank you again for such a nice magazine, I amlooking forward to enjoying more in the future.

Best Regards,C. Y. Lu

Ph. D., IEEE Fellow, APS FellowChairman & CEO, Ardentec Corporation,

HsinChu, Taiwan, ROCSenior VP and CTO, Macronix International Co.,

Ltd, HsinChu Science Park, HsinChu, Taiwan, [email protected]

Dear Ms. Lanzerotti, I was fascinated by the photomicrograph of the first

monolithic (one rock) integrated circuit produced byFairchild Semiconductor, which I date to about October-November 1959 Winter; 2007 issue, p. 10. This was the “F”element, a Set-Reset Flip-Flop. The connection padsshown, clockwise from the top were: Ground, Set, F’,+Supply, F, and Reset. The load resistors are the dark stripeacross from F’ to +Supply to F. Not visible were the seriesresistors to the base of each transistor to reduce the “cur-rent hogging” that was a problem with DCTL configura-tions. The planar technology invented by Jean Hoerni*,had three important attributes:

The Collector-Base Junction was formed under the

oxide surface of the wafer resulting in a substantialimprovement in transistor reliability and manufacturability.

Of particular interest to Bob Noyce*, the oxide sur-face could be used for depositing circuit interconnects.

The resulting semiconductor junctions were “pure”resulting in a remarkable conformity to the then recent-ly described Ebers and Moll model.

The measurements by Don Farina on the small geom-etry 2N1210 planar transistor over several decades ofCollector current showed conformity to the Ebers andMoll model even though its low Inverse Alpha was notconsidered suitable in their original paper. Importantly,the consistency of these transistors with this modelmade it possible to use mathematical expansion of theEbers and Moll model to design the circuitry of this firstcompatible family of monolithic logic circuits.

It is worth noting that the required Fan-In/Fan-Outparameters had already been established in the devel-opment of several military digital computers at SperryGyroscope Company.

The photomicrograph shows the first pass at isolatingthe various circuit components, another important require-ment for the successful development of monolithic inte-grated circuits. This approach was to etch apart semicon-ductor islands supported by the surface oxide then backfilling with plastic. It became immediately obvious that thistechnique would not meet the -55 to + 125 degrees, Centi-grade military temperature requirements or thermal cycling.As shown the chips were chemically etched apart whichcarried the evident manufacturing problems. Meanwhile,Jean Hoerni developed diffused isolation which becamethe production method. While the long backside diffusionmade the silicon wafers more brittle, leading to easy break-age in manufacturing, the Integrated Circuits were manu-factured as multiple instances on silicon wafers which werescribed and broken into chips in much the same fashion asindividual transistors were batch fabricated.

At about this time an IBM paper was published in the“Proceedings of the IRE” on “Test to Failure”. Vic Grinich*,V. P. Engineering, endorsed subjecting the Micrologic Inte-grated Circuits to a similar “test to failure” reliability regi-men. While all of the prior work on military computersnoted above included transistor qualification tests and lifetests by the Sperry Gyroscope Standards Laboratory, andtemperature and voltage margin tests, all were by and large“ad hoc”. Using TO-5 cans made it possible to use the man-ufacturing expertise already developed for transistors. Fol-lowing the lead of the “Test to Failure” paper we were ableto quickly and convincingly arrive at mechanical, thermal,and electrical screens which assured the quality of the man-ufacturing process and the products, with two exceptions:

The detergent bomb used in the gross leak test couldnot be used since the circuit resistances were low andtherefore a device could pass with a small amount ofdetergent in the TO-5 can which in turn could damage

continued on page 10

*Founders of Fairchild Semiconductor, Division ofFairchild Camera and Instrument Co.



RESEARCH HIGHLIGHTS

CMOS transistors are getting smaller and cheaper,and we have witnessed a revolution in computa-tion, signal processing, and communication

using this wonderful technology. As transistors havegotten smaller, they have also gotten incredibly fast.Our mission at the Berkeley Wireless Research Center(BWRC) was to tap into this speed to realize the fastestpossible communication circuits operating in the 60GHz band.

Silicon-based circuits operating at 60 GHz, especial-ly in CMOS technology, represented a huge leap in theoperating frequency of silicon technology. At the time,in early 2001, most researchers were focusing on thespectrum from 1-5 GHz, with a few isolated researchgroups pushing circuits up to 24 GHz. Our suggestionto exploit 60 GHz with CMOS even seemed comic tosome observers. Fortunately DARPA funded this earlystage research project under the umbrella of the TEAMprogram (Technology for Efficient, Agile Mixed-SignalMicrosystems), a program that supported a broadrange of research to advance silicon technology intothe mm-wave spectrum. Many of our industrial part-ners at BWRC also thought this was a worthy effort,something that would be relevant to industry in 5-10years. Our original plan was to take three steps to 60GHz, starting at 20 GHz in 180nm CMOS, 40 GHz in130nm CMOS, and finally 60 GHz in 90nm CMOS.Midway through our effort we decided to leapfrog to60 GHz directly using 130nm technology. This articlechronicles our efforts—and the challenges involved—to reach 60 GHz.

Why 60 GHz?Given the many challenges to working in this fre-quency, what are the benefits? The availability of alarge block of a nearly universal unlicensed spectrumin this frequency band is an obvious motivation, with7 GHz available in the U.S. and at least 3-4 GHz in theintersection of the set of all international standards.High bandwidth translates into high throughput, eas-ily supporting Gb/s data wireless communication datarates with low complexity modulation schemes. Thereis a plethora of applications crying out for high band-width, especially in the domain of personal area net-works (PANs). Data transfer from high resolution dig-ital cameras, transfer of music and video and othermultimedia content between a computer and aportable device, such as the ubiquitous iPod, aresome obvious examples. Other emerging applicationsinclude transmission of uncompressed video betweena multimedia device and an HD flat screen television

or projector. Taking the signals a bit further, we see aWLAN counterpart to gigabit Ethernet. If we can goup to 77 GHz, then there are applications in automo-tive radar for collision detection and automatic speedcontrol and mm-wave imaging for security.

Shannon’s theorem tells us that channel capacity isproportional to bandwidth and a logarithmic functionof SNR. On the bandwidth front we have a big advan-tage over low GHz communication standards. Thisallows us to utilize relatively inefficient modulationschemes and still realize large data rates, a tradeoff wecan make in the complexity of the baseband architec-ture. High data rates with smaller bandwidths (e.g.WLAN at 2.4 GHz), requires complex modulationschemes to squeeze as many bits/Hz as possible.

There is also 7 GHz of untapped bandwidth in theUWB spectrum from 3-10 GHz. In contrast to the 60GHz band, in UWB systems the FCC regulations limitthe transmit power to an average of about 0 dBm.There is also a great amount of complexity in a UWBradio, either in the form of FFTs in an OFDMapproach, or in the form of long correlators to “picka needle out of a haystack,” or to find a weak signalin a sea of noise and interference. In contrast, in theU.S. the maximum power transmission in the 60 GHzband is 40 dBm, or four orders of magnitude higherthan UWB. Power and bandwidth are good motiva-tors for a communication system.

Fear of 60 GHzWith these motivations, we had to overcome someconsternation with 60 GHz. We were inundated withquestions and doubts about mm-wave circuits in sili-con and wireless propagation in this frequency band.In fact, we were certainly not the first to try to buildmm-wave circuits and systems. The Japanese wereearly innovators in this field and demonstrated workingtransceivers in III-V technologies [1]. Many of the ques-tions about the validity of lumped circuit theory at mm-wave frequencies are easily answered if you realizethat CMOS transistors are still a tiny fraction of thewavelength, and can be treated as lumped circuits. Theinterconnect and matching circuits must be treated asdistributed circuits, but this is a problem that wassolved decades ago by microwave engineers. Theimportant question is whether the conductive siliconsubstrate will in some way be a big deterrent to realiz-ing circuits at 60 GHz. We shall show in this article thatthis is not the case and in fact very good active andpassive devices have been demonstrated by BWRC andother groups working on silicon mm-wave circuits.

0-60 GHz in Four Years: 60 GHz RF in Digital CMOSAli M. Niknejad, Electrical Engineering and Computer Science Department, University of Califor-nia, Berkeley, CA, [email protected]



Signal propagation at 60 GHz has a higher pathloss, and waves experience higher attenuation whentraveling through materials in the mm-wave band. Inparticular, the oxygen absorption spectrum occursprecisely in this frequency range, one of the reasonsthis band is relatively unused for long-range commu-nication. Furthermore, given the low supply voltagesof nanoscale CMOS (and the relatively high noise fig-ure), we don’t expect to be able to transmit inordinatepower levels to overcome the path loss at 60 GHz. Sowe turn to another strength of CMOS, and that is thecapability to integrate a large number of transceiverson a die. A phased antenna array can overcome thelimitations of CMOS by improving the antenna gain,and hence effective radiated power. Antenna ele-ments are small in the mm-wave spectrum and can beintegrated into the package. This in turn allows beamforming, which improves the antenna gain andincreases spatial diversity. A side benefit is resilienceto multi-path fading and interference. Finally, andmost importantly, an antenna array allows spatialpower combining, which simplifies the design of thePA considerably. The vision for our system is capturedin Fig. 1, which shows several transceivers incorpo-rating electronic phase shifters to form a smart anten-na array.

The Phased “Smart” Antenna ArrayThe antenna array solves the fundamental problemwith higher frequency operation: path loss. Friis’sequation tells us that the path loss drops with smallerwavelengths (1/λ2). For instance, if we employ a sim-ple dipole antenna with modest gain, the antennacapture area is proportional to the wavelengthsquared (λ2), and so we capture a smaller fraction ofthe radiated power P which is divided over a sphereof surface area 4πR2, resulting in a (λ/R)2 term in theequation. This loss, though, can be overcome byemploying a larger area, such as a dish antenna, at thecost of directionality. The antenna gain is in fact tofirst order inversely proportional to the solid anglebeam width. For a mobile system we need a way ofmoving the antenna beam dynamically, and this iseasily done in an antenna array by employing phaseshifters in the transmitter and receiver, which intro-

duce just enough delay (2πdcosθ/λ) in each element(spacing d) so that signals arriving at some angle doso perfectly in phase. At the receivers the signals aresummed together to improve the SNR of the receiver,and in the transmitter the signals sum to increase theradiated power. Another benefit to a directionalantenna in the receiver is that it reduces multipathpropagation since signals arriving through paths otherthan the LOS path arrive from different directions, andthus are potentially attenuated by the nulls in theantenna pattern. This simplifies the baseband of thetransceiver, allowing simpler equalization and lowerresolution ADCs to be employed. For the transmitterthe design of the power amplifier is simplified con-siderably. Not only is the total power divided by thenumber of elements, but the increased antenna gainallows one to even drop the transmit power morethan 1/N. To replace an isotropic transmitter with 100mW with an array of 10 elements, we can transmitpower levels of a few mW per element and utilize theantenna gain and spatial power combining to realizean effective power of 100 mW transmitted in a givendirection.

Devices and ModelingOne of the biggest challenges in moving from lowGHz frequencies to the mm-wave band is the lack ofinfrastructure, CAD tools, and models. Measurementequipment requires a large investment of capital,training, and finesse in making precise and accuratemeasurements. Noise measurements are particularlydifficult at these frequencies, with a handful of groupsaround the world that have expertise at noise meas-urements beyond 26 GHz. We upgraded our meas-urement facilities at BWRC to support small-signal,large-signal, and noise circuit measurements up to 65GHz and then again up to 110 GHz. We have charac-terized process nodes starting at 180nm down to90nm through extensive test chips with building blockdevices such as MOS transistors, transmission lines,custom MIM capacitors, resistors, MOS capacitors, res-onators, and inductors. By characterizing thesedevices, we were able to build a library of active andpassive devices for mm-wave design.

Characterization of transmission lines with differentgap spacing allowed us to characterize the high fre-quency losses in the Si substrate and dielectric layersto allow new structures to be simulated with a full-wave electromagnetic simulator. Transmission linesare characterized by their characteristic impedance Z0and the complex frequency dependent propagationconstant y (w). We make extensive use of transmis-sion lines—as opposed to spiral inductors—since theyare length scalable, allowing us to precisely designsmall reactance values to form matching circuits at 60GHz. Inductors are more difficult to simulate, espe-

RESEARCH HIGHLIGHTS

Fig. 1.



cially since the lead inductance can become a sub-stantial fraction of the circuitry. Moreover, transmis-sion lines have well controlled field patterns with anearby ground return path, which limits the amountof substrate coupling. Short sections of co-planar trans-mission lines act as inductors with Qs approaching 30at 60 GHz, allowing high Q resonators. Varactors,though, have small Q, making large tuning resonatorsparticularly challenging at mm-wave frequencies.

A typical transistor measurement is shown in Fig. 2,where we plot the simulated and measured currentgain (H21), maximum stable gain (MSG), and unilater-al gain (U) of the device.

Microwave devices are characterized by their Fmax,as opposed to the Ft, since the device Ft is independ-ent of layout and does not include the influence ofdevice losses. The Fmax, on the other hand, definesthe maximum frequency of activity, setting the limiton the highest frequency that we can extract powergain from the device. This means that amplifiers andoscillators can only be realized below the device Fmax.The device Fmax can be shown to rely on device par-asitics through the following relation

Fmax ≈ Ft

2√

R g (gmC g d /C g g ) + (R g + rch + Rs)gd s

which shows that the device performance increas-es proportional to Ft, but also depends strongly on thegate, source, and channel resistance of the device.The role of the layout parasitics is quite dramatic, withFmax ranging from 0.5 Ft to nearly 2 Ft when the gatefingers range from 8µm to 1µm. An optimized deviceis biased in strong inversion with short gate fingers.The modeled results show an excellent match tomeasurements, especially in the match of U, Mason’sUnilateral Gain, which is a strong function of deviceparasitics. Since the device is only conditionally stableat 60 GHz, its maximum stable gain is not a strongfunction of the device loss, since the loss is absorbed

into a larger external stabilizing termination (until thestability factor K=1). On the other hand, if we stabi-lize the device through feedback, then the gainincreases to a limit given by Mason’s Unilateral Gain.Incidentally, the noisiness of the U data is also a goodindicator of the quality of the measurements, sinceany small error in the measurement of device losstranslates into a large variation of U. Conventionally,the Fmax of the device is extrapolated from the valueof U = 1 from low frequency data. The measurementsshow that this is a reasonable way to extract thedevice Fmax beyond the measurement capability, but abetter approach is to model the device up to high fre-quencies and use a model extrapolated value.

The device is modeled with an extended BSIM3model which incorporates gate/drain/source induc-tance and loss and a custom substrate resistance net-work (Fig. 3).

This model is first fitted to DC curves in the biasregions of interest, from weak inversion to stronginversion, with particular emphasis on fitting thedevice transconductance. Next the device parasiticsare varied to fit the measured S-parameters up to 65GHz. This modeling approach is verified with large-signal measurements of device output power versusVgs and harmonic power measurements. A further val-idation of the model comes from the measurement ofnon-linear circuits such as mixers and amplifier com-pression point. The noise of the devices is modeledusing Pospieszalski’s noise model [2], with a short-channel excess noise factor y = 1.4. This model is ableto predict the trends of NFmin, Rn, and Yopt over biasand device geometry reasonably well. The measuredFmin for a 130nm is 4 dB at 65 GHz, which means thatmoderately low noise amplifiers are possible.

Circuits and Building BlocksGiven a good library of active and passive devices,the actual circuit design is relatively simple. Transmis-

RESEARCH HIGHLIGHTS

Fig. 2.

Fig. 3.



sion lines are used extensively for matching, bias, andinterconnect. Bypass and AC coupling capacitors areused to bias and de-couple the amplifier stages. Athree-stage amplifier incorporating unconditionallystable cascode stages was designed, fabricated andmeasured. This amplifier, the world’s first 60 GHzCMOS amplifier, was reported at ISSCC in 2004 [3].The amplifier had a measured gain of 11.5 dB, a NFof 9 dB, and an output compression point of +2 dBm.

A quadrature balanced mixer was designed to con-vert a 60 GHz RF to a 2 GHz IF signal. The mixerschematic and layout, shown in Fig. 4-5, utilizes aquadrature coupler to combine the RF and LO signals,with the LO (0dBm) signal modulating the transistoroperating point to realize the -2 dB down-conversiongain in the 60 GHz band.

This mixer and LNA were combined together withother building blocks, including the VCO, LO buffer,and frequency doubler, to realize a highly integrated

60 GHz receiver front-end in a digital CMOS 130nmprocess [4]. The chip micrograph is shown in Fig. 6,which occupies an area of 3.3 mm x 1.7 mm, con-sumes 77 mW of power, has 12 dB of RF conversiongain, a NF of 10.4 dB.

The free running VCO has a phase noise of -93dBc/Hz at a 1 MHz offset. Even at this early stage,assuming modest transmit power of 6 dBm per ele-ment in a 12-fold array, the receiver can support 1Gb/s data rate communication over a LOS 10m range,with 26 dB SNR at the receiver. This leaves quite a bitof margin since 10-3 BER communication is feasiblewith 10 dB SNR, but in a real system many othersources of loss need to be accounted for.

Future of CMOSThe future of CMOS is bright, so put on your shades.We are now actively pursuing 90nm CMOS for 60GHz applications and we have already demonstrateda new device layout which achieves an extrapolatedFmax of 300 GHz, three times the device Ft. With moregain at 60 GHz, we can back off and consume lesspower in the amplifiers. Oscillators and frequencydividers are also less power hungry, allowing one tolower the overall power consumption. We havealready demonstrated the world’s fastest CMOS ampli-fier, running at 104 GHz [5]. As the operating fre-quency increases, we envision new applications, with300 GHz “THz” spectrum within the grasp of CMOS ina few generations of technology scaling. New emerg-ing applications include imaging for radar, security,and medical systems. In a security application, due tothe relatively small wavelength, mm-waves providemedium resolution imaging which can penetratethrough clothes and display potentially hiddenweapons, even non-metallic objects. In medical appli-cations mm-waves can penetrate the skin and beincorporated into a low resolution CAT scan. Theadvantage over an X-ray system is the low non-ioniz-ing photon energy level, which makes these testsmuch safer.

Conclusion CMOS technology continues to amaze us, with scalingpushing the operating frequency up to 100 GHz with

RESEARCH HIGHLIGHTS

Fig. 4.

Fig. 5.

Fig. 6.



standard digital transistors. Successful circuit designrequires a combination of careful measurements andcompact modeling of active and passive devices.Using relatively simple lumped circuit compact mod-els of transistors and electrical models of transmissionlines, communication building blocks such as ampli-fiers, mixers, and oscillators have been demonstratedin CMOS technology operating in the mm-wave band.With further technology scaling, the performance ofthese building blocks will continue to improve and thepower consumption will continue to drop, enabling ahost of new communication and imaging applicationsto be realized with inexpensive CMOS technology.

AcknowledgementsThis research was done in collaboration with the fac-ulty of The Berkeley Wireless Research Center(BWRC) , including Robert Brodersen. Moreover, twogenerations of talented graduated students have con-tributed tremendously to the research, includingChinh Doan, Sohrab Emami, Mounir Bohsali, BabakHeydari, Ehsan Adabi, Bagher Afshar, and DavidSobel. This research would not have been possiblewithout the funding from the DARPA TEAM projectand BWRC member companies. [1] K. Ohata, K. Maruhashi, M. Ito, S. Kishimoto, K.

Ikuina, T. Hashiguchi, N. Takahashi, S. Iwanaga,“Wireless 1.25Gb/s transceiver module at 60GHzBand,” ISSCC 2002, p. 298-299, 467.

[2] M. W. Pospieszalski, “On the measurement ofnoise parameters of microwave two-ports,” IEEEMTT-S IMS Digest, pp. 456-458, April 1986.

[3] C.H. Doan, S. Emami, A.M. Niknejad, R.W.Brodersen, “Design of CMOS for 60GHz applica-tions,” ISSCC 2004, pp. 440-538.

[4] H. Doan, S. Emami, A.M. Niknejad, R.W. Broder-sen, “A 60GHz CMOS Front-End Receiver,” ISSCC2007, pp. 190-191.

[5] B. Heydari, M. Bohsali, E. Adabi, A.M. Niknejad,“Low-Power mm-Wave Components up to

104GHz in 90nm CMOS,” ISSCC 2007, pp.200-201,597.

About the AuthorAli M. Niknejad received the B.S.E.E.degree from the University of California,Los Angeles, in 1994, and the M.S. andPh.D. degrees in electrical engineeringfrom the University of California, Berkeley,in 1997 and 2000. From 2000-2002 heworked at Silicon Laboratories in Austin,

TX, where he was involved with the design and researchof CMOS RF integrated circuits and devices for wirelesscommunication applications. Presently he is an associ-ate professor in the EECS department at UC Berkeley.He is a co-director of the Berkeley Wireless ResearchCenter (BWRC) and also the co-director of the BSIMResearch Group. He served as an associate editor ofthe IEEE Journal of Solid-State Circuits and is current-ly serving on the TPC for CICC and ISSCC. His currentresearch interests lie within the area of analog inte-grated circuits, particularly as applied to wireless andbroadband communication circuits. His interests alsoinclude device modeling and numerical techniques inelectromagnetics.

See it on web TV.Excerpts from Ali Niknejad’s CICC presentation on 60GHzchips developed by the Berkeley Wireless Research Cen-ter can be watched on IEEE.tv using your IEEE webaccount. From this URL www.ieee.org/web/member-ship/IEEEtv/about.htmlselect launch IEEE.tv from the right. The broadcastappliance will request your IEEE web account.After logging in select the program under CONFER-ENCE HIGHLIGHTS, Custom Integrated CircuitsConference.

RESEARCH HIGHLIGHTS


10 IEEE SSCS NEWSLETTER Spring 2007

the aluminum interconnects. (We changed to a differenttype of gross leak test.)

Scratches of the aluminum interconnects made dur-ing the assembly process adversely impacted reliability.The only screen we could find was to optically inspectthe assembled devices. We later developed a glass coat-ing to protect these interconnects.

The test-to-failure lessons immediately fed back totransistor production. (The information from this testingmade it possible to deliver transistors to NASA AmesLaboratory to be used in telemetry from projectileswhich were literally shot from guns into a supersonicwind tunnel to examine the effects of hypersonic flight.)

As happens so often in the semiconductor industry,the incredible teamwork of Jay Last*, Jean Hoerni*, JimNall and Isy Haas, under Gordon Moore*, and myself,Don Farina, Helmut Wolf and later Al Wesolowski,Orville Baker, Dick Anderson, and Howard Bogertunder Vic Grinich*, led and inspired by Bob Noyce,resulted in the first successful manufacture of Microlog-ic prior to its introduction at the February, 1960 ISSCC.

P. S. I don’t recall Gordon saying complexity woulddouble every two years. Recall that in the original paper,Gordon’s curve rounded off because he could not con-ceive any use for such massively complex chips. In fact,this was the subject of an Asilomar Conference shortlyafterwards. Gordon had made the statement that while the

technology would support a million transistors on a chipthere was some question about the usefulness of suchcomplexity. Among other things it was pointed out at thatconference that a single chip Doppler radar processorwould require 25 million gates. We should recall that Gor-don’s more recent comments are in the context of massivefinancial investments in the manufacture and distributionof what amounts to a single “legacy” architecture. This hasbeen accompanied by comparable investments by othersto develop robust applications software to run on thisarchitecture. With 20/20 hindsight one might argue wewould have been better off starting with a multi-processorarchitecture, but that ship has sailed. There is plenty ofroom to develop and use a lower power per gate imple-mentation and exploit distributed processor architectures,but not at the low unit cost of the legacy X86. That shiphas sailed. On the other hand, all the work that Gordonand others have done opens the way for a variety ofprocessor architectures and programming paradigms,including self-organizing networks. There are, at the min-imum end, fabrication resources such as MOSIS, whichsupport work on new circuits, structures, and architec-tures, again at higher unit cost.

P. P. S. Thank you for the work you are doing on thispublication.

Robert H. Norman PO Box 1301

West Chatham, MA 02669 [email protected]

February 21, 2007

Letters to the Editor continued from page 4

ABET Accreditation Criteria and Procedures NowAvailable in Spanish

The IEEE recently teamed with ABET, Inc., the rec-ognized accreditor for college and university pro-grams in applied science, computing, engineering,

and technology, to provide 2006-2007 accreditation cri-teria and procedures in Spanish. The translated docu-ments are now available online. ABET, Inc. is a federationof 28 professional and technical societies.

IEEE commissioned the translations, oversaw thework and collaborated on the project with the Institutode la Calidad en la Acreditacion de Carreras de Inge-nieria y Tecnolgogia (ICACIT), a university-level Peru-vian accrediting body in the process of being established

and chartered. IEEE will have the translated documentsupdated when ABET updates the originals to ensure themost current information is available to individualsworking on accreditation in Central and South America.

The translated ABET criteria and procedures wereused during a 2006 IEEE workshop held for educatorsand practitioners on education in Lima, Peru.

The project was supported by the Educational Activ-ities Board and the IEEE Peru Section. For access to thetranslated documents, visit dfl.ece.drexel.edu/icacit/index.php?PAGE=DOCUMENTS, or for more informa-tion on ICACIT visit dfl.ece.drexel.edu/icacit/.

*Founders of Fairchild Semiconductor, Division ofFairchild Camera and Instrument Co.


Spring 2007 IEEE SSCS NEWSLETTER 11

Few people will argue that we enjoy today anabundance of electronic capability enabled bysuccessive generations of technology scaling.

Transistor device technologies have evolved in materialand structure to circumvent limitations arising frompower consumption, variability, and fundamentally,atomistic-level physics. What has been less apparenthowever is the circuit design response to these devicechanges. Each of the major “home runs” in high per-formance Field Effect Transistor technology (PMOS,NMOS, CMOS, and SOI) has ushered in with it novelcircuit topologies and changes in the way logic func-tions are realized. Further, as whole new applications(such as low power, handheld portable devices)became enabled by improving transistor devices, entire-ly new circuits had to also be developed. Much is writ-ten about transistor scaling; this article will provide aglimpse at what’s happened over the years in circuitdesign, “the other dugout”. Let’s look at some majorleague digital circuit styles which have quietly trackedscaling.

NMOSThe PMOS technology used in the world’s first DRAMchip, the 1K Intel 1103 in 1972, was among the firstmarketed MOSFET applications. It was NMOS tech-nology, however, that began the era of high perform-ance MOSFET-based logic, seeing popular usage inthe 70s and 80s in applications like the HP 9800series, the first truly modern consumer desktop calcu-lators. NMOS provided the designer the use of“enhancement-mode” (positive Vt) and “depletion-mode” (negative Vt) FETs. They were of commonpolarity, i.e. the drain-to-source current in bothincreased monotonically as gate voltage increased.

The depletion-mode devicewas used predominantly asa current source load withits gate tied to its source.Enhancement devices pro-vided the switchable pathto ground. The on-currentcapability of the loaddevice to the switching FETwas selected so that theenhancement-mode devicecould sink the loaddevice’s current wellenough to produce anacceptably low output volt-age (low Vout), recogniza-ble as a “Logical 0” by thenext stage. The circuit dis-sipates static power only inthe low Vout state. Howev-er, the load current was the source of charge availableto pull up the output capacitance to the high “Logi-cal 1” Vout level when the enhancement device wasswitched off. Therein lies the rub with NMOS: largerdepletion devices increased the load current avail-able to the output which sped up the rising transi-tions, but at the cost of increased static power in theON state power. This reduced NMOS’ power advan-tage over its bipolar transistor predecessor. TheNMOS realization of the common NAND2 is shownin Figure 1.

The more complex “Push-pull” or clocked logic cir-cuits (see below) turn off the load current when thepath to Ground is on, eliminating the static power.

Sizing a depletion-mode load device large enough

RESEARCH HIGHLIGHTS

“Out-of-the-Park Home Runs” Legendary Digital Circuits that Tracked TechnologyScalingKerry Bernstein, Senior Technical Staff Member, IBM T. J. Watson Research Center,Yorktown Heights, NY, [email protected]

Table 1 Circuit topologies reviewed in this article

Fig. 1 NMOS NAND2


12 IEEE SSCS NEWSLETTER Spring 2007

to quickly drive large loads such as word lines wouldhave presented prohibitive power consumption whencoupled to Ground. Alternately, using an enhance-ment-mode load device, which could be turned off tosave power would’ve reduced the output voltage byone threshold (“VTE”), and so was equally unaccept-able. “Bootstrapping” avoided the one-VTE -drop inoutput voltage occurring when an output is driventhrough an enhancement-mode device with a positiveVTE [Hardee81]. A precharged inversion-layer-capac-itor, inserted between gate and drain of the givendrive device, (Figure 2) elevated the drive device’sdrain to a voltage in excess of VDD+VTE as the drive-device’s gate was driven high.

As the device turned on, it passed the now-boost-ed signal to the output node, reduced by VTE. Sincebootstrapping elevated the drain of the enhancement-mode drive device above VDD by at least VTE, theresulting output still achieved a full “high” level. Anisolation device above the drive device prevented thebootstrapped drive device drain from discharging upinto the lower voltage supply, by reverse-biasing asbootstrapping occurred.

Depletion load devices were later clocked in anattempt to eliminate static power.

Eventually, in NMOS logic circuits, this “Push-Pull”circuit style became the preferred approach to man-age power [Streetman80]. The next improvement,however, would come from the ability to gate indi-vidual loads completely on or off to save power.

CMOSThe advent of CMOS finally provided designers withFET devices of complementary polarities, allowing thesame transient input to simultaneously turn on thepull-up transistors and turn off the pull down transis-tors (or vice-versa), instantly eliminating static powerand the power-delay trade-off of the NMOS circuits.The fundamental power consumption is the CV2fdynamic switching power. The circuit has no staticcurrent or power because of the infinite resistance ofthe MOSFET gate (in contrast to the base current of

bipolar logic circuits), and because either NFET orPFET devices are turned off for a given input logiclevel; the only static current is leakage (which hasbecome an increasing problem as devices are scaled).Although logic circuits built with CMOS devices werefirst described in 1963 by Wanlass [Wanlass63] (seeFigure 3), it was not until the late 80’s that CMOSbecame VLSI’s “designated hitter”.

Initially, CMOS chips comprised static combinatori-al CMOS logic circuits. Soon, pinch-hitters such ascascode voltage switching, pass gates / transmissiongates, and dynamic logic circuits began appearing.

Static Combinatorial CMOS LogicBecause static combinatorial CMOS circuits are quitenoise-immune, easy to design, reliable, relatively lowpower, and fully testable, unclocked static logic will con-tinue to be a mainstay of microprocessors. Many superbtextbooks provide insight into circuit design using thismodern fundamental circuit family [e.g., Chandrakasan01].Static CMOS circuits are given to formulaic design, allow-ing designers understanding only cursory device physicsto produce robust circuits. Ivan Sutherland described a“cookbook” approach to setting CMOS device dimensionswhich he called “Logical Effort”, or “design on the back ofan envelope”. A popular paperback later written bySutherland, Sproull, and Harris has made this approach anengineering curriculum standard [Sutherland99].

A downside of static CMOS is that the pull-up struc-tures use the lower-transconductance PFET, requiringlarger devices and costing area and power from theincreased gate size and capacitance. Idiosyncraticpower is also lost to short-circuit (or “crowbar”) currentflowing from Vdd to Ground during the switch intervalwhen both PFET and NFET devices are on [Hirata96].Alternative circuit styles addressed improved powerand/or delay, as we’ll see in a minute.

Ironically, in logically wide NORs, high resistanceresulting from stacking multiple PFETs in series forthe pull-up function (i.e. the 3 series PFETs in Figure3) is sometimes circumvented by substituting a solePFET. The gate of this device is then tied to ground inan arrangement called “Pseudo-NMOS” [Subba00], a

RESEARCH HIGHLIGHTS

Fig. 2 NMOS Bootstrap Circuit

Fig. 3. NOR3, the First CMOS Circuit Description, from the1963 ISSCC Digest


Spring 2007 IEEE SSCS NEWSLETTER 13

throw-back to the use of a depletion load device in“ratioed circuits” from the old NMOS days.

Cascode Voltage SwitchingDifferential Cascode Voltage-Switched Logic (DCVSL),first described at the ISSCC in 1984 by Larry Heller,[Heller84], is the foundation of later higher-speed cir-cuit structures. DCVSL influenced subsequent differ-ential innovations appearing in industrial applications.The author was privileged to work with Dr. Heller.

A number of DCVSL variations exploit the benefit ofusing pairs of differential logic inputs to flip a staticcross-coupled device pair and store an output state.DCVS is noise immune and logically complete. Treesof stacked evaluation devices potentially couple thecircuit’s output node to ground, conditional upon theresult of the evaluation. Referring to Figure 4, withinput B high and input B-not low, transitioning highinput A and transitioning low input A-not are fed tothe differential evaluate tree, latching node Q-not low,and node Q high. DCVSL improves logic den-sity byevaluating complex trees of logic in one delay stage.

Differential-pair logic trees may easily be 4 devicestall, and process (24-1) inputs. The stacks of largePFETS in the evaluate path are now gone. Booleanfunctions are implemented in NFETs only; the PFETsserve solely as pull-up devices. Static DCVS logicoffers implicit noise immunity at each stage, due to itscross-coupled nature. Performance can be compro-mised, however by “hysteresis”, caused by the intrin-sic difficulty associated with switching a latch. ThePFET load devices must be small enough that its on-current is easily overcome by the switching logicalpull-downs, but large enough to drive high out-putswith acceptable delays.

Because true or complement outputs are notalways needed yet always provided by DCVS, andbecause noise immunity was achieved in other ways,the ‘need-for-speed’ eventually took DCVS out of thecircuit line-up.

Pass Gates and Transmission GatesFET devices configured as pass transistors appearedhistorically as an integral component of a fundamen-tal MOS circuit, the one-device DRAM cell. Pass gatesare also indispensable in SRAM memory. It is no sur-prise then, that their versatility is exploited in CMOSlogic. Hitachi, in the mid 90s, proposed circuits using

pass-gate based circuit libraries (“Lean Integration”)with substantial performance advantages as shown inFigure 5 [Yano94].

The style required a “lean inverter” as shown in theinset. This half-latch restored signals which had beenreduced by one VTE to full high voltage levels. Othercompanies employed alternative pass-based circuit fam-ilies such as Complementary Pass Logic (CPL) [Yano90]and Double Pass Transistor Logic (DPL) [Suzuki93]. Seethe references for explanations of their operation.Although quite fast, pass gate structures have intrinsi-cally more vulnerabilities than static. Vulnerabilitiesinclude fan-out limitations, noise, body effect/sourcefollower action, and decode exclusivity [Bernstein98].

A variant of the pass gate, the transmission gate,added a PFET in parallel with the NFET pass gate,driving it with the complement of the NFET’s gate sig-nal [Dillinger88]. The PFET avoids the NFET sourcefollower behavior, insuring that the output signal willachieve the full Vdd output level, but at the cost ofadditional devices and power.

As chip device counts reached into the hundreds ofmillions in the late 90s, pass gate based logic usedeclined, mainly due to (a) the added design attentionthey required compared to slower but simpler combi-natorial structures, and (b) the above sensitivity todevices characteristics, which have increased withCMOS scaling.

CMOS Dynamic LogicDynamic circuits use the presence or absence ofcharge rather than voltage to evaluate logical inputs.Dynamic Dominos are the most common form ofCMOS Dynamic logic, enjoying a 20-50% performanceadvantage over static circuitry. Single-ended dynamicdomino, first proposed in 1982 [Krambeck82],implicitly eliminates race conditions between compet-ing logic paths, and was seen in the highest speedlogic designs, including the DEC Alpha Microproces-sor family [Williams96].

Dynamic Dominos are composed of precharge,evaluate, and buffer functional blocks.

The single-ended dynamic domino realization of atwo-way AND function is shown in Figure 6.

RESEARCH HIGHLIGHTS

Fig. 4 CMOS Differential Cascode Voltage Scheme (DCVS)

Fig. 5 CMOS LEAP/LEAN Pass-transistor Logic


RESEARCH HIGHLIGHTS


During precharge, clock PC is low. PFET device 1charges node N1 to VDD, driving output Q to groundand turning on “keeper” PFET device 2. “Foot switch”NFET device 5 is off, interrupting the path to groundduring precharge of the evaluate block. The evaluateblock is represented by devices 3 and 4. When PCtransitions high, the circuit switches from precharge toevaluate mode. With logic inputs A and B high, nodeN1 is coupled to ground, switching the output ofinverter buffer I1 high and turning off keeper PFETdevice 2.

Single ended dominos can contain a substantialamount of logic “width” in the NOR direction, and“depth” in the NAND direction. This enables signifi-cant “logic gain” along a path of dominos. PFETdevice 2 is an optional device which providesreplacement charge for leakage loss from node N1.This keeper, with the output inverter/buffer, forms a“half-latch,” introduces some hysteresis. If the circuitis pre-charged every clock cycle, and if the clocknever quiesces the domino stage in it’s evaluatemode, then the keeper is often omitted. As powerbecame precious in CMOS, Domino had a strikeagainst it because of the precharge clock power everycycle. Strike two came from poor fail diagnosability,since internal nodes can’t be interrogated. Leakagevariability impacts Domino’s noise margin in deeplyscaled CMOS; Domino ultimately struck out for all buta few important remaining logic applications.

Who’s on deck?Novel FET structures have been proposed to keepfield effect transistors scaling for a few more innings.For the most part, these devices are “evolutionary”rather than “revolutionary:” FinFETs [Nowak03], andCarbon Nanotubes [Javey03] schematically and logi-cally may be treated as MOSFETs by circuit design-ers. The references have the details. A few notewor-thy emerging design practices, however, have thepotential of disrupting the design of future products.Techniques include body biasing and reduced-volt-age operation. Let’s take a closing look at theserookies.

The body or substrate node of the MOSFET isthe long-neglected 4th device terminal. While it iswell-known that the potential of the body directlyinfluences the threshold voltage of the device,until recently little was done to actively managedevice threshold. The advent of the triple-wellbulk CMOS [Kontos06] and the isolated-body par-tially-depleted SOI CMOS [Shahidi99] processesprovide opportunities for contacting groups ofbodies and controlling threshold. Many schemeshave been proposed to vary body voltage to tradeoff active performance with standby power[Tschanz02]. These schemes are used (a) to collec-tively put unused resources into low-power sleepmode; (b) to dynamically adjust for across-chipvariability; or (c) to simply improve performance.As overdrive becomes more precious at low volt-age operation, body-biasing will sustain reducedsupply voltage performance [Park06]. DynamicThreshold CMOS (“DTCMOS”) connects the SOI-MOSFET’s gate to its body and operates the deviceat voltages less than Vdiode [Assaderaghi94]. Thestructure, shown schematically in Figure 7, may beuseful if key problems are fixed: solutions haveyet to come forward.

Wrap-upJust as many generations have enjoyed the game ofbaseball [Baseball06], generations of CMOS scalinghave provided us with higher and higher speed tran-sistors. The technical marvels which enhance ourlives come directly from the innovative ways wearrange and connect these “players”. It’s safe to saythat if we can keep improving our “roster”, we’llcontinue to fill the ballpark [Leventhal06] with happyVLSI fans!

AcknowledgmentsThe author thanks Lewis Terman for importantinsights and suggestions.

Fig. 6 Dynamic Domino Realization of 2AND

Fig. 7 Dynamic Threshold CMOS ties the gate to the float-ing body



RESEARCH HIGHLIGHTS

References[Abidi87] A. Abidi, et al., “An analysis of bootstrapped

gain enhancement techniques” IEEE Journal ofSolid-State Circuits, Volume 22, Issue 6, Dec 1987pp. 1200 - 1204

[Assaderaghi94] F. Assaderaghi, et al, “A DynamicThreshold Voltage MOSFET (DTCMOS) for Ultra-low Voltage Operation”, 2004 (IEDM), Dec. 2004,pp. 809-812

[Baseball06] Editors of Sports Illustrated, “The Base-ball Book”, Sports Illustrated Publishing, Oct 2006

[Bernstein98] K. Bernstein, et al, “High Speed CMOSDesign Styles”, Kluwer Academic Publishers, 1998

[Chandrakasan01] A. Chandrakasan, et al, “Design ofHigh Performance Microprocessor Circuits”, IEEEPress, 2001, pp. 119-139

[Dillinger88] T. Dillinger, “VLSI Engineering,” Prentice-Hall Publishing, 1988, pp. 433-435

[Hardee81] K.C.Hardee, et al, “A fault-tolerant 30ns/375 mW 16K/spl times/1 NMOS static RAM”,IEEE Journal of Solid State Circuits, Oct 1981, pp.435 - 443

[Heller84] L. Heller, et al, “ Cascode Voltage SwitchLogic: A Differential CMOS Logic Family”, 1984IEEE ISSCC, pp. 16-17

[Hirata96] A. Hirata, et al., “Estimation of short-circuitpower dissipation and its influence on propagationdelay for static CMOS gates”, 1996 IEEE ISSCC, pp.751 - 754

[Javey03] A. Javey et al., “Advancements in comple-mentary carbon nanotube field-effect transistors”,2003 IEEE (IEDM), Dec. 2003, pp. 31.2.1 - 31.2.4

[Kontos06] D. Kontos, et al, “Investigation of ExternalLatchup Robustness of Dual and Triple WellDesigns in 65nm Bulk CMOS Technology”, Pro-ceedings of the 2006 IEEE International ReliabilityPhysics Symposium, pp. 145 - 150

[Krambeck82] R.H. Krambeck, et al, “High SpeedCompact Circuits with CMOS”, IEEE Journal ofSolid-State Circuits, No. 3, June 1982, pp. 614-619

[Leventhal06] J. Leventhal, “Take Me out to the Ball-park: An Illustrated Tour of Baseball Parks Past andPresent”, Black Dog Publishers, Feb 2006

[Nowak03] E.J. Nowak, et al., “Scaling Beyond the65nm Node with FinFET-DGCMOS”, Proceedingsof the 2003 IEEE CICC

[Park06] D. Park, et al, “An Adaptive Body-BiasedVCO with Voltage-Boosted Switched Tuning in 0.5-V Supply”, 2006 European Solid-State Circuits Con-ference, pp. 444 - 447

[Shahidi99] Shahidi, G.G, et al, “Partially-depleted SOItechnology for digital logic”, 1999 ISSCC, pp. 426 -427

[Streetman80] B.G. Streetman, “Solid State ElectronicDevices”, Prentice Hall, 1980

[Subba00] N. Subba, et al., “Pseudo-nMOS revisited:

impact of SOI on low power, high speed circuitdesign” 2000 IEEE International SOI Conference,pp. 26 - 27

[Sutherland99] I. Sutherland, et al., “Logic Effort:Designing Fast CMOS Circuits”, Morgan KaufmannPublishers, 1999

[Suzuki93] M. Suzuki, et al, “A 1.5ns 32-b CMOS ALUin Double Pass-Transistor Logic”, IEEE Journal ofSolid-State Circuits, November 1993, pp. 1145-1151

[Tschanz02] J. Tschanz, et al., “Adaptive body bias forreducing impacts of die-to-die and within-dieparameter variations on microprocessor frequencyand leakage”, IEEE Journal of Solid State Circuits,Nov. 2002, pp. 1396 - 1402

[Wanlass63] F. Wanlass, et al, “Nanowatt logic usingfield-effect metal-oxide semiconductor triodes”,Digest of Technical Papers, 1963 ISSCC, pp. 32 - 33

[Williams96] T. Williams, “Dynamic Logic: Clockedand Asynchronous”, 1996 ISSCC, Tutorial Proceed-ings #4

[Yano90] K. Yano, et al, “A 3.8 ns CMOS 16 x 16 mul-tiplier using complementary pass transistor logic”,IEEE Journal of Solid-State Circuits, Vol. 25, No. 2,April 1990, pp. 388-395

[Yano94] K. Yano, et al, “Top-Down Pass-TransistorLogic Design”, IEEE Journal of Solid-State Circuits,Vol. 31, No. 6, June 1996, pp. 792-803

About the AuthorKerry Bernstein is a Senior TechnicalStaff Member at the IBM T.J. WatsonResearch Center, Yorktown Hts, NY.He currently is Principal Investigatorfor 3D integration technology at IBMResearch, exploring 3D microproces-sor and memory architectures, and 3D

circuits. Mr. Bernstein received the B.S. degree inelectrical engineering degree from Washington Uni-versity in St.Louis, and joined IBM in 1978.

Mr. Bernstein’s work has bridged technology andcircuit design, exploring the technology sensitivitiesof high performance CMOS circuit topologies; the mit-igation of delay variability in design; and the circuitresponses to single-event upsets. He served as leadtechnologist for IBM’s POWER Server series and forIBM’s PowerPC microprocessor family. He also super-vised technology application for IBM’s highest per-formance external foundry customers. Mr. Bernsteinhas had the privilege of participating in the teamsdeveloping and introducing fundamental device andinterconnect technologies to the industry throughouthis career, including NMOS, CMOS, Partially-DepletedSilicon-On-Insulator devices, and copper/Low-K inter-connects.

Mr. Bernstein holds 50 U.S. patents in the areas ofhigh performance circuits and technology. He co-authored 2 college textbooks with colleague and


RESEARCH HIGHLIGHTS


friend Norman Rohrer, and approximately 100papers or book chapters on high speed / low powerCMOS. He attributes any success he has enjoyed tobe due in large part to working with wonderful, tal-ented people. Mr. Bernstein has served on the pro-gram committees for IEEE ISSCC and Symposium onVLSI Design. He derives fulfillment as an industrialmentor for students and research at SEMATECH,

SRC/MARCO, DARPA, and for high schoolers inter-ested in math/science/engineering careers. Mr. Bern-stein is a staff instructor on Computational Neuro-science at RUNN/Marine Biological Laboratories,Woods Hole, MA, and a commanding officer in theHQ Battalion of the Vermont State Guard. He andhis family live in Northern Vermont. Mr. Bernstein isan IEEE Fellow.

The (Pre-) History of the Integrated Circuit: A Random WalkBy Thomas H. Lee, Center for Integrated Systems, Stanford University, Stanford, CA,[email protected]

The half-century of the integrated circuit haswitnessed so many technical miracles that per-haps engineers can be forgiven for being a lit-

tle blasé. But a little reflection should astonish eventhe most jaded: The silicon we use comes as giantmonocrystals weighing hundreds of kilograms, andwhose impurities are denominated in sub-parts perbillion. On the wafers cut from these boules we reg-ularly inscribe features with lateral dimensions oftens of nanometers (using light whose free-spacewavelength is several times larger), and routinelygrow layers with controlled thicknesses of only afew atoms. If those technical facts are too familiar,then perhaps a biological comparison will impress:The aggregate number of transistors produced annu-ally exceeds the number of ants on Earth. For eachof an estimated 170dB ants, the IC industry fabricatesabout ten transistors each year, and that number isincreasing exponentially. These remarkable achieve-

ments beg several questions: How did we get to thispoint, and how long can this continue? And whatcomes next?

Attempting to predict the future is often foolish andfruitless, but perhaps looking backwards is a usefulway to discern at least the outlines of possible futures.The history of the IC is not at all the neat, linear andlogical narrative found in many textbooks and pressarticles. In truth, there were false starts, dead ends, U-turns, titanic egos, geopolitics, frustrating failures,ideas that were ahead of their time, and ideas that willnever be of any time. The story of the chip is, afterall, a human story.

The standard capsule history of the integrated cir-cuit usually goes something like this: Vacuum tubesdominate the first half of the 20th century, but theirlimitations stimulate a search for alternatives. Thedevelopment of solid-state PN junction diodes leadsnaturally to transistors in 1947, and then to the planar

TECHNICAL LITERATURE

History Center adds 75 New Oral Histories to Web Site

The IEEE History Center has added 75 new oral his-tories to its online archive. The oral histories areorganized into nine different collections and

include interviews with Gordon Moore, the developer ofMoore’s law and co-founder of Intel Corporation, RobertNoyce, one of the inventors of the integrated circuit andWilson Greatbatch, who helped develop the implanted,

cardiac pacemaker. All oral histories are in PDF formatand include an abstract and an index.

To view the list of collections, visit www.ieee.org/web/aboutus/history_center/oral_history/oral_history.html; for an alphabetical listing, visit www.ieee.org/web/aboutus/history_center/oral_history/oh_a_fo.html.



TECHNICAL LITERATUREprocess and inevitably to the IC about a decade later.Moore’s law gets established, and exponential scalingcontinues beyond expectations, thanks to a vast, sus-tained multidisciplinary effort. Ultimately the gigas-cale era arrives on schedule, allowing every ant tohave a transistor radio.

Pre-vacuum tube semiconductorsAs a counterpoint to the truncated standard ver-sion, consider that the first solid-state rectifierswere built by accident, out of materials other thansilicon, long before there were any compellingapplications for semiconductors, and well beforethe physics necessary for understanding them hadbeen developed. Future Nobelist Ferdinand Braun,working at the University of Würzburg as an assis-tant shortly after receiving his doctorate, wasinvestigating the validity of Ohm’s law. After find-ing violations of Ohm’s conjecture in electrolyticsolutions, he discovered in the early 1870s that cer-tain naturally-occurring metallic sulfides couldexhibit asymmetrical conduction as well [Braun,1874]. Among the minerals he studied were chal-copyrites (sulfides of copper and iron), as well asgalena (lead sulfide). His inability to provide anoperative theory compounded the lack of anypractical use for these crude rectifiers, assuring therelative obscurity of this work for decades.

The dawn of the wireless age provided thenecessary stimulus for engineers to revisitBraun’s work thirty years later. The need for sen-sitive detectors was particularly acute. An earlydevice introduced primarily by Edouard Branly(based on an accidental discovery by one Temis-tocle Calzecchi-Onesti) and developed further byMarconi was the coherer [Scott, 1955]. Consistingof metallic filings loosely packed within a glasstube, the resistance of a coherer is initially high.When triggered by a sufficiently strong electro-magnetic signal, the resistance can drop severalorders of magnitude. Shaking the cohererrestores the high-resistance state. Frustration withthe coherer’s erratic nature and low sensitivityimpelled an aggressive search for better detec-tors. Without a suitable theoretical framework asa guide, however, this search sometimes tookmacabre turns. In one case, a human brain froma fresh cadaver was even tested as a coherer,with the flamboyant, and soon-to-be convictedfelon, A. Frederick Collins, claiming remarkablesensitivity for his carbon-based apparatus[Collins, 1902].

Most detector research was guided by the vaguenotion that the coherer’s operation depends onsome mysterious property of imperfect contacts.Haphazard, but determined experimentation witha vast combination of materials eventually led a

variety of researchers to stumble, virtually simulta-neously, on the point-contact detector. The firstpatent for such a device was awarded in 1904 tothe remarkable J.C. Bose for a detector that usedthe galena identified by Braun thirty years earlier[Bose, 1904]. This patent appears to be the firstawarded for a semiconductor detector, although itwas not recognized as such (indeed, the wordsemiconductor had not yet been coined, as semi-conductors were not yet acknowledged as a dis-tinct class of materials). Soon after, Henry HarrisonChase Dunwoody filed a patent application for adetector using silicon carbide (carborundum), amaterial that had been produced accidentally adecade earlier during attempts by Edward Ache-son to create artificial diamonds. On Dunwoody’sheels was Greenleaf Whittier Pickard (whosegreat-uncle was the poet John Greenleaf Whittier),who applied for a patent on a silicon detector[Dunwoody, 1906; Pickard, 1906]. Although Dun-woody actually applied for his patent first,Pickard’s was granted a month sooner. The sim-plicity and excellent performance of galena, car-borundum, silicon and other semiconductor detec-tors (collectively called crystal detectors byGeorge W. Pierce of Harvard) rapidly drove coher-ers into obsolescence.

One electrical connection to a crystal detector isusually made with a small wire (whimsicallyknown as a catwhisker) that contacts the crystalsurface rather lightly at a single point. It is at thisinterface that rectification occurs. Too high a con-tact pressure produces an ohmic contact; too lighta pressure results in excessive series resistance.Adjustment is typically delicate and tenuous. Theother connection is a large-area ohmic contact typ-ically formed by a clamp to the body of the crys-tal, or through the use of a low-melting-point con-ductive alloy (e.g. Wood’s metal) in which the crys-tal is embedded. In modern parlance, one mightcall a device made this way a point-contact Schot-tky diode, although measurements are rarely quan-titatively reconciled with such a description. Cer-tainly, no two point-contact devices are alike; thecathode may or may not correspond consistentlywith either the catwhisker or the large-area con-tact, for example. Even for a given device, there isenormous variability over the surface, and onemust hunt for a good spot, with no assurance thatone will be found.

The origin of the modern schematic symbol for adiode is apparent from Pickard’s patent drawing(fig. 1). The element labeled “TJ” is the point-con-tact diode.

This symbol originally depicted the physical struc-ture, without regard for polarity. In short order, thedrawing gave way to a simpler schematic, with an




arrow representing the point contact, and a rectanglerepresenting the semiconductor bulk. The arroweventually took on the additional responsibility ofidentifying the direction of forward current, and therectangle ultimately collapsed to a single line repre-senting the cathode terminal.

Pickard worked harder than anyone else todevelop crystal detectors, eventually trying over30,000 combinations of wires and crystals [Dou-glas, 1981]. Among these are iron pyrites (fool’sgold) and rusty scissors, in addition to silicon.Galena came to be widely used because no bias isneeded for good results. However, adjustment ofthe catwhisker is particularly tricky (lore has it thatargentiferous galena – “steel galena” – isn’t asfussy). Silicon detectors are less exacting aboutcontact pressure, but can require a small (order of100mV) bias for best results. Carborundum detec-tors typically need a bias of several volts, but oper-ate satisfactorily with a relatively high contact pres-sure (indeed, many were packaged in cartridgesthat one adjusted by slamming against a hard sur-face). They found wide use aboard ships as a con-sequence. By around 1907 semiconductors hadbecome important in wireless technology, despitethe fact that no one could explain how theyworked. This First Age of Semiconductors lastedabout a decade, fading into history only after thevacuum tube had evolved to a reasonable statearound World War I.

The first semiconductor amplifiersAlthough this First Age had practically come to anend in the West by around 1920 or so, individualresearchers elsewhere soldiered on with the solidstate. One of the most remarkable (and virtuallyunknown) stories from this era is that of self-taughtSoviet engineer Oleg Losev and his solid-state ampli-fiers and oscillators [Losev, 1922]. Vacuum tubeswere expensive then, particularly in the SovietUnion so soon after the Revolution, so there wasnaturally a great desire to find more economical

alternatives. Losev chose to investigate the mysteriesof crystals.

His foray into semiconductor research resulted inhis independent rediscovery of blue electrolumines-cence from point-contact carborundum diodes [Loeb-ner, 1976]. Although Henry J. Round had first pub-lished on this phenomenon in 1907 [Round, 1907],Losev studied these blue LEDs in great detail. Hisfindings supported Round’s contention that the lightwas not due to incandescence. Armed with insightsinformed by a young quantum mechanics, Losev ulti-mately concluded that the cold light emission he wasobserving was the direct inverse of the photoelectriceffect. He could not go any further than that, and theabsence of a market for tiny, low-efficiency blue lightseventually led him to set aside this work.

Even more impressive than his insights into thebehavior of LEDs was his discovery of the negativeresistance that can be obtained from biased point-contact zincite (ZnO) crystal diodes. Although spo-radic reports of oscillation with galena, carborundumand other materials populate the literature startingsoon after this class of detectors was patented [e.g.,Eccles, 1909], the poor repeatability and poor per-formance of these devices kept them mere curiosities.Losev discovered that the limitations of zincite are lessserious. Thanks to zincite’s superior performance, hewas able to construct fully solid-state RF amplifiers,detectors and oscillators at frequencies beyond 5MHza quarter century before the invention of the transis-tor. He set about realizing a variety of classical radioarchitectures in solid-state form, including tuned-RF,heterodyne and regenerative receivers. He eventuallyabandoned the “crystadyne” technology after about adecade of work though, because of difficulties withobtaining zincite (it’s found in commercially signifi-cant quantity in only two mines, and they’re both inNew Jersey), as well as the problem of interstageinteraction inherent in using two-terminal devices toget gain, to say nothing of having to adjust more thanone point contact.

The reason almost no one in the U.S. has heard ofLosev is simple. First, it seems that there isn’t muchinterest in preserving the names and stories of engi-neering pioneers in general (e.g., few know who Ohmwas, aside from having had a law famously namedafter him). Plus, nearly all of Losev’s papers are in Ger-man and Russian, limiting readership. Add the gener-ally poor relations between the U.S. and the U.S.S.Rover much of the 20th century, and it’s actually a won-der that anyone knows who he was. Losev himselfwas unable to advocate for his place in historybecause he was one of an estimated million peoplewho starved to death during the terrible Siege ofLeningrad, breathing his last in January of 1942. Hiscolleagues at the Nizhegorod Radio Laboratory had

Fig. 1. J. W. Pickard and drawing from his 1906 patent



TECHNICAL LITERATUREadvised him to leave the city before the blockade wascomplete, but he was just too interested in finishing up“promising experiments with silicon.” Sadly, allrecords of those experiments have apparently beenlost. [Loebner, 1976].

History is not monotonicAround the same time that Losev was beginning hiswork with zincite, Lars Grondahl of the Union Switchand Signal Company in the U.S. was studying failuremechanisms in switch contacts and became curious asto why tarnished copper behaves as it does. He and acolleague, Paul Geiger, discovered that cuprous oxide(Cu2O) is a semiconductor (although, again, we areusing modern language and concepts that they did notuse). By around 1922 they had developed a rectifierbased on disks of copper abutting disks of cuprousoxide [Grondahl and Geiger, 1927]. In contrast withthe point-contact devices that preceded it, these arelarge-area rectifiers. As a result, these copper-diskdevices found use as high-power rectifiers, the firstsolid-state devices capable of doing so (fig. 2).

The Bell System eventually adopted them as well,to act as modulators for carrier-based telephony.Researchers were mystified as to why copper ofseemingly equal purity produced rectifiers of vastlydifferent quality. For example, copper from certainmines in Chile were found to be best, and so AT&Tobtained control over the copper supply from thesesources. Spectroscopic analysis was unable to identi-fy the reasons for the differences in quality, and thismystery persists to the modern day. Nonetheless, con-siderable developmental effort was expendedbecause of the commercial importance of copper diskrectifiers. By the late 1930s, cuprous oxide was themost highly developed semiconductor in use.

Pre-transistor transistorsThe growing number of useful phenomena observedin the solid state encouraged more widespread think-ing about what else could be done. Vacuum tubediodes had given way to triodes, so why shouldn’t

semiconductor devices follow the same historicalprogression?

Scarcely had Grondahl and Geiger announced thecopper oxide rectifier when Julius Lilienfeld began fil-ing patent applications for three-terminal solid-stateamplifiers, some of which seem to anticipate the MES-FET and MOSFET in many respects. Although there isno evidence that Lilienfeld ever actually built workingdevices, the basic concepts are sound. Indeed, Shock-ley’s patent application for a MOSFET was rejectedbecause of Lilienfeld’s patents.

An example is Lilienfeld’s first of three relatedpatent applications (fig. 3). Some sources refer to it asa MOSFET, others as a MESFET. In truth, it’s not quiteeither. Rather, it’s a literal reinterpretation of a triodevacuum tube in solid-state form.

The jagged structure down the middle is producedby cracking the transistor in two, and interposing a2.5μm thick electrode (analogous to a vacuum tubegrid) in the space produced. The two halves are thenreassembled. In an echo of Braun, Lilienfeld suggestsusing copper sulfide as the semiconducting materialthat makes up the bulk of the device [Lilienfeld, 1930].

Rudolf Hilsch and Robert Pohl have the distinctionof having published the first experimental data for athree-terminal solid-state amplifier. In 1938 theyreported their results on an alkali halide-based device[Hilsch and Pohl, 1938]. Although the large dimen-sions (necessitated by the requirement that the space-charge layer accommodate a grid-like control elec-trode) guaranteed sub-Hz frequency response, thefact that it worked at all provided important encour-agement to those following the field.

The story of point-contact devices begins anewaround this same period, thanks to the demands ofmicrowave technology. During his research intowaveguide propagation of microwave signals, GeorgeSouthworth of Bell Labs was frustrated by the poorperformance of vacuum tube detectors at microwavefrequencies. In desperation, Southworth decided totest some ancient point-contact detectors. He rea-soned that the tiny point contact might have a corre-spondingly low capacitance, and thereby enable

Fig. 2. Copper-disk devices found use as high-powerrectifiers

Fig. 3. J. J. Lilienfeld, method and apparatus for control-ling electronic currents




operation at the higher frequencies desired. A trip tothe surplus shops of New York‘s Cortlandt Alley wasall it took to find some crystal detectors. After clean-ing up the dusty relics, he discovered to his relief anddelight that they indeed worked extremely well. Thisconspicuous success encouraged others to reconsiderthe utility of point-contact devices specifically, andsemiconductors in general.

Southworth’s success had far-ranging consequences.Indeed, the modern age of silicon traces directly backto that achievement. The development of radar inWorld War II was made possible by the point-contactsilicon detector (fig. 4). In turn, the vast resources ded-icated to the development of semiconductors duringthe war set the stage for all that was to come.

The late-1930s saw a lively debate about whatmade a given sample of semiconductor n-type or p-type. Spectroscopic analysis with the best instrumentsavailable was unable to provide definitive answers.One day Jack Scaff and Henry Theuerer of Bell Labshappened to saw through an n-type portion of a sili-con ingot. As the saw cut through the material, theyboth smelled an odor that was familiar to these twoexpert chemists. They had smelled something similarin their youth, when cars had headlamps fueled byacetylene. Trace amounts of phosphorus-bearingcompounds gave off a characteristic odor as thelamps burned. Realizing the implications of phospho-rus in their n-type ingot, they understood what waslikely making their sample n-type. Their highlytrained nostrils had provided a solution to a long-standing mystery, and pointed researchers toward anew understanding of doping [Riordan and Hoddes-on, 1997].

At almost the same time as Scaff and Theuerer’snoses were putting spectrographic analysis to shame,their colleague Russell Ohl discovered both the pho-tovoltaic effect and the PN junction in silicon, in thatorder. By chance, an ingot had been processed in away that left it n-type at one end and p-type at theother. Somewhere near the middle was a PN junction.Ohl found it by dutifully making resistance measure-

ments along the ingot. He noticed erratic readingsnear the middle and, after investigating, discoveredthat it was due to the modulation of his laboratorylighting by a spinning fan blade. He was astonishedto measure nearly half a volt across the junction, forthe copper-oxide photocells then in use typically gen-erated only a tenth of that. Investigating further, hediscovered the rectifying properties of the same struc-ture [Riordan and Hoddeson, 1997]. By about 1940,then, doping was understood, the PN junction hadbeen discovered, and a good body of phenomeno-logical knowledge was being gathered.

Sometimes, obsessive behavior is a good thingThe early history of semiconductors is one of makingdo with naturally-occurring polycrystalline materials,for the most part. Shockley didn’t feel that the lack ofmonocrystalline starting materials was a seriousimpediment to progress, and even went as far as dis-couraging others at the Labs from undertaking anylarge-scale efforts dedicated to growing single crys-tals. After all, as Shockley noted, polycrystalline point-contact detectors had served wartime radar quite well.Fortunately for the history of electronics, Gordon Tealwas undaunted by Shockley’s opposition. Teal knewthat early vacuum tubes were erratic because of poorvacuum technology, and was well aware that the elec-trical characteristics of tubes improved markedly, asdid their predictability and repeatability, as bettervacua were obtained. He saw in that history lesson ananalogy with semiconductors. He was certain that themessiness of polycrystalline substances was likelyresponsible for the poor performance and high vari-ability exhibited by early semiconductor devices. Hefelt strongly that the availability of more-perfect mate-rials was essential to moving the field forward. With-out his near-obsession with material perfection, semi-conductor technology would have had a muchrougher time at a critical period. Teal was clearly theright man for the job, for this is the same person whohad chosen for his doctoral thesis the study of ger-manium because “its complete uselessness fascinatedand challenged” him [Teal, 1976].

Discovering the transistorAs described beautifully in the companion article byRiordan and Hoddeson in this issue, Bardeen andBrattain discovered the transistor, in much the samemanner as Ohl had discovered the PN junction diode.Shockley had first assigned his team the task of con-structing a MOSFET, but they met only repeated fail-ure. Switching from a messy compound semiconduc-tor, copper oxide, to an elemental one, germanium,didn’t help. It was during the course of a series ofingenious diagnostic experiments that Bardeen andBrattain accidentally created a solid-state amplifier. It

Fig. 4. Polysilicon microwave diodes, c. 1945



TECHNICAL LITERATUREwasn’t the MOSFET that Shockley had been hopingfor. Indeed, how it worked was still a topic of hotdebate. Shockley’s delight at his group having madesomething that worked was balanced by his frustra-tion at having been a mere spectator. He withdrewsocially, and worked madly to understand what theyhad built, and then use those insights to design some-thing better still that he could call his own. His workpaid off, for he was the first to understand explicitlythe role of minority carrier injection. That under-standing in turn allowed him to invent the junctiontransistor. In a first for semiconductors, he correctlydescribed the terminal characteristics of the bipolarjunction transistor several years before one was built[Shockley, 1976].

Bell Labs began to manufacture the point-contacttransistor in 1948, using polycrystalline germanium.Not far behind was Raytheon, which managed todevelop its own point-contact transistor, the CK703, ina crash program less than six months after engineerNorman Krim witnessed a demonstration at Bell Labsin July of 1948 [Goldstein, 2003]. In 1951 Krim hap-pened to room with Shockley while the two spent aweek serving on a government committee. Krim tookcareful mental notes as Shockley spoke freely abouttransistor developments. Realizing the growing impor-tance of quartz tubes and germanium, the crafty Krimarranged for Raytheon to corner the market on quartztubing as well as to buy up all the germanium pro-duced by Eagle-Picher, a Missouri firm whose outputaccounted for over 90% of the world’s supply ofdevice-grade germanium [Goldstein, 2003].

For engineers who have worked with junction bipo-lar transistors, point-contact devices seem exotic. Theparameter alpha can exceed unity (sometimes by anorder of magnitude), implying a negative beta! It ispossible to make a single-transistor latch, thanks to thisproperty. Although many theories have been advancedover the years to explain this odd behavior, Shockley’sexplanation fits the largest range of data. During themanufacture of a point-contact transistor, a brief surgeof current is passed through the collector in a some-what mysterious process called “forming.” The energiesare high enough to cause local diffusion of atoms fromthe catwhisker into the semiconductor, and perhapsproduce what amounts to a PNPN-like structure. Thismodel is the only published one that can explain thevery high alpha values occasionally encountered atvoltages low enough to preclude impact ionization andavalanche multiplication. With or without a model, thepoint-contact transistor was simply too unreliable tocompete seriously with the vacuum tube. This limita-tion is hardly surprising, considering the unreliability ofits point-contact diode ancestors. That’s why Bell Labsexpended so much effort to realize Shockley’s bipolarjunction transistor in a practical way. By the early tomid-1950s, they had succeeded.

Despite Shockley’s numerous technical achieve-ments, his inability to get along with many of his col-leagues did not go unnoticed at the Labs, and he wasfrustrated to find his path to promotion blocked. Heeventually decided it was time to move back to hishometown of Palo Alto, California, where his agedmother still lived. Proximity to Stanford University,with its pool of students as potential employees for thecompany he planned to found, was an added lure.

He assembled a remarkably talented foundinggroup for the Shockley Semiconductor Laboratory,but was unable to manage them well. His idiosyn-cratic (indeed, often paranoid) style led to a famousmass resignation by eight gifted employees on 18September 1957. In business as in comedy, timing iseverything. The “Traitorous Eight,” as Shockleyreferred to them thereafter, went on to found FairchildSemiconductor, just as the launching of Sputnik by theSoviet Union on October 4 immediately created ademand for compact, lightweight and low-powerelectronics to help win the Space Race.

A year later, a recently hired Jack Kilby found him-self nearly alone at Texas Instruments when most ofthe company took a two-week vacation. Rather thansitting idle while his boss was away, Kilby consideredthe engineering challenges associated with miniatur-ized electronics, and realized that the IC was possible.On 12 Sept. 1958, he successfully demonstrated a1.3MHz integrated RC oscillator (fig. 5). Because TIhad not yet mastered the art of diffusion in silicon, thefirst IC was built out of germanium bits. Bondwiresinterconnected the various components because Kilbyhad not solved that problem yet. He was preoccupiedwith proving the basic IC concept.

At Fairchild, Bob Noyce had been thinking alongsimilar lines. Rumors of TI’s achievement spurred himinto action, and he quickly combined the planarprocess ideas invented by his colleague, Jean Hoerni,with his own ideas about photolithographically-defined interconnect and junction isolation. Later, hediscovered that Kurt Lehovec at Sprague had alreadyanticipated junction isolation. Nonetheless, Fairchild

Fig. 5. First IC: 1.3MHz RC oscillator




was the first to describe explicitly a complete flow forbuilding a practical integrated circuit. After protractedlitigation between TI and Fairchild, the two compa-nies decided to declare a draw, and call Noyce andKilby (and thus their respective companies) co-inven-tors of the integrated circuit.

Today the IC is so valuable and ubiquitous that it ishard to imagine a time before the chip. As obviouslygood an idea as it may appear to be today, the IC wasnot warmly greeted at its birth. Many engineersthought of it as an expensive stunt. Others thoughtthat yields would never be high enough to be practi-cal (and would plummet anyway if you were foolishenough to increase the number of components).Fairchild first described their IC at the 1960 IRE-AIEEConference on Transistor Circuits (later to becomeISSCC). The polite interest expressed by attendeesstood in stark contrast to the near mania for the tun-nel diode, a device that all the experts were certainwould change the face of technology. Fortunately,Noyce and others in the fledgling industry pressedonward (perhaps because they had no practical alter-native), and put us finally on the path that we con-tinue to travel today.

Ultimately, Shockley’s company changed hands acouple of times, finally disappearing within the bow-els of ITT, never having turned a profit. Shockley gaveup his entrepreneurial ambitions and became a Stan-ford professor. His insistence on turning nearly everyconversation into a debate on race made him a pari-ah on campus.

Fairchild went on to establish Moore’s law, buteventually Moore and Noyce left to found Intel.

As we’ve seen, the path to the present was any-thing but linear. Even if one were to argue that theendpoint – planar silicon technology – was all butinevitable, there were so many forks in the road alongthe way that the path to the present was by no meansunique. Given how the past unfolded, it is likely that

the future will evolve in a similarly random walk.Over the short term, the future will look like a sensi-ble extension of the present. Over a longer period,however, there will be nonlinear changes of a typethat are hard to predict. But even if we can’t say whatthose changes will be, we can assert with confidencethat they’ll happen.

Every generation seems to worry that “all the goodstuff has already been invented.” As an antidote to thatsort of thinking, consider that technology has by nomeans wrung out all that nature has to offer. Leading-edge microprocessors today consume on the order of100 watts, but have yet to compose anything as sublimeas, say, the Brahms piano trio, Op. 8, no.1. The humanbrain consumes about 20-25 watts, and is capable of therich array of creative (and destructive) behaviors char-acteristic of our species. The gap in performancebetween carbon and silicon is made all the more starkwhen we compare the picosecond-level switchingspeeds of electronics to the microsecond speeds of biol-ogy. Yet, despite the apparent performance deficit atthe device level, biology wins by an enormous marginat a great many tasks. Nature has thus provided ampleevidence that we have only scratched the surface. Ifengineers are given the “will to think” about doingmore, more will get done. As rocket scientist Wernhervon Braun famously noted, “Man is the only computerthat can be mass-produced by unskilled labor.” There isstill plenty of room to grow.

Addendum Kilby definitely was preoccupied with the devicesthemselves, and didn’t focus at all on the interconnectproblem. With Noyce, it was a bit the other wayaround. His choice of aluminum was considered curi-ous at the time, because conventional wisdom heldthat, as an acceptor material, using aluminum was a badidea. Some lore (from Bell Labs) also suggested that alu-minum didn’t adhere well to oxide. So, when GordonMoore sought to implement Noyce’s interconnect idea,he tried just about every metal *but* aluminum. Afterreporting to Noyce that all of these presented seriousproblems of one kind or another, Noyce suggested try-ing aluminum because it was about the only thing left.Moore was pessimistic, but dutifully tried it. The rest ishistory.

ReferencesBose, Jagadish Chandra (Jagadis Chunder), “Detector

for electrical disturbances,” U.S. Patent 755,840,filed 30 September 1901, issued 29 March 1904.

Braun, Ferdinand, “Ueber die Stromleitung durchSchwefelmetalle (On current flow through metallicsulfides).” Annalen der Physik und Chemie, v.153,1874, pp. 556-563. He was christened Karl Ferdi-nand Braun, but never used his first name or first

Fig. 6. First IC: 1.3MHz RC oscillator



TECHNICAL LITERATUREinitial. His doctoral thesis is signed simply ‘Ferdi-nand Braun,’ for example. Some academics startedadding ‘Karl’ about 10 years ago, a practice thatBraun’s descendants find odd and somewhat irk-some.

Collins, A. Frederick, “The effect of electric waves onthe human brain,” Electrical World and Engineer,v.39, 1902, p. 335. He started out with brains ofother species and worked his way up to humans.

Douglas, Alan, “The crystal detector,” IEEE Spectrum,pp. 64-67, April 1981.

Dunwoody, H. H. C., “Wireless telegraphy system,”U.S. Patent 837,616, filed 23 March 1906, issued 4December 1906.

Eccles, William H., “On an oscillation detector actuat-ed solely by resistance-temperature variations,”Proc. Phys. Soc. London, v.22, 1909, pp.360-368.

Goldstein, Harry, “The Irresistible Transistor,” IEEESpectrum, March 2003, v.40, pp. 42- 47.

Grondahl, Lars and Geiger, Paul H., “A new electron-ic rectifier,” Trans. AIEE, vol. 46, 1927, pp. 357-366.Also see “Unidirectional Current-Carrying Device,”U.S. patent 1,640,335, filed 7 January 1925, issued23 August 1927.

Hilsch, Rudolf and Pohl, Robert W., “Steuerung vonElektronenströmen mit einem Dreielektro-denkristall und ein Modell einer Sperrschicht (Con-trol of electron flow with a three-electrode crystaland a model of a barrier layer),” Zeitschrift fürPhysik, v.111, May 1938, pp.399-408.

Kilby, Jack St. Clair, “Miniaturized Electronic Circuits,”U.S. patent 3,138,743, filed 6 February 1959, issued23 June 1964.

Lilienfeld, Julius E., “Method and apparatus for con-trolling electric currents,” U.S. patent 1,745,175,filed 8 October 1926, issued 28 January 1930. Alsosee 1,877,140 and 1,900,018.

Loebner, Egon, “Subhistories of the light-emittingdiode,” IEEE Trans. on Electron Devices, ED-23, no.7, pp. 675-699, July 1976.

Losev, Oleg, “Detector-Generator; Detector-Amplifi-er,” Telegrafia i Telefonia bez Provodov, v.14, 1922,pp. 374-386. German-language publications renderhis name as Lossev, with the double-s correspon-ding to an unvoiced consonant in that language.We have chosen a transliteration that is closer tothe original spelling.

Pickard, G. W., “Means for receiving intelligence com-municated by wireless waves,” U.S. Patent836,531, filed 30 August 1906, granted 20 Novem-ber 1906.

Riordan, Michael and Hoddeson, Lillian, Crystal Fire:The Birth of the Information Age. New York: W. W.Norton & Company, 1997.

Round, Henry J., “A note on carborundum,” Electrical

World, 1907, v. 49 p. 308.Scott, T. R., Transistors and other crystal valves, Mac-

Donald and Evans, Ltd., 1955. Scott’s referencesreveal that the coherer was discovered independ-ently several times between 1835 and 1890.

Shockley, William B., “The path to the conception ofthe junction transistor,” IEEE Trans. on ElectronDevices, ED-23, no. 7, pp. 597-620, July 1976.

Teal, Gordon K., “Single crystals of germanium andsilicon – Basic to the transistor and integrated cir-cuit,” IEEE Trans. on Electron Devices, ED-23, no.7, pp. 621-639, July 1976.

Additional reading:The story of early crystal detectors is well told by D.Thackeray in “When tubes beat crystals: early radiodetectors,” IEEE Spectrum, pp. 64- 69, March 1983.Material on other early detectors is found in a delight-ful and comprehensive volume by V. Phillips, EarlyRadio Wave Detectors, Peter Peregrinus, 1980.

About the AuthorThomas H. Lee received the S.B., S.M.and Sc.D. degrees in electrical engi-neering, all from the MassachusettsInstitute of Technology in 1983, 1985,and 1990, respectively.

He joined Analog Devices in 1990where he was primarily engaged in

the design of high-speed clock recovery devices. In1992, he joined Rambus Inc. in Mountain View, CAwhere he developed high-speed analog circuitry for500 megabyte/s CMOS DRAMs.

He has also contributed to the development ofPLLs in the StrongARM, Alpha and AMD K6/K7/K8microprocessors. Since 1994, he has been a Profes-sor of Electrical Engineering at Stanford Universitywhere his research focus has been on gigahertz-speed wireline and wireless integrated circuits builtin conventional silicon technologies, particularlyCMOS.

He has twice received the “Best Paper” award atthe ISSCC, co-authored a “Best Student Paper” atISSCC, was awarded the Best Paper prize at CICC, andis a Packard Foundation Fellowship recipient.

He is an IEEE Distinguished Lecturer of both theSolid-State Circuits and Microwave Theory and Tech-nology Societies. He holds 43 U.S. patents andauthored “The Design of CMOS Radio-FrequencyIntegrated Circuits” (now in its second edition), and“Planar Microwave Engineering”, both with Cam-bridge University Press. He is a co-author of fouradditional books on RF circuit design. He is a founderof Matrix Semiconductor (now part of Sandisk) andZeroG Wireless.




In mid-December 1947 John Bardeen and WalterBrattain, physicists at Bell Telephone Laboratoriesin Murray Hill, New Jersey, solved a problem that

had been vexing their boss William Shockley for near-ly a decade. They succeeded in making a solid-stateamplifier from germanium. A close cousin of silicon,this semiconductor element had been employed incrystal rectifiers at the heart of radar receivers duringWorld War II. Bardeen and Brattain’s revolutionarydevice consisted of two closely spaced metal pointspressing onto a thin sliver of high-purity germaniumabout the size of a small fingernail, to the back ofwhich was attached a third lead. A positive bias of afew volts on one point dramatically increased theconductivity just beneath the other one, boosting thecurrent through it by almost a hundredfold.

On the afternoon of December 23, Bardeen andBrattain were scheduled to demonstrate their promis-ing new electronic device to executives at Bell Labs.Soft-spoken and cerebral, Bardeen had come up withthe key ideas for this gizmo, which Brattain quicklyand skillfully implemented. Working shoulder-to-shoulder for most of the prior month, day after dayexcept on Sundays, they had finally gotten their RubeGoldberg contraption to work as intended. [Riordanand Hoddeson, 1997b; Hoddeson and Daitch, 2001]

That morning, while Bardeen completed a few cal-culations, Brattain was in his laboratory making last-minute checks. Around one edge of a triangular plasticwedge, he had glued a small strip of gold foil, which hecarefully slit along this edge with a razor blade. He thenpressed both wedge and foil down into the steel-greygermanium surface with a makeshift spring fashionedfrom a heavy-duty paper clip. Barely an inch high, thisdelicate device was clamped clumsily together by a U-shaped piece of plastic resting upright on one of its twoarms. Two copper wires soldered to edges of the foilsnaked off to batteries, transformers, an oscilloscope,and other equipment needed to power the device andassess its performance. [Brattain, 1968, 1976; Hoddeson,1981; Riordan and Hoddeson, 1997b, pp. 115–141]

Shortly after lunch, Bardeen joined Brattain in his lab-oratory. Shockley arrived about ten minutes later, accom-panied by the department head, acoustics expert HarveyFletcher, and research director Ralph Bown. After a fewwords of explanation, Brattain powered up the equip-ment. The others watched the luminous spot racingacross the oscilloscope screen jump and fall abruptly as

he switched the odd-looking device in and out of the cir-cuit using a toggle switch. From the height of the jump,they could easily tell it was amplifying the input signalmany times when it was included in the loop. And yetthere wasn’t a single vacuum tube in the entire circuit!

Then, borrowing a page from the Bell historybooks, Brattain mumbled a few impromptu wordsinto a microphone. A sudden look of surprise cameover Bown’s bespectacled face as he reacted to thesound of Brattain’s gravelly voice booming in his earsthrough a pair of headphones. Bown passed them toFletcher, who shook his head in wonder shortly afterputting them on. [Brattain, 1974]

For Bell Labs, it was an archetypal moment. Morethan 70 years earlier, a similar event had occurred inthe attic of a boarding house in Boston, Massachusetts,when Alexander Graham Bell uttered the words, “Mr.Watson, come here! I want you!” [Fagen, 1975, p. 12]

In the following weeks, however, Shockley was tornby conflicting emotions. The invention of the tran-sistor, as Bardeen and Brattain’s solid-state amplifi-

er soon came to be called, had been a “magnificentChristmas present” for his group and especially for BellLabs, which had staunchly supported their program ofbasic research in solid-state physics. But he was cha-grined that he had not had a direct role himself in thiscrucial breakthrough. “My elation with the group’s suc-

Crystal Fire: The Invention, Development andImpact of the TransistorAdapted from Chapter 1 of Crystal Fire: The Birth of the Information Age, by MichaelRiordan and Lillian Hoddeson, published in 1997 by W. W. Norton & Company.

By Michael Riordan, University of California, Santa Cruz and Lillian Hoddeson, University of Illinois, Urbana-Champaign

William Shockley (at lab bench), John Bardeen and WalterBrattain, the physicists who invented the first transistors.They shared the 1956 Nobel Prize in Physics for this work.

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TECHNICAL LITERATUREcess was tempered by not being one of the inventors,”he wrote 25 years later. “I experienced frustration thatmy personal efforts, started more than eight yearsbefore, had not resulted in a significant inventive con-tribution of my own.” [Shockley, 1976, p. 612]

Shockley had been hired in 1936 by Mervin Kelly,then Bell Labs research director, specifically to applyhis expertise in solid-state physics to the invention ofnew electronic devices. Having previously served asthe director of vacuum-tube development, Kelly rec-ognized the limitations of these bulky, power-hungrydevices and of the balky electromechanical switchesin the Bell Telephone System. And he could foreseethat solid-state devices might provide much better andmore reliable alternatives. With Kelly’s blessing,Shockley began searching for ways to fashion ruggednew solid-state devices that could amplify and switchelectrical signals. His familiarity with the quantummechanics of solids gave him a decided advantage inthis quest. In late 1939 he thought he had come upwith a good idea and built a crude gizmo with Brat-tain’s help, but it proved a complete failure. [Hodde-son, 1980; Shockley, 1974, 1976]

Far better insight into the subtleties of solids wasneeded — and much purer semiconductor materials,too. World War II interrupted Shockley’s efforts, butthe advances stimulated by wartime research anddevelopment set the stage for major breakthroughs inelectronics and communications once the war ended.Stepping in as Bell Labs Vice President, Kelly recog-nized these opportunities and organized a solid-statephysics group, installing his ambitious protegé as oneof its two leaders. [Hoddeson, 1981; Riordan andHoddeson, 1997a; 1997b, pp. 115-122]

Soon after returning to the Labs in early 1945,Shockley came up with yet another design for a semi-

conductor amplifier, what is now known as a field-effect transistor. But again, it didn’t work when Brat-tain and others fabricated and tested a few such pro-totype devices using silicon. And Shockley couldn’tunderstand why. Discouraged, he turned to otherprojects, leaving to Bardeen and Brattain the task offiguring out why it had failed. In the course of thisresearch, they stumbled upon a completely different— and successful — way to make a solid-state ampli-fier. [Shockley, 1976]

Their invention quickly spurred their headstrongboss into a bout of feverish activity. Galled that he hadbeen upstaged by members of his own group, in whatwas obviously a landmark discovery worthy of a NobelPrize, Shockley could think of little else besides semi-conductors for the next month. He spent almost everyfree moment trying to design a better solid-state ampli-fier that would be a lot easier to manufacture and use.[Riordan and Hoddeson, 1997b, pp. 142–151; 1997c]

By late January 1948 Shockley had figured out theimportant details of his own design. His approachwould use a three-layer sandwich of semiconductormaterial — silicon or germanium — with wires attachedat each end and in the middle, to an inner “base” layer.He eliminated the two fragile “point contacts” ofBardeen and Brattain’s unwieldy contraption, whichwould make manufacturing difficult and lead to quirkyperformance. Based on the boundaries or “junctions”between the layers, to be established within the semi-conductor material itself, his amplifier should be mucheasier to mass-produce and far more reliable. [Ibid.]

It still took more than two years before other Bellresearchers perfected the techniques needed to growultrahigh-purity germanium crystals with just the rightcharacteristics to act as transistors and amplify electri-cal signals. On the 4th of July, 1951, Bell Labsannounced the production of the first “bipolar junctiontransistors,” which had been successfully fabricated bychemists Morgan Sparks and Gordon Teal based onShockley’s designs. [Teal, 1976; Goldstein, 1993]

But it was awhile before these junction transistorscould be produced in quantity. Meanwhile, a crackteam of Bell Labs engineers led by Jack Morton forgedahead with development of point-contact transistorsbased on Bardeen and Brattain’s ungainly invention,for which the two physicists were awarded a patentin 1950. By the middle of that decade, millions of dol-lars worth of new equipment based on these deviceswas about to enter the Bell System. And in 1956Bardeen, Brattain and Shockley received the NobelPrize in physics for their invention of the transistor.[Riordan and Hoddeson, 1997b, pp. 168–194]

By the mid-1950s physicists and electrical engi-neers may have recognized the significance ofthis invention, but the general public was still

mostly oblivious to it. Millions of radios, television

The first, point-contact transistor invented by JohnBardeen and Walter Brattain in December 1947.

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sets and other electronic devices were producedevery year by such giants of American industry asGeneral Electric, RCA and Sylvania, but they came inlarge, cumbersome boxes powered by balky vacuumtubes that took a minute or so to warm up before any-thing else could happen. In 1954 the transistor waswidely perceived to be an expensive laboratorycuriosity with a few specialized applications, such asin hearing aids and military communications.

That year things started to change dramatically,however. A small, innovative company in Dallasbegan producing germanium junction transistors for aportable radio, which hit U.S. stores in October at$49.95. Texas Instruments abandoned this market,only to watch it be cornered by a little-known Japan-ese company that called itself SONY. Transistor radiosyou could carry around in your shirt pocket rapidlybecame a status symbol for teenagers in the suburbsthat were sprawling across the American landscape.And after SONY started manufacturing television setspowered by transistors in the early 1960s, U.S. lead-ership in consumer electronics began to be seriouslythreatened. {Riordan and Hoddeson, 1997b, pp.195–224; Morita, 1986]

Bell Labs and Texas Instruments had already turnedtheir R&D backs on germanium to focus researchefforts on the much more promising but challengingsemiconductor element silicon. With a bigger energygap (1.1 electron volts for silicon versus 0.67 eV forgermanium) between its valence and conductionbands, silicon made far better electronic switches withalmost no leakage current in the “off” condition. Andthey continued to amplify signals reliably at high tem-perature, while germanium quit working above about75°C. But molten silicon reacts with just about every-thing it comes in contact with, which made it far moredifficult to purify and grow large crystals from it. Theseproblems began to be solved in 1954, when Bell Labsand Texas Instruments fabricated the first successfulsilicon transistors. The following year Bell Labschemist Morris Tanenbaum fashioned the first siliconjunction transistor using diffusion of trace impurities togrow ultra-thin base layers hardly a micrometer thick.Such transistors can operate at high frequencies above100 MHz, as used in FM radio and television broad-casting. A new semiconductor industry based on sili-con instead of germanium was about to emerge. [Rior-dan, 1998, 2005J; Tanenbaum and Thomas, 1956]

Vast fortunes would eventually be made in a serenevalley south of San Francisco then full of apricotorchards. Dissatisfied with his lack of advancementand eager to profit from this research, Shockley leftBell Labs in 1955 for California. Intent on making mil-lions, he founded the very first semiconductor com-pany in the San Francisco Bay area. He lured top-notch scientists and engineers to the valley, ambitious

men like himself who two years later jumped ship tostart their own firm, the Fairchild Semiconductor Cor-poration. What eventually became famous around theworld as Silicon Valley had begun with ShockleySemiconductor Laboratory, which could trace its ownroots directly back to Bell Labs. [Riordan and Hodde-son, 1997b, pp. 224–253; 1997d]

But it was Texas Instruments and Fairchild Semi-conductor that took the next giant steps in the histo-ry of the semiconductor industry. Using diffusiontechnology pioneered by Bell Labs, electrical engineerJack Kilby figured out how to fabricate the world’sfirst integrated circuit at Texas Instruments in 1958.Like Bardeen and Brattain’s clumsy point-contact tran-sistor, his first device was a delicate prototype; it useddiffused junctions in a single chip of germanium.Prodded by physicists Jean Hoerni, Robert Noyce andJay Last, Fairchild took the lead in silicon, getting thefirst successful integrated circuits to market. Itsapproach used the far superior “planar” processingtechnique conceived by Hoerni, in which impuritiesare diffused into the silicon from a single side of thewafer, and the resulting junctions are protected by aglassy layer of silicon dioxide. Noyce figured out howto employ this technique in making integrated cir-cuits, and Last headed the development team that suc-ceeded in producing them by early 1961. [Kilby, 1976;LeCuyer, 2006, pp. 127–167]

Use of the silicon dioxide layer to protect and pat-tern the semiconductor material beneath it had beendiscovered in 1955 and pioneered by two Bell Labschemists, Carl Frosch and Link Derick, who publishedtheir work in 1957. But the Labs did not pursue theuse of this technique in making integrated circuits,largely because Morton and other engineers thoughtyields would be unacceptably low. So it took “out-siders” at Sun Belt companies to make the big leapinto IC production. [Riordan and Hoddeson, 1997d;Riordan, 2006]

In 1960 M. M. Atalla and Dawon Khang succeededin using the oxide layer to fashion the first successfulfield-effect transistor at Bell Labs. Their basic structurewas strikingly reminiscent of the one Shockley hadconceived 15 years earlier, to which Bardeen latercontributed major ideas. Voltage on a thin metal strip(called the “gate”) above the oxide layer modulatedthe current flowing in a semiconductor channelbeneath it, from the “source” to the “drain.” This struc-ture soon became known as the metal-oxide-semi-conductor, or MOS, transistor (also as the MOSFET,for MOS field-effect transistor). Because of its initiallypoor reliability and far lower frequency response, BellLabs did not pursue MOS technology further in 1961,and cast its lot initially with bipolar junction transis-tors. This left the door wide open to RCA andFairchild, which perceived the potential this technol-



TECHNICAL LITERATUREogy held for making microchips densely packed withcomponents. By the time Bell Labs returned to MOStechnology in the late 1960s, Fairchild researchers hadsolved its difficult problems, and the company had acommanding lead. [Bassett, 2002, pp. 22–56]

The transistor has indeed proved to be whatShockley in 1949 called the “nerve cell” of theelectronic computers that were just then

emerging. [Shockley, 1949] And he made this com-ment at a time when the only working transistors hadtwo tungsten contacts sticking into a germanium sliv-er! Today, almost no electronic equipment can bemade without transistors, more than 99 percent ofwhich are MOS transistors. Millions and even billionsof them are routinely packed with other microscopicspecks onto chips that control everything from toysand cell phones to automobiles, aircraft and super-computers, serving as the binary “on-off” switches indigital logic. Bipolar junction transistors have largelybeen relegated to the roles of amplifying signals andboosting power levels.

The initial impact of transistors came in portableelectronics. During the mid-1950s, they began to beused extensively in hearing aids and transistor radios,which liberated music and contributed to the explo-sion of rock-and-roll over the following decade. Wal-ter Brattain often marveled about the use of transistorradios by African tribesmen, but railed at the raucousnoise they produced. By 1961 transistors were thefoundation of a billion-dollar semiconductor industrywhose sales were almost doubling annually, findingnew applications every year in consumer electronics,computers, and military hardware.

It took the invention and development of themicrochip, however, to realize the full potential of thisrevolutionary electronic device to utterly change mod-ern life. Computers had been built using transistorssince the mid-1950s, but that feat still involved sol-dering together thousands of discrete components.With the advent of the microchip in the 1960s, thiscould be done on a single silicon chip using what wasessentially a printing process. Early microchips quick-ly found application in the Minuteman intercontinen-tal ballistic missile and the Apollo guidance system,where every ounce came at a premium.

By 1965, when Gordon Moore published hisfamous article in Electronics establishing whatbecame known as “Moore’s Law,” they were begin-ning be used in CDC and IBM computers aimed at theacademic, business and government markets. [Moore,1965] Three decades later, as the transistor was near-ing fifty, he observed that there were more of themmade every year than raindrops falling on California.And more recently, he claims that the number of tran-sistors produced annually exceeds the number ofcharacters printed in all publications the world over!

Today the computing power that had oncerequired rooms full of bulky, fault-prone electronicequipment is easily loaded into sturdy, reliable unitsthat sit on desktops, are lugged around in briefcasesand can even sit in the palm of one’s hand. Words,numbers, sounds and images flash around the globevia transistor-powered satellites, fiber-optic networks,cell phones and fax machines. Teen-agers swap pho-tographs over the Internet, play video games onXboxes, and carry many albums worth of musicaround on iPods. Unusual new terms such as “togoogle” and “podcast” have become part of everydaylanguage.

Through their landmark efforts, Bardeen, Brattainand Shockley had struck the first glowing sparks of atremendous technological fire, which has raged eversince and shows no signs of abating. Cheap, portable,reliable electronic equipment based on transistors isnow found in almost every town, village and hamlet.This tiny invention has made the world far smallerand more intimate than ever before, bringing everycorner of the globe into almost instantaneous contact.

Nations that embraced the new information tech-nologies based upon the transistor have flourished,while one that did not has collapsed. China, Japan,South Korea and Taiwan increasingly set communica-tions standards, manufacturing much of the electron-ic equipment. Television signals penetrate a growingfraction of the globe via communications satellite,while financial transactions occur via veritable riversof ones and zeroes flashing through electronic net-works all over the world.

The dystopian society envisioned by GeorgeOrwell in the aftermath of World War II, at about thesame time the transistor was invented, has complete-ly failed to materialize—in large part because transis-torized electronic devices have empowered creativeindividuals and nimble entrepreneurs far more thanBig Brother. A man or woman today can easily pur-chase the computing and communications power thatonly governments, armed forces or major companiescould afford in that gloomy postwar decade, whenvacuum tubes dominated electronics and two super-powers braced for nuclear war.

The birth of an artifact of such tremendous signifi-cance had gone largely unnoticed amidst the clamorof worldly events, until its impacts became thorough-ly woven throughout the fabric of global society andculture. In the sixty years since then, the transistor hasessentially redefined the very meaning of power,which is today based more upon the control andexchange of information than on iron or oil. At thethrobbing heart of this global transformation is thetiny solid-state device invented by Bardeen, Brattainand Shockley. The raging crystal fire they ignited hasradically reshaped the world and the way we now goabout our daily lives.




ReferencesBassett, Ross Knox, 2002. To the Digital Age:

Research Labs, Start-Up Companies, and the Riseof MOS Technology. Baltimore, MD: Johns Hop-kins University Press.

Brattain, W., 1964. Interview by A. N. Holden andW. J. King, January, American Institute of Physicsarchives (AIP).

, 1968. “Genesis of the Transistor.” The PhysicsTeacher, March, pp. 109–114.

, 1974. Interview by Charles Weiner, 28May, AIP.

, 1976. “Walter Brattain: A Scientific Autobiog-raphy.” Adventures in Experimental Physics 5, pp.29–31.

Fagen, M. D., ed., 1975. A History of Science andEngineering in the Bell System: The Early Years(1875-1925). Murray Hill, NJ: Bell Telephone Lab-oratories.

Goldstein, Andrew, 1993. “Finding the Right Materi-al: Gordon Teal as Inventor and Manager.” InFrederik Nebeker, ed., Sparks of Genius: Portraitsof Electrical Engineering Excellence. NewBrunswick, NJ: IEEE Press, pp. 93–126.

Hoddeson, Lillian, 1980. “The Entry of the QuantumTheory of Solids into the Bell Telephone Labora-tories, 1925–40.” Minerva 18:3, pp. 422–447.

, 1981. “The Discovery of the Point-ContactTransistor.” Historical Studies in the Physical Sci-ences 12:1, pp. 43–76.

Hoddeson, Lillian and Vicki Daitch, 2001. TrueGenius: The Life and Science of John Bardeen.Washington, DC: Joseph Henry Press.

Kilby, Jack, 1976. “Invention of the Integrated Cir-cuit.” IEEE Transactions on Electron DevicesED–23:7, July, pp. 648–54.

LeCuyer, Christophe, 2006. Making Silicon Valley:Innovation and the Growth of High-Tech,1930–1970. Cambridge, MA: The MIT Press.

Morita, Akio, 1986. Made in Japan: Akio Morita andSONY. New York: E. P. Dutton.

Moore, Gordon E., 1965. “Cramming More Compo-nents onto Integrated Circuits.” Electronics, 19April, pp. 114–17.

Riordan, Michael, 1998. “The Road to Silicon WasPaved with Germanium.” In H. R. Huff et al.,eds., Semiconductor/Silicon Pennington, NJ: TheElectrochemical Society, pp. 99–108.

, 2005. “The Lost History of the Transistor,”IEEE Spectrum, May, pp. 44-49.

, 2006. “How Bell Labs Missed the Microchip.” IEEESpectrum, December, pp. 36–41.

Riordan, Michael and Lillian Hoddeson, 1997a. “TheOrigins of the p-n Junction,” IEEE Spectrum, June,pp. 42–47.

, 1997b. Crystal Fire: The Birth of the Informa-

tion Age. New York: W. W. Norton & Company., 1997c. “Minority Carriers and the First Two

Transistors,” In A. Goldstein and W. Aspray, eds.,Facets: New Perspectives on the History of Semi-conductors. New Brunswick, NJ: IEEE Center forthe History of Electrical Engineering, pp. 1–33.

, 1997d. “The Moses of Silicon Valley,” PhysicsToday, December, pp. 46–51.

Shockley, William, 1949. Text of interview titled “TheTransistor,” on radio station WGYN, Schenectady,NY, 21 December, Shockley Papers, StanfordArchives.

, 1974. Interview by Lillian Hoddeson, 10September, AIP.

, 1976. “The Path to the Conception of theJunction Transistor.” IEEE Transactions on Elec-tron Devices ED–23:7, July, pp. 597–620.

Tanenbaum, M. and D. E. Thomas, 1956. “DiffusedEmitter and Base Silicon Transistors.” Bell SystemTechnical Journal 35, pp. 1–22.

Teal, Gordon K., 1976. “Single Crystals of Germani-um and Silicon—Basic to the Transistor and Inte-grated Circuit.” IEEE Transactions on ElectronDevices, ED–23:7, July, pp. 621–39.

About the AuthorsMichael Riordan serves as Lecturer inthe History Department at StanfordUniversity and as Adjunct Professorof Physics at the University of Cali-fornia, Santa Cruz, where he teachesthe history of physics and technolo-gy. He is author of The Hunting of

the Quark: A True Story of Modern Physics (Simon& Schuster, 1987), for which he won the 1988 Sci-ence Writing Award of the American Institute ofPhysics (AIP). He is also coauthor of The SolarHome Book: Heating, Cooling and Designing withthe Sun (Cheshire Books, 1977), The Shadows ofCreation: Dark Matter and the Structure of the Uni-verse (W. H. Freeman, 1991), and Crystal Fire: TheBirth of the Information Age (W.W. Norton, 1997)— for which he shared (with Lillian Hoddeson) the1998 Sally Hacker Prize of the Society for the His-tory of Technology.

Riordan has published many articles, essays andreviews in The New York Times, The Los AngelesTimes, San Francisco Chronicle and WashingtonPost, as well as in New Scientist, Physics Today, Sci-ence, Scientific American and Technology Review.He has written extensively about the history ofsemiconductor devices in IEEE Spectrum and otherperiodicals.

Riordan is a Guggenheim Fellow and a Fellowof the American Physical Society. In 2002 hereceived the AIP’s prestigious Andrew W. Gemant



TECHNICAL LITERATUREAward in recognition of his many efforts commu-nicating physics and its relationship to the widerculture.

Lillian Hoddeson is an historian oftwentieth-century science and technol-ogy. As a Professor of History at theUniversity of Illinois at Urbana-Cham-paign, she teaches courses on the his-tory of science and technology, oralhistory, and memory. She is author or

editor of eight books and over 50 articles in the his-tory of science or technology.

Her general book with Michael Riordan on the his-tory of the transistor (Crystal Fire: the Birth of theInformation Age, 1997) won the first Sally Hacker prizeof the Society for the History of Technology for the bestbook on technology aimed at popular as well as aca-demic audiences. Her biography of John Bardeen(True Genius: the Life and Science of John Bardeen,

2002, coauthored with Vicki Daitch) was recognized asone of the best intellectual reads of 2002 by the TimesHigher Education Supplement, and it was the “SilverWinner 2002 For Biography” in ForeWard Magazine’sBook of the Year Awards. She is presently at work onfive other books. A history of “megascience,” as itevolved at Fermilab, coauthored with Adrienne Kolband Catherine Westfall, is in press with the Universityof Chicago Press. In preparation are: a biography of anindependent American inventor of alternative energytechnologies, a monograph on oral history and humanmemory, a books of essays on memory and the con-struction of identity and culture, and, with MichaelRiordan and Adrienne Kolb, a history of the discontin-ued Superconducting SuperCollider.

Hoddeson’s professional honors include: Fellow ofthe American Physical Society, Fellow of the Centerfor Advanced Study at the University of Illinois; andFellow of the John Simon Guggenheim MemorialFoundation.

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PATENTS


Semiconductor Amplifier Patent

W. SHOCKLEY

Publisher Item Identifier S 0018-9219(98)01000-7.

34 PROCEEDINGS OF THE IEEE, VOL. 86, NO. 1, JANUARY 1998



PATENTS

SHOCKLEY: SEMICONDUCTOR AMPLIFIER PATENT 35


PATENTS



PATENTS


This invention relates to electrical circuit structuresincorporating semiconductor devices. Its principalobjects are these: to provide improved device-and-lead structures for making electrical connections tothe various semiconductor regions; to make unitarycircuit structures more compact and more easily fab-ricated in small sizes than has heretofore been feasi-ble; and to facilitate the inclusion of numerous semi-conductor devices within a single body of material.

In brief, the present invention utilizes dished junc-tions extending to the surface of a body of extrinsicsemiconductor, an insulating surface layer consistingessentially of oxide of the same semiconductorextending across the junctions, and leads in the formof vacuum-deposited or otherwise formed metal stripsextending over and adherent to the insulating oxidelayer for making electrical connections to andbetween various regions of the semiconductor bodywithout shorting the junctions.

The invention may be better understood from thefollowing illustrative description and the accompany-ing drawings.

Figure 1 of the drawings is a greatly enlarged planview of a transistor-and-lead structure embodyingprinciples of this invention;

Figure 2 is a section taken along the line 2—2 ofFigure 1;

Figure 3 is a greatly enlarged plan view of a multi-device semiconductor-and-lead structure embodyingprinciples of this invention;

Figure 4 is a section taken along the line 4—4 ofFigure 3;

Figure 5 is a simplified equivalent circuit of thestructure shown in Figures 3 and 4, with additionalcircuit elements external to said structure representedby broken lines;

Figure 6 is a greatly enlarged plan view of anothertransistor-and-lead structure embodying principles ofthe invention;

Figure 7 is a section taken along the line 7—7 ofFigure 6.

Figures 1 and 2 illustrate one example of a struc-ture according to this invention. A single-crystal bodyof semiconductor-grade silicon, represented at 1, hasa high-quality surface 2, prepared in accordance withknown transistor technology. Within the body 1 thereare high-resistivity regions, designated I in the draw-ing, composed either of high-purity silicon having sofew donor and acceptor impurities that it is a goodinsulator at ordinary temperatures and an intrinsicsemiconductor at elevated temperatures, or of some-

what less-pure silicon containing a trace of a materialsuch as gold that diminishes the effect of donor andacceptor impurities by greatly reducing the carrierconcentrations.

Elsewhere within body 1, there are extrinsic N-typeand extrinsic P-type regions, designated N and Prespectively, formed in the well-known manner bydiffusing N-type and P-type dopants through surface2 into the crystal, with appropriate masking to limitthe dopant to the desired areas. The smallest anduppermost N-type region constitutes an emitter layerof the transistor. This emitter layer overlies a some-what larger P-type region which consitutes the baselayer of the transistor. The base layer, in turn, overliesa still larger N-type region which constitutes the col-lector layer of the transistor. Between the emitter andbase layers there is a dished, P-N junction 3, having acircular edge which extends to surface 2 and therecompletely surrounds the emitter. Between the baseand collector layers there is a dished, P-N junction 4,having a circular edge that extends to surface 2 andthere completely surrounds the base. The thickness ofthe emitter and base layers has been exaggerated inthe drawings: in actual practice each of these layers isbut a few microns thick. The collector layer generallyis considerably thicker, and in the example illustratedextends completely through the body 1 so that con-tact thereto may be made from the back side. Thus,the three extrinsic semiconductor layers describedform a transistor equivalent to previously knowntypes of double-diffused junction transistors.

During diffusion of the donor and acceptor impuri-ties into the semiconductor, at elevated temperaturein an oxidizing atmosphere, the surface of the siliconoxidizes and forms an oxide layer 5, often one micronor more in thickness, congenitally united with andcovering surface 2. This layer may consist chiefly ofsilicon dioxide, or of disproportionated silicon subox-ide, depending upon the temperature and conditionsof formation. In any event, the oxide surface layer isdurable and firmly adherent to the semiconductorbody, and furthermore it is a good electrical insulator.

According to common prior practice in manufac-turing diffused-junction transistors, the semiconductorbody was deoxidized by chemical etching prior todeposition of metal contacts on the semiconductorsurface. According to the present invention, onlyselected portions of the oxide layer are removed, asillustrated in Figures 1 and 2, for example, while otherportions of the oxide layer are left in place to serve asinsulation for electrical leads used in making connec-

Semiconductor Device-and-Lead StructureReprint of U.S. Patent 2,981,877 (Issued April 25, 1961. Filed July 30, 1959)

Robert N. Noyce, Fairchild Semiconductor Corporation



PATENTS

tions to and between the several semiconductorregions.

In particular, portions of the remaining oxide filmextend across the edges of the P-N junctions at thesurface of the semiconductor body, to facilitate themaking of electrical connections from one side of ajunction to another without shorting the junction.Thus, as illustrated in Figures 1 and 2, the remainingoxide film comprises a tongue 5′ that crosses the edgeof junction 4, and another tongue 5′′ that crosses theedges of both junctions 3 and 4. On the other hand,at least a portion of the surface over each of the emit-ter and base layers must be cleared to permit the for-mation of base and emitter contacts.

A convenient and highly accurate way to removeonly selected portions of the oxide film is to use pho-toengraving techniques. The photoengraving resist isplaced over the oxide-coated surface, and this is thenexposed through a master photographic plate havingopaque areas corresponding to the areas from whichthe oxide is to be removed. In the usual photograph-ic developing, the unexposed resist is removed; andchemical etching can then be employed to removethe oxide layer from the unexposed areas, while theexposed and developed resist serves as a mask to pre-vent chemical etching of the oxide areas that are to beleft on the semiconductor surface.

A discoid, metal, emitter contact 6 is adherent tosurface 2, wholly within the edge of junction 3, cen-

tered upon and in electrical connection with the emit-ter region of the transistor. Electrical connections tothis emitter contact are made through a metal strip 7extending over and adherent to oxide layer 5. Thestrip 7 extends over the tongue 5′′ of the insulatingoxide layer across the junctions 3 and 4, and thus pro-vides an electrical connection extending from oneside of the composite structure inward to the centralemitter contact, without shorting any of the transistorjunctions.

The base contact is a C-shaped, metal strip 8,adherent to surface 2 wholly between the edges ofjunctions 3 and 4, substantially concentric with theemitter contact 6 and substantially encircling the junc-tion 3. It will be noted that tongue 5′′ and lead 7extend between the two ends of the C-shaped contact8, so that lead 7 and the emitter contact are effective-ly insulated from the base contact even though thebase contact substantially surrounds the emitter junc-tion. Electrical connection to contact 8 is madethrough a metal strip 9 extending over and adherentto the insulating oxide layer 5. Strip 9 extends overtongue 5′ across the collector junction 4, and thusprovides an electrical connection from one side of thecomposite structure into the base layer, which in thisembodiment is completely surrounded by the collec-tor layer at the surface 2, without shorting the collec-


PATENTS


tor junction 4.Various methods may be employed for forming the

base and emitter contacts and leads. By way of exam-ple, the contacts and leads can be deposited in theconfiguration shown by direct vacuum evaporation ofaluminum, or other suitable contact metal, through amask of suitable size and shape. Alternatively, a metalcoating may be deposited over the entire upper sur-face of the composite structure, and the unwantedmetal then removed by known photoengraving tech-niques to leave only the contact-and-lead configura-tion shown. After the contacts have been depositedupon surface 2 of the semiconductor, the structure isusually heated to form an alloy at the metal-siliconinterface so that good, ohmic contact between themetal and the silicon is obtained.

It will be noted that regions of high-resistivity sili-con are made to underlie portions of the leads 7 and9. The principal purpose in this is to reduce the shuntcapacitance between the leads and the semiconductorbody. Otherwise, an undesirably high shunt capaci-tance may exist in some cases since the extrinsicsemiconductor regions are fairly good conductors,and the insulating layer 5 has a thickness of only oneto two microns. The high-resistivity regions act essen-tially as insulators rather than as conductors, and thusreduce the area of closely spaced conductors that leadto high shunt capacitances. Of course, in cases wherethe shunt capacitance is not excessive for the purpos-es desired, use of high-resistivity regions as disclosedis not required.

The transistor structure is completed by an electri-cal contact to the collector layer, which may take theform of a metal coating 10 plated over the entire backside of the silicon body.

Even in a single transistor, as illustrated in Figures1 and 2, the composite semiconductor-and-leadstructure provided by this invention has significantadvantages. According to prior practice, electricalconnection to the base and emitter contacts had to bemade by fastening wires directly to the contact areas.This led to certain manufacturing difficulties, particu-larly in the case of small devices wherein, for exam-

ple, the emitter region might be only a few mils indiameter and a few microns in thickness. Merely toposition the emitter lead on the emitter contact insuch small structures required the use of microscopesand micro-manipulators; and the use of any consid-erable pressure or considerable heat in making thejoint permanent could cause sufficient damage todestroy the transistor.

By means of the present invention, the leads 7 and9 can be deposited at the same time and in the samemanner as the contacts themselves. Furthermore,leads 7 and 9 can be made as large as may be desiredat the point where wires or other external circuit ele-ments are to be attached; and such attachments canbe made at a distance from the active elements of thetransistor proper, so that the chances of damage to thetransistor are significantly reduced.

Further advantages accrue when it is desired toincorporate more than one circuit device into a singlebody of semiconductor. In this way exceptionallycompact and rugged circuits can be constructed. Oneexample of such a multi-device structure is illustratedin Figures 3 and 4.

A single-crystal body 11 of silicon, largely P-type,has a high-quality surface 12 prepared in accordancewith well known transistor technology. The other sideof body 11 is plated with a metal coating 13, whichserves as an electrical contact to the largest P-typeregion and as a ground plane for the electrical circuit.Various circuit elements may be formed within and onthis body of silicon. N-type and P-type dopants,restricted to specific areas by known masking tech-niques, are diffused through surface 12 to form a plu-rality of N-type and P-type extrinsic semiconductorregions, separated from the underlying P-type regionand from each other by a plurality of dished, P-Njunctions of various diameters and depths, all having,in this particular example, circular edges extending tosurface 12 and there surrounding the overlying semi-conductor regions.

Toward the left end of the structure illustrated inFigures 3 and 4, there will be found an N-type regionoverlying a small P-type region and separated there-



PATENTSfrom by a dished junction 14. The small P-type regionoverlies another N-type region; and the underlying N-type region in turn overlies the large, grounded P-type region and is separated therefrom by a dishedjunction 15. The junction between the two intermedi-ate layers is shorted by contact 17. Consequently, thisstructure provides two rectifying junctions connectedin series, each equivalent to a crystal diode.

Electrical connection to the upper N-type region ismade through a discoid, metal contact 16, adherent tosurface 12, wholly within junction 14 and substantial-ly centered upon the N-type region. Electrical contactto the two regions between junctions 14 and 15 ismade through a C-shaped metal contact 17, adherentto surface 12, wholly between the edges of junctions14 and 15, concentric with contact 16 and substantial-ly encircling the edge of junction 14, which extendsto the surface 12.

Proceeding toward the right in the drawings, therewill be found another N-type region, separated fromthe underlying, grounded, P-type region by a dishedjunction 18. Electrical connection to the N-type regionin this case is made through a discoid, metal contact19, adherent to surface 12 and substantially centeredinside the edge of junction 18, which extends to thesurface of the semiconductor.

Toward the right end of the structure illustrated,there will be found a small N-type region overlying aP-type region and separated therefrom by a dishedjunction 20. The last-mentioned P-type region in turnoverlies a larger N-type region and is separated there-from by a dished junction 21. The N-type regionbelow junction 21 in turn overlies the grounded P-type region and is separated therefrom by a dishedjunction 22. In this case, the width of the P-typeregion between junctions 20 and 21 is less than a dif-fusion length, so that a substantial proportion of theelectrons that cross junction 20 are collected by junc-tion 21. The result is an N-P-N junction transistor, inwhich the small N-type region overlying junction 20acts as the emitter, the P-type region between junc-tions 20 and 21 acts as the base, and the N-typeregion between junctions 21 and 22 acts as the col-lector. The width of the last-menttioned N-type regionis greater than a diffusion length, and consequentlythere is little interaction between junctions 21 and 22.As will be explained hereinafter, junction 22 is nor-mally reversebiased and acts much as a capacitor inthe overall circuit. It serves the important function ofisolating the collector of the transistor from thegrounded, underlying, P-type region.

Electrical connections to the three active regions ofthe transistor are made as follows: A discoid, metalcontact 23 is adherent to surface 12, wholly within theedge of junction 20, centered upon and in electricalconnection with the emitter layer of the transistor. AC-shaped contact 24 is a metal strip adherent to sur-

face 12 between junctions 20 and 21, substantiallysurrounding the circular edge of junction 20 thatextends to the surface of the semiconductor body.This contact overlies and is in electrical connectionwith the base layer of the transistor. Another and larg-er C-shaped contact 25, which overlies and is in elec-trical connection with the collector layer, is likewise inthe form of a metal strip, adherent to surface 12between junctions 21 and 22, and surrounding the cir-cular edge of collector junction 21 that extends to thesurface.

Still another contact is provided upon and adherentto surface 12. This is the discoid, metal contact 26,directly upon and in electrical connection with thegrounded P-type layer, for the purpose of providing aground terminal at the upper surface of the compos-ite structure.

Except for the contacts described above, the entiresurface 12 is covered with an insulating layer 27 ofoxidized silicon, generally about one micron thick.This insulating layer may be formed upon theexposed surface of the silicon during diffusion of theN-type and P-type dopants into the silicon, at elevat-ed temperatures and in an oxidizing atmosphere. Thepresence of water vapor will enhance oxidation ofthe silicon. Preferably, in accordance with this inven-tion and contrary to prior practice, after diffusion iscompleted the oxide layer is never removed from thesilicon, except for the areas to be covered by thecontacts herein described. The contact areas arecleared by photoengraving, after which the contactmetal can be deposited by various known processes,e.g., by the vacuum deposition of an aluminum filmcovering both the cleared and oxide-coated areas.Afterwards, unwanted metal can be removed fromthe oxide-coated areas by photoengraving. The alu-minum contacts may be alloyed to the silicon tomake ohmic contacts in a known manner.

The circuit structure is completed by providingmetal strips extending over and adherent to the insu-lating oxide layer 27 and making electrical connec-tions to and between the various contacts heretoforedescribed. These metal strips may be deposited byvacuum evaporation and deposition, and may conve-niently be parts of the deposited film from which con-tacts are made. The leads come from portions of thefilm that are deposited onto the oxide film and arethereby insulated from the semiconductor body. Ashereinbefore explained, photoengraving can be usedto remove the unwanted metal, leaving only the leadsand contacts.

In the structure illustrated, there is an input lead 28electrically connected to contact 17, and an outputlead 29 electrically connected to contact 25. A lead 30interconnects contacts 16 and 19; if desired, lead 30can be made sufficiently thin and narrow to have anappreciable resistance, and thereby serve as a resist-


PATENTS


ance element in the circuit. A similar lead 31 inter-connects contacts 19 and 24, and still another lead 32,which may be made to have an appreciable resistanceif desired, interconnects contacts 23 and 26.

The solid lines in Figure 5 represent the simplified,equivalent circuit for the structure shown in Figures 3and 4, while the broken lines in Figure 5 representtypical external circuit components added for purpos-es of explanation. The solid-line parts are identifiedby reference numbers identical to the reference num-bers of corresponding parts in the structure of Figures3 and 4, with the addition of a prime to the referencenumbers in Figure 5.

Any desired source of an amplitude-modulated, A.-C. signal is represented at 34 in Figure 5. This A.-C. signal is applied between the input lead 28′ andthe ground, connection 13′, corresponding to lead 28and ground plane 13 of the physical structure shownin Figures 3 and 4. Lead 28 conducts the signalthrough contact 17 into the two layers between junc-tions 14 and 15. As hereinbefore explained, each ofthe junctions 14 and 15 performs essentially the func-tions of a crystal diode rectifier, as schematically rep-resented at 14′ and 15′, Figure 5.

Thus, as is evident from the equivalent circuitshown in Figure 5, the input signal is rectified ordetected by the junctions 14 and 15, to provide atcontact 16 a signal essentially corresponding to themodulation envelope of the input signal. Because ofits appreciable resistance, lead 30 acts as a circuitresistor, represented in Figure 5 as 30′. It will be notedthat the polarity of rectifying junctions 14 and 15 issuch that the signal supplied to contact 19 has a D.-C. component of the polarity required to reverse-biasjunction 18. Hence, the voltage across junction 18 isalways in the high-resistance direction of the junction,and there is no appreciable current flow across thisjunction. However, there are charge layers on bothsides of the junction which form a capacitance, as iswell known, and therefore the circuit function of junc-tion 18 is to provide a capacitance, represented inFigure 5 at 18′. The value of this capacitance can bemade greater or less, as desired, by increasing ordecreasing the area of junction 18.

Lead 31 has an appreciable resistance and thereforeacts as a circuit resistor, represented at 31′, Figure 5.This leads to the base contact 24 of the transistor,shown at 24′ in Figure 5. The emitter contact of thetransistor is connected through lead 32 and contact 26to the grounded P-type semiconductor region. This isrepresented in Figure 5 by the emitter terminal 23′

connected through resistor 32′ to the ground line 13′.The value of the resistor 32′ is the sum of the resist-ances of contacts 23 and 26, lead 32, and the currentpath through the P-type layer between contact 26 andground plane 13.

Normal operation of the N-P-N transistor requiresthat the N-type collector be supplied with a relativelypositive voltage, as is accomplished in the equivalentcircuit illustrated in Figure 5 by the external voltagesupply 36 connected to the collector terminal 25′

through any appropriate load 35. It is evident that thissupply voltage reverse-biases junction 22, and there-fore, for reasons already explained, the junction 22acts essentially as a capacitor, represented at 22′ of theequivalent circuit shown in Figure 5.

It should now be apparent that the structure shownin Figures 3 and 4 comprises, within a single, rugged,compact unit, detector, filtering, and transistor-ampli-fier stages. It is believed to be evident that the princi-ples of this invention make feasible the constructionof an endless variety of circuit combinations, includ-ing combinations much more elaborate and complexthan the simple circuit employed for purposes of illus-tration, all within a highly compact and rugged,essentially unitary, solid body.

Figures 6 and 7 show an example in which theemitter and base contacts are parallel strips. A single-crystal body 37 of silicon contains a P-type, emitterlayer overlying an N-type, base layer and separatedtherefrom by a dished junction 38, which extends tothe upper surface of the semiconductor and there sur-rounds the P-type, emitter layer. In this case, the edgeof junction 38 does not form a circle at the surface,but forms an elongated, closed figure. The N-type,base layer overlies a P-type, collector layer and is sep-arated therefrom by a flat junction 39.

The emitter contact 40 is a straight strip of metal,vacuum-deposited or otherwise placed upon theupper surface of the silicon, and preferably alloyedthereto to form an ohmic contact. The base contact 41is a similar strip of metal, parallel to contact 40. Theedge of junction 38 extends between the two con-tacts, and around contact 40, as shown. The collectorcontact 42 may be a metal layer plated onto the bot-tom surface of the silicon.

Except for the areas covered by contacts 40 and41, the upper surface of the silicon is covered by aninsulating oxide layer, congenitally united with thesilicon and actually formed by heating the silicon inan oxidizing atmosphere. The oxide layer complete-ly covers the edge of junction 38, and protects thejunction against accidental shorting in addition toproviding insulation between the electrical leads andthe silicon.

Electrical connection to contact 40 is made by ametal strip 43, extending over and firmly adherent tothe oxide layer. Electrical connection to contact 41 ismade by a metal strip 44, similarly extending over andfirmly adherent to the oxide layer. These metal stripscan be formed by vacuum deposition through a mask,or by plating the entire surface and then removing



PATENTSunwanted metal by photoengraving, or by any othermethod providing metal strips that adhere securely tothe oxide surface.

The invention in its broader aspects is not limitedto the specific examples illustrated and described.What is claimed is:1. A semiconductor device comprising a body of

semiconductor having a surface, said body con-taining adjacent P-type and N-type regions with ajunction therebetween extending to said surface,two closely spaced contacts a adherent to said sur-face upon opposite sides of and adjacent to oneportion of said junction, an insulating layer con-sisting essentially of oxide of said semiconductoron and adherent to said surface, said layer extend-ing across a different portion of said junction, andan electrical connection to one of said contactscomprising a conductor adherent to said layer,said conductor extending from said one contactover said layer across said different portion of thejunction, thereby providing electrical connectionsto both of the closely spaced contacts.

2. A semiconductor device comprising a body ofextrinsic semiconductor having a surface, saidbody containing adjacent P-type and N-typeregions, one overlying the other, with a junctiontherebetween extending to said surface and therecompletely encircling said overlying region, theunderlying one of said regions extending to saidsurface and there surrounding said junction, a firstmetal contact adherent to said surface in ohmicelectrical connection with said overlying region,an insulating layer consisting essentially of oxideof said semiconductor united with said surfaceand extending across said junction, a metal stripadherent to said layer, said strip being electricallyconnected to said first contact and extendingtherefrom over said layer across said junction, anda second metal contact adherent to said surface inohmic electrical connection with said underlyingregion, said second contact substantially encir-cling said junction from one side of said strip tothe other.

3. A semiconductor device comprising a body ofextrinsic semiconductor having a surface, saidbody containing adjacent P-type and N-typeregions with a dished junction therebetween hav-ing a substantially circular edge at said surface, adiscoid metal contact adherent to said surfacewholly within and substantially concentric withsaid edge, a C-shaped metal contact adherent tosaid surface and substantially concentric with saiddiscoid contact, said C-shaped contact being whol-ly outside of and substantially encircling said edge,said C-shaped contact having two ends defining agap there-between, an insulating layer consistingof oxide of said semiconductor on said surface

extending through said gap and across said junc-tion, and a metal strip over and adherent to saidlayer extending through said gap and across saidjunction to said discoid contact, said contacts beingin direct electrical connection with respective onesof said regions, and said metal strip being in directelectrical connection with said discoid contact butspaced and insulated from the ends of said C-shaped contact.

4. A diffused junction transistor comprising a body ofextrinsic silicon having a surface, said body contain-ing adjacent base and emitter regions, with a discoidemitter junction therebetween having a substantiallycircular edge at said surface encircling said emitterregion, a discoid metal contact to said emitter regionadherent to said surface wholly within said edge, a C-shaped metal contact to said base region adherentto said surface and substantially encircling said edge,said C-shaped contact having two ends defining agap therebetween, an insulating layer of oxidizedsilicon on said surface, said layer being congenitallyunited with said body and extending across saidjunction, and a metal strip adherent to said layer,said strip extending from said discoid contact oversaid layer across said junction and between saidends forming an electrical connection to said emit-ter region.

5. A semiconductor device comprising a single-crys-tal body of semiconductor material having a sur-face, said body containing a high-resistivity regionand extrinsic P-type and extrinsic N-type regionswith a P-N junction therebetween extending tosaid surface, a metal contact to one of said extrin-sic regions adherent to said surface, an insulatinglayer consisting essentially of oxide of said mate-rial on said surface, said layer being congenitallyunited with said body and extending across saidjunction, and an electrical connection to said con-tact comprising a metal strip adherent to saidlayer, said strip extending from said contact oversaid layer across said junction, said high-resistivi-ty region underlying a portion of said strip, reduc-ing the shunt capacitance between said strip andsaid body.

6. A semiconductor device comprising a body ofsemiconductor having a surface, said body con-taining adjacent P-type and N-type regions, oneoverlying the other, with a junction therebetweenextending to said surface, a first metal contactadherent to said surface in electrical connection tosaid overlying region, a second metal contact inelectrical connection with the underlying one ofsaid regions, an insulating layer consisting essen-tially of oxide of said semiconductor on said sur-face, said layer being congenitally united with saidbody and extending across said junction, an elec-trical connection to said first contact comprising a


PATENTS


metal strip adherent to said layer, said stripextending from said first contact over said layeracross said junction, and circuit means for apply-ing between said strip and second contact a D.C.voltage of the polarity that reverse-biases saidjunction, so that said junction acts as a capacitorconnected between said strip and said secondcontact.

7. A semiconductor device comprising a body ofextrinsic semiconductor having a surface, saidbody containing adjacent, first, second and thirdregions, one overlying the other, P-type and N-type alternately, with a first, dished, P-N junctionbetween said first and second regions having anedge extending to said surface and there sur-rounding said first region, and a second, dished,P-N junction between said second and thirdregions extending to said surface and there sur-rounding said second region, a first metal con-tact adherent to said surface in electrical con-nection with said first region, a second metalcontact adherent to said surface in electrical con-nection with said second region, a third metalcontact in electrical connection with said thirdregion, an insulating layer consisting essentiallyof an oxide of said semiconductor on said sur-face, said layer being congenitally united withsaid body and extending across both of saidjunctions, an electrical connection to said firstcontact comprising a first metal strip adherent tosaid layer, said first strip extending from said firstcontact over said layer across both of said junc-tions, and an electrical connection to said sec-ond contact comprising a second metal stripadherent to said layer, said second strip extend-ing from said second contact over said layeracross said second junction.

8. A semiconductor device as in claim 7, whereinsaid second contact is a C-shaped metal strip sub-stantially encircling said first junction, and saidthird contact is a larger C-shaped metal stripadherent to said surface and substantially encir-cling said second junction.

9. A semiconductor device comprising a body ofextrinsic semiconductor having a surface, saidbody containing a plurality of dished, P-N junc-

tions each having an edge extending to said sur-face and there surrounding and defining anenclosed region of said semiconductor, a pluralityof metal contacts adherent to said surface in elec-trical connection with respective ones of saidenclosed regions, an insulating layer consistingessentially of oxide of said semiconductor on saidsurface, said layer being congentially united withsaid body and extending across a plurality of saidjunctions, and electrical interconnections betweensaid contacts comprising metal strips adherent tosaid layer and extending over said layer across aplurality of said junctions.

10. A semiconductor device comprising a body ofextrinsic semiconductor having a surface, saidbody containing adjacent P-type and N-typeregions with a dished junction therebetween, saidjunction having an edge that extends to said sur-face and there forms an elongated, closed figure,first and second contacts in the form of parallelmetal strips adherent to said surface, said first con-tact being wholly within and said second contactwholly without said edge of the junction, an insu-lating layer consisting of oxide of said semicon-ductor on said surface and extending across saidjunction, and a metal strip adherent to said insu-lating layer and extending thereover across saidjunction to connect physically and electricallywith said first contact.

References Cited in the file of this patentUNITED STATES PATENTS

2,813,326 Liebowitz Nov, 19, 19572,836,878 Shepard June 3, 19582,842,723 Koch et al. July 8, 19582,849,664 Beale Aug. 26, 1958

United States Patent Office2,981,877Patented Apr. 25, 1961Semiconductor Device-and-Lead StructureRobert N. Noyce, Los Altos, Calif., assignor toFairchild Semiconductor Corporation, Mountain View,Calif., a corporation of DelawareFiled July 30, 1959, Ser. No. 830,507 10 Claims. (Cl. 317–235)



PATENTS


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PATENTS



PATENTS


This invention relates to miniature electronic circuits,and more particularly to unique integrated electroniccircuits fabricated from semiconductor material.

Many methods and techniques for miniaturizingelectronic circuits have been proposed in the past. Atfirst, most of the effort was spent upon reducing thesize of the components and packing them more close-ly together. Work directed toward reducing compo-nent size is still going on but has nearly reached alimit. Other efforts have been made to reduce the sizeof electronic circuits such as by eliminating the pro-tective coverings from components, by using more orless conventional techniques to form components ona single substrate, and by providing the componentswith a uniform size and shape to permit closer spac-ings in the circuit packaging therefor.

All of these methods and techniques require a verylarge number and variety of operations in fabricatinga complete circuit. For example, of all circuit compo-nents, resistors are usually considered the most sim-ple to form, but when adapted for miniaturization byconventional techniques, fabrication requires at leastthe following steps:

(a) Formation of the substrate.(b) Preparation of the substrate.(c) Application of terminations.(d) Preparation of resistor material.(e) Application of the resistor material.(f) Heat treatment of the resistor material.(g) Protection or stabilization of the resistor.

Capacitors, transistors, and diodes when adaptedfor miniaturization each require at least as many stepsin the fabrication thereof. Unfortunately, many of thesteps required are not compatible. A treatment that isdesirable for the protection of a resistor may damageanother element, such as a capacitor or transistor, andas the size of the complete circuit is reduced, suchconflicting treatments, or interactions, become ofincreasing importance. Interactions may be minimizedby forming the components separately and thenassembling them into a complete package, but thevery act of assembly may cause damage to the moresensitive components.

Because of the large number of operationsrequired, control over miniaturized circuit fabricationbecomes very difficult. To illustrate, many raw mate-rials must be evaluated and controlled even thoughthey may not be well understood. Further, many test-ing operations are required and, even though a high

yield may be obtained for each operation, so manyoperations are required that the over-all yield is oftenquite low. In service, the reliability of a circuit pro-duced by methods of such complexity may also bequite low due to the tremendous number of controlsrequired. Additionally, the separate formation of indi-vidual components requires individual terminationsfor each component. These terminations may eventu-ally become as small as a dot of conductive paint.However, they still account for a large fraction of theusable area or volume of the circuit and may becomean additional cause of circuit failure or rejection dueto misalignment.

In contrast to the approaches to miniaturization thathave been made in the past, the present invention hasresulted from a new and totally different concept forminiaturization. Radically departing from the teach-ings of the art, it is proposed by the invention thatminiaturization can best be attained by use of as fewmaterials and operations as possible. In accordancewith the principles of the invention, the ultimate incircuit miniaturization is attained using only one mate-rial for all circuit elements and a limited number ofcompatible process steps for the production thereof.

The above is accomplished by the present inven-tion by utilizing a body of semiconductor materialexhibiting one type of conductivity, either n-type orp-type, and having formed therein a diffused regionor regions of appropriate conductivity type to form ap-n junction between such region or regions and thesemiconductor body or, as the case may be, betweendiffused regions. According to the principles of thisinvention, all components of an entire electronic cir-cuit are fabricated within the body so characterized byadapting the novel techniques to be described indetail hereinafter. It is to be noted that all componentsof the circuit are integrated into the body of semicon-ductor material and constitute portions thereof.

In a more specific conception of the invention, allcomponents of an electronic circuit are formed in ornear one surface of a relatively thin semiconductorwafer characterized by a diffused p-n junction or junc-tions. Of importance to this invention is the conceptof shaping. This shaping concept makes it possible ina circuit to obtain the necessary isolation betweencomponents and to define the components or, stateddifferently, to limit the area which is utilized for agiven component. Shaping may be accomplished in agiven circuit in one or more of several different ways.These various ways include actual removal of por-tions of the semiconductor material, specialized con-

Miniaturized Electronic CircuitsReprint of U.S. Patent 3,138,743 (Issued June 23, 1964. Filed Feb. 6, 1959)

Jack S. Kilby, Dallas, Tex., assignor to Texas Instruments



PATENTS

figurations of the semiconductor material such as longand narrow, L-shaped, U-shaped, etc., selective con-version of intrinsic semiconductor material by diffu-sion of impurities thereinto to provide low resistivitypaths for current flow, and selectve conversion ofsemiconductor material of one conductivity type toconductivity of the opposite type wherein the p-njunction thereby formed acts as a barrier to currentflow. In any event, the effect of shaping is to directand/or confine paths for current flow thus permittingthe fabrication of circuits which could not otherwisebe obtained in a single wafer of semiconductor mate-rial. As a result, the final circuit is arranged in essen-tially planar form. It is possible to shape the waferduring processing and to produce by diffusion thevarious circuit elements in a desired and proper rela-tionship. Certain of the resistor and capacitor compo-nents described herein have utility and novelty in andof themselves although they are completely adaptableto and perhaps find their greatest utility as integralparts of the semiconductor electronic circuit hereof.

It is, therefore, a principal object of this inventionto provide a novel miniaturized electronic circuit fab-ricated from a body of semiconductor material con-taining a diffused p-n junction wherein all compo-nents of the electronic circuit are completely integrat-ed into the body of semiconductor material.

It is another principal object of this invention toproduce desired circuits by appropriately shaping awafer of semiconductor material to obtain the neces-sary isolation between components thereof and todefine the areas utilized by such components.

It is a further object of this invention to provide aunique miniaturized electronic circuit fabricated asdescribed whereby the resulting electronic circuit willbe substantially smaller, more compact, and simplerthan circuit packages heretofore developed usingknown techniques.

It is a still further object of this invention to providenovel miniaturized electronic circuits fabricated asdescribed above which involve less processing thantechniques heretofore used for this purpose.

It is a primary object of the invention to provide aminiaturized electronic circuit wherein the active andpassive circuit components are integrated within abody of semiconductor material, the junctions of suchcomponents being near and/or extending to one faceof the body, with components being spaced or elec-trically separated from one another as necessary inthe circuit. These features permit a versatility indesign of integrated circuits not heretofore available.

The foregoing and other objects and features of theinvention will become more readily apparent from thefollowing detailed description of preferred embodi-ments of the present invention when taken in con-junction with the appended drawings, in which:

FIGURES l–5a illustrate schematically various circuitcomponents fabricated in accordance with the princi-ples of the present invention in order that they maybe integrated into, or as they constitute parts of, a sin-gle body of semiconductor material;

FIGURE 6a illustrates schematically a multivibratorcircuit fabricated in accordance with the presentinvention;

FIGURE 6b shows the wiring diagram for the mul-tivibrator circuit of FIGURE 6a laid out in the samerelationship;

FIGURE 7 illustrates the wiring diagram of the mul-tivibrator circuit of FIGURE 6a in a more convention-al presentation;

FIGURE 8a illustrates schematically a phase shiftoscillator fabricated in accordance with the principlesof the present invention;

FIGURE 8b shows the wiring diagram for FIGURE 8a with the components laid out in the samerelationship; and

FIGURE 8c portrays the wiring diagram of thephase shift oscillator.

As will be apparent to one skilled in the art, circuitcomponents can be classified according to their cir-cuit functions. Thus, circuit elements may be thoughtof as being active or passive in nature. According to“The Encyclopedic Dictionary of Electronics andNuclear Engineering,” edited by Sarbacher, and pub-lished by Prentice-Hall, active elements are thosewhich in an impedance network act as current gen-erators; whereas passive elements do not so act.Examples of active elements are photocells and tran-sistors; examples of passive elements are resistors,capacitors and inductors. Diodes, while most oftenemployed as passive elements, may if suitably biasedand energized, function in an active capacity. Varac-tor diodes and tunnel diodes are examples of diodesoperating in an active capacity. The term “circuit” (or“network”) means two or more discrete circuit ele-ments electrically connected together; and by “dis-crete circuit element” is meant a resistor, capacitor,inductor, diode, transistor or the like that is formedseparately or purposely as distinguished from exis-tence as a function incidentally, accidentally orinherently as a part of some other circuit element, as,for example, every transistor may be said to exhibitsome resistance and capacitance along with its tran-sistor action.

Referring now to the drawings in detail, preferredembodiments of the present invention will now bedescribed in detail in order that a better understand-ing of the principles of the invention and the variousforms and embodiments of the invention will be bet-ter understood.

As noted previously, the invention is primarily con-


PATENTS


cerned with miniaturization of electronic circuits.Also, as noted, the invention contemplates the use ofa body of semiconductor material appropriatelyshaped, electrically and physically and having formedtherein a p-n junction or junctions and the use ofcomponent designs for the various circuit elements orcomponents which can be integrated into or whichconstitute parts of the aforesaid body of semiconduc-tor material.

FIGURES 1–5 inclusive illustrate in detail circuit ele-ments formed in accordance with the principles ofthis invention which can be integrated into a body ofsemiconductor material. It is noted at this point thatthe body of semiconductor material is of single crys-tal structure, and can be composed of any suitablesemiconductor material. There may be mentioned asexamples of suitable materials germanium, silicon,intermetallic alloys such as gallium arsenide, alu-minum antimonide, indium antimonide, as well asothers.

Referring particularly to FIGURE 1, there is showna typical design for a resistor which may be embod-ied or integrated into a body of single crystal semi-conductor material. As noted in FIGURE 1, the designcontemplates utilizing the bulk resistance of a body10 of semiconductor material of any conductivitytype. Contacts 11 and 12 are made ohmically to onesurface of the body 10, spaced apart a sufficient dis-tance to achieve a desired resistance. As will beapparent to one skilled in the art, ohmic connectionsare those which exhibit symmetry and linearity inresistance to flow of current therethrough in anyavailable direction. If two resistors are to be connect-ed together, it is not necessary to provide separate ter-minations for the common point. The resistance maybe calculated from

R = ρL/A

where L is the active length in centimeters, A is thecross sectional area, and ρ is the resistivity in ohm-cm.of the semiconductor material.

In addition to the resistor shown in FIGURE 1, aresistor may be provided as shown in FIGURE la forintegration into and as forming a part of a body ofsemiconductor material. In FIGURE la, there is showna body 10a of p-type semiconductor material with ann-type region 10b formed therein. Of course,between the body 10a and region 10b there is a p-njunction which is designated by the numeral 13. Con-tacts 11a and 12a are made to one surface of theregion 10b, spaced apart from each other in order toachieve a desired resistance. As in FIGURE 1, thecontacts 11a and 12a are ohmic contacts to the region10b. A resistor formed in the manner of FIGURE la has several important advantages. First,the p-n junction 13 provides a barrier to current flow

from the n-type region 10b into the p-type body 10aand, thus, the current flow is confined to a path inthe n-type region 10b between the contacts thereto.The second advantage is that the total resistancevalue thereof can be controlled to a large degree. Thetotal resistance value may be controlled by etchingvery lightly over the entire surface to remove theuppermost portion of the n-type region 10b, beingvery careful to not etch through the p-n junction, andas well by selectively etching to or through the p-njunction 13 thereby effectively to increase the lengthof the path traveled by the current between the con-tacts. The third, and perhaps major, advantage informing a resistor according to FIGURE la is in that,by controlling the doping level or impurity concen-tration in the n-type region 10b, lower and morenearly constant temperature coefficients may be pro-vided for the resistor. The above description hasbeen in terms of a p-type body 10a and an n-typeregion 10b but it is obvious that the body 10a couldbe equally as well of n-type conductivity and theregion 10b of p-type conductivity. Resistors accord-ing to FIGURE la may be formed as separate circuitelements or components.

Capacitor designs may be obtained by utilizing thecapacitance of a p-n junction, as shown in FIGURE 2,wherein a semiconductor wafer 15 of p-type conduc-tivity is shown containing an n-type diffused layer 16.Ohmic contacts 17 are made to opposite faces of thewafer 15. The capacitance of a diffused junction isgiven by

C = Aε

(qa

12εV

)1/3

where A is the area of the junction in square cm., ε isthe dielectric constant, q is electronic charge, where ais the impurity density gradient, and V is the appliedvoltage.

Instead of the capacitor of FIGURE 2, capacitancein a body of single crystal of semiconductor materialmay be provided as shown and described in connec-tion with FIGURE 2a. FIGURE 2a shows a body 15a ofsemiconductor material, of either n- or p-type con-ductivity, which constitutes one plate of the capacitor.Evaporated onto the body 15a is a layer 18 providinga dielectric layer for the capacitor. It is necessary thatthe layer 18 have a suitable dielectric constant and beinert when in contact with the semiconductor body15a. Silicon oxide has been found to be a suitablematerial for dielectric layer 18 and may be applied byevaporation or thermal oxidation techniques ontobody 15a. Plate 19 forms the other plate of the capac-itor and is provided by evaporating a conductivematerial onto layer 18. Gold and aluminum have beenfound to be satisfactory materials for the plate 19.Ohmic contact 17a is made to the body of semicon-ductor material 15a and contact to plate 19 may be



PATENTS

made by any suitable electrical contact (not shown).Capacitors formed in the manner described in con-nection with FIGURE 2a have been found to exhibitmuch more stable characteristics than pure junctioncapacitors, that is, p-n junction capacitors, and, ofcourse, may be fabricated as separate elements orcomponents.

Capacitors produced in the manner of FIGURE 2are also diodes, and must therefore be properly polar-ized in the circuit. Non-polar capacitors may be madeby connecting two such areas back-to-back. Althoughjunction capacitors have a marked voltage depend-ence, such dependence is present to a lesser degreefor low voltages in the non-polar configuration.

Resistor and capacitor designs may be combinedto form a distributed R-C network. Such is shown inFIGURE 3, wherein a wafer 20 of p-type conductivityhaving an n-type conductivity diffused layer 21formed therein is provided with a broad area contact22 on the face and spaced contacts 23 on the oppo-site face. These networks are useful for low pass-filters, phase shift networks, coupling elements, etc.Their parameters may be calculated from the equa-tions above. Other configurations of this general typeare also possible.

Transistors and diodes may be formed on a wafer,as described by Lee in “Bell System Technical Jour-nal,” vol. 35, p. 23 (1956). This reference describes atransistor, as shown in FIGURE 4, which has a collec-tor region 25, a diffused p-n junction 26, a base layer27, an emitter contact 28 for a rectifying connectionwith base layer 27 and base and collector contacts 29and 30, respectively. The base layer 27 is formed as amesa of small cross section. A diode of similar designis shown in FIGURE 5, and consists of a region 35 ofone type conductivity, a mesa region 36 of oppositeconductivity type with a p-n diffused junction formedtherebetween and contacts 37 and 38 to each region.

Small inductances, suitable for high frequency use,may also be made by shaping the semiconductor asevidenced by FIGURE 5a which shows a spiral ofsemiconductor material. It is also possible to preparephotosensitive, photoresistive, solar cells and otherlike components utilizing the considerations outlinedabove.

Although all of the circuit elements have beendescribed in terms of a single diffused layer, it is quitepossible to use a double diffused structure. Thus,double diffusion may be employed to form both n-p-n and p-n-p structures. Moreover, any suitablesubstances can be used for the semiconductor materi-als, conductivity producing impurities, and contactmaterials; and suitable and known processing can beexploited in producing the above circuit designs.

Because all of the circuit designs described abovecan be formed from a single material, a semiconduc-

tor, it is possible by physical and electrical shaping tointegrate all of them into a single crystal semiconduc-tor wafer containing a diffused p-n junction, or junc-tions, and to process the wafer to provide the propercircuit and the correct component values. Junctionareas for the transistors, diodes, and capacitors areformed by properly shaped “mesas” on the wafer.

A specific illustration of an electronic circuitembodying the principles of the invention is shown inFIGURE 6a. As shown, a thin wafer of single crystalsemiconductor material containing a diffused p-njunction has been processed and shaped to include acomplete and integrated multivibrator electronic cir-cuit formed essentially in one surface of the wafer.The regions of the wafer have been marked with sym-bols representative of the circuit element functionsthat are performed in the various regions. FIGURE 6bshows a wiring diagram of the various circuit func-tions in the relationship which they occupy in thewafer of FIGURE 6a. A more conventionally drawncircuit diagram is shown in FIGURE 7 with the circuitvalues actually used. The multivibrator circuit shownin FIGURES 6a, 6b and 7 will be described as illus-trative of the processing techniques employed. First,a semiconducting wafer, preferably silicon or germa-nium, of the proper resistivity is lapped and polishedon one side. For this design, 3 ohm-cm, p-type ger-manium was used. The wafer was then subjected toan antimony diffusion process which produced an n-type layer on the surface about 0.7 mil deep. Thewafer was then cut to the proper size, 0.200 inch ×0.080 inch and the unpolished surface was lapped togive a wafer thickness of 0.0025 inch.

Gold plated Kovar leads 50 were attached by alloy-ing to the wafer in the proper positions (as shown).Kovar is a trade name for an iron-nickel-cobalt alloy.Gold was then evaporated through a mask to providethe areas 51–54 which provide ohmic contact with then region, such as the transistor base connections andthe capacitor contacts. Aluminum was evaporatedthrough a properly shaped mask to provide the tran-sistor emitter areas 56, which form rectifying contactswith the n layer.

The wafer was then coated with a photosensitiveresist or lacquer, such as Eastman Photo Resist, sup-plied by Eastman Kodak Company, and exposedthrough a negative to a light. The lacquer imageremaining after development was used as a resistfor etching the wafer to the proper shape. In par-ticular, this etching forms a slot through the waferto provide isolation between R1 and R2 and the restof the circuit and also shapes all of the resistorareas to the previously calculated configuration.Either chemical etching or electrolytic etching maybe used, although electrolytic etching appears to bepreferable.


PATENTS


After this step, the photoresist was removed with asolvent and the mesa areas 60 masked by the samephotographic process. The water was again immersedin etchant and the n layer completely removed in theexposed areas. A chemical etch is considered prefer-able. The photoresist was then removed.

Gold wires 70 were then thermally bonded to theappropriate areas to complete the connections and afinal clean-up etch given. Instead of using the goldwires 70 in making electrical connections, connec-tions may be provided in other ways. For example,an insulating and inert material such as silicon oxidemay be evaporated onto the semiconductor circuitwafer through a mask either to cover the wafer com-pletely except at the points where electrical contactis to be made thereto, or to cover only selected por-tions joining the points to be electrically connected.Electrically conducting material such as gold maythen be laid down on the insulating material to makethe necessary electrical circuit connections.

After testing, the circuit may be hermetically sealed,if required, for protection against contamination. Thefinished device was smaller by several orders of mag-nitude than any others which have previously beenproposed. Because the fabrication steps required arequite similar to those now used in manufacturing tran-sistors and because of the relatively small number ofsteps required, these devices are inherently inexpen-sive and reliable, as well as compact.

A further illustration of the process hereof is shownin FIGURES 8a–8c. Each area of the single crystalsemiconductor wafer has been marked with a symbolfor the circuit element which it represents. This unitillustrates the use of resistors, transistors, and a dis-tributed R-C network to form a complete phase shiftoscillator.

It must be emphasized that the two embodimentsdescribed above are merely two of innumerable cir-cuits which can be fabricated by the techniques of thepresent invention. There is no limit upon the com-plexity or configuration of circuits which can be madein this manner. While there is a limit upon the typesand values of components which can be made in alimited space, the invention hereof nevertheless rep-resents a remarkable improvement over the prior art.As evidence of the advance in the art accomplishedby the present invention, it is possible using the tech-niques described above to achieve component densi-ties of greater than thirty million per cubic foot ascompared with five hundred thousand per cubic footwhich is the highest component density attained priorto this invention.

Although the invention has been shown anddescribed in terms of specific embodiments, it will beevident that changes and modifications are possiblewhich do not in fact depart from the inventive con-cepts taught herein. Hence, such changes and modi-

fications are deemed to fall within the purview of theinvention.

What is claimed is:

1. In an integrated circuit having a plurality of elec-trical circuit components in a wafer of single-crys-tal semiconductor material, a plurality of junctiontransistors defined in the wafer, each transistorincluding thin layers of semiconductor material ofopposite conductivity-types adjacent one majorface of the wafer providing a base and an emitterregion which overlie a collector region, the base-emitter and base-collector junctions of each of saidtransistors extending wholly to said one majorface, a plurality of thin elongated regions of thewafer exhibiting substantial resistance to providesemiconductor resistors, the elongated regionsbeing spaced on said one major face from thetransistors, and conductive means connectingselected ones of the elongated regions to regionsof selected ones of the transistors.

2. In a semiconductor device which includes a single-crystal semiconductor wafer: a junctiontransistor provided adjacent one major face of thewafer by thin layers of semiconductor material ofopposite conductivity types overlying one anotherand extending to said one major face with theemitter-base and base-collector junctions of thetransistor extending wholly to said one major face;and a resistor provided in the wafer by a discreteelongated region of the semiconductor materialwhich is spaced from the transistor on said onemajor face.

3. An integrated circuit comprising a wafer of semi-conductor material containing a plurality of elec-trical circuit components including at least oneactive circuit component and at least one passivecircuit component, the active circuit componentincluding at least two thin layers of semiconductormaterial of opposite conductivity-types extendingto one major face of the wafer with p-n junctionsof the active circuit component extending whollyto said one major face, the passive circuit compo-nent including at least one discrete region of thesemiconductor material of the wafer which isspaced on said one major face away from the thinlayers of the active component, substantial electri-cal impedance being exhibited between the semi-conductor material contiguous to the at least onediscrete region of the passive component andsemiconductor material immediately underlyingsaid thin layers of the active component.

4. An integrated circuit according to claim 3 whereinsaid active circuit component is a junction transis-tor, said passive circuit component is an elongatedresistor region, and said semiconductor materialimmediately underlying said thin layers of the



PATENTS

active component defines the collector region ofthe junction transistor.

5. An integrated circuit according to claim 3 whichfurther comprises: at least one other active circuitcomponent provided in the wafer and including atleast two thin layers of semiconductor material ofopposite conductivity-types extending to said onemajor face with p-n junctions of such other activecircuit component extending wholly to said onemajor face; and at least one other passive circuitcomponent provided in the wafer and including atleast one discrete region of the semiconductormaterial which is spaced on said one major faceaway from the thin layers of the at least one otheractive component.

6. An integrated circuit according to claim 5 whereinsaid discrete regions of said passive circuit com-ponents include thin surface-adjacent regions atsaid one major face of the wafer.

7. An integrated circuit according to claim 3 whereinthe at least one discrete region of the passive cir-cuit component includes a thin surface-adjacentlayer of semiconductor material.

8. An integrated circuit according to claim 7 whereinthe passive circuit component is a resistor.

9. An integrated circuit according to claim 3 whereinat least one of said circuit components includes athin layer of dielectric material overlying said onemajor face of the wafer with a thin layer of con-ductive material overlying the dielectric material.

10. A semiconductor device comprising: a body ofsingle-crystal semiconductor material; an activecircuit component provided adjacent one majorface of the body and including thin regions of thesemiconductor material which extend to said onemajor face, each of such regions being of differentconductivity than adjoining semiconductor materi-al with the interface between each such regionand other of the semiconductor material of thebody extending wholly to said one major face; apassive circuit component provided in the bodyby a discrete portion of the semiconductor mate-rial which is spaced from the active circuit com-ponent on said one major face, substantial electri-cal impedance existing through the body betweensaid thin regions of the active circuit componentand the discrete portion of the passive circuitcomponent.

11. A semiconductor device according to claim 10wherein at least part of said substantial electricalimpedance is exhibited by at least one p-n junc-tion within the wafer.

12. An integrated circuit comprising a wafer of single-crystal semiconductor material having aplurality of electrical circuit components therein,the components including an active circuit com-

ponent which comprises thin regions of semicon-ductor material of opposite conductivity-typesclosely adjacent one major face of the wafer withp-n junctions between such thin regions extend-ing wholly to said one major face, the compo-nents further including a semiconductor resistorprovided by a discrete elongated region of thewafer which is spaced on said one major facefrom the active circuit component, and a conduc-tive lead connecting an end of the elongatedregion to one of the thin regions of the active cir-cuit component.

13. In an integrated circuit having a plurality of circuitcomponents in a wafer of single-crystal semicon-ductor material, a pair of junction transistorsdefined in the wafer with each transistor includingthin layers of alternate conductivity type adjacentone major face of the wafer providing a base andan emitter region which overlie a collector region,the base-emitter and collector-base junctions ofeach of said transistors extending wholly to saidone major face, elongated semiconductor meansdefined in the wafer and exhibiting substantialresistance to provide load resistor means for thepair of transistors, first conductive means con-nected to the collector region of one of the tran-sistors and to an end of the elongated semicon-ductor means, second conductive means connect-ed to the collector region of the other one of thetransistors and to an end of the elongated semi-conductor means, means including contacts to theemitter regions of the transistors and to the elon-gated semiconductor means for applying operat-ing bias to the transistors and means includingseparate contacts on said base regions for apply-ing inputs to said pair of transistors.

14. In an integrated circuit according to claim 13 firstand second elongated semiconductor regionsdefined in the wafer and exhibiting substantialresistance to provide base resistors for the pair oftransistors, and conductive means separately con-necting an end of the first elongated region to thebase region of one of the transistors and an endof the second elongated region to the base regionof the other of the transistors.

15. An integrated circuit ahving a plurality of electricalcircuit components in a wafer of single-crystal semi-conductor material, at least one of the componentsbeing an active circuit component which includesthin layers of semiconductor material of alternateconductivity types defined in the wafer adjacent onemajor face thereof with p-n junctions of such activecircuit component extending wholly to said onemajor face, at least one of the components being apassive circuit component which includes at leastone discrete region defined in the wafer, the passive


PATENTS


circuit component being spaced on said one majorface from the active circuit component, substantialelectrical impedance being exhibited through thewafer between the active circuit component and thepassive circuit component, a plurality of intercon-nections between selected ones of the electrical cir-cuit components, the circuit components and inter-connections being so arranged and constructed asto allow, upon the application of electrical power,the performance within the structure of an electricalfunction equivalent to the function performed by aplural element electrical network.

16. An integrated circuit comprising a wafer of single-crystal semiconductor material containing aplurality of electrical circuit components defined inthe wafer, the circuit components including an activecircuit component which comprises at least two thinregions of the wafer of opposite conductivity-typeseach extending to one major face with the junctionbetween each such thin region and other semicon-ductor material of the wafer extending to said onemajor face, the circuit components further includinga passive circuit component which comprises at leastone discrete region of the semiconductor material,the discrete region being spaced on said one majorface from the thin regions of the active circuit com-ponent, non-common regions of the active and pas-sive circuit components being interconnected toform at least part of an electrical circuit.

17. In a semiconductor device according to claim 2,said thin layers of said junction transistor beingportions of a raised mesa-shaped part of said onemajor face.

18. An integrated circuit according to claim 3 where-in said active circuit component is a junction tran-sistor with said two thin layers being the base andemitter regions of said junction transistor, theemitter region being substantially smaller than thebase region on said one major face, a base con-tact being positioned on said base region spacedfrom the emitter region.

19. An integrated circuit according to claim 18 where-in said discrete region of the passive circuit com-ponent includes a thin surface-adjacent layer ofsemiconductor material of conductivity-typeopposite that of subjacent semiconductor materi-al, an ohmic contact is provided on said surface-adjacent layer, and a conductive lead connectssuch ohmic contact to said base contact.

20. A semiconductor device according to claim 10wherein said passive circuit component providedin the body by said discrete portion of the semi-conductor material includes a thin surface-adja-cent portion of the semiconductor material at saidone major face of the body, such thin portionbeing of conductivity differing from subjacentsemiconductor material.

21. A semiconductor device according to claim 20wherein separate electrical contacts are provided onat least two of said thin regions of the active circuitcomponent on said one major face, wherein a con-tact is provided on said thin surface-adjacent por-tion on said one major face, and wherein conduc-tive means interconnects said contact on said sur-face-adjacent portion with one of said contacts onsaid thin regions of the active circuit component.

22. In an integrated circuit according to claim 13 saidelongated semiconductor means being a singleelongated region of the semiconductor materialwith said first and second conductive means beingseparately connected to opposite ends of suchelongated region and with said means for apply-ing operating bias being connected to a centrallylocated portion of such elongated region.

23. In an integrated circuit according to claim 13 saidmeans for applying inputs to said pair of transistorsincludes separate coupling means connecting thefirst conductive means to the contact on the baseregion of said one of the transistors and connectingthe second conductive means to the contact on thebase region of said other one of the transistors.

24. An integrated circuit according to claim 16 where-in said discrete region of the passive circuit com-ponent includes a thin surface-adjacent region ofconductivity type opposite to that of subjacentsemiconductor material.

25. An integrated circuit according to claim 24 where-in said passive circuit component is a P–N junc-tion capacitor.

References Cited in the file of this patentUNITED STATES PATENTS

2,493,199 Khouri Jan. 3, 19502,748,041 Leverenz May 29, 19562,816,228 Johnson Dec. 10, 19572,817,048 Thuermel Dec. 17, 19572,824,977 Pankove Feb. 25, 19582,836,776 Ishikawa May 27, 19582,878,147 Beale Mar. 17, 19592,915,647 Ebers Dec. 1, 19592,916,408 Freedman Dec. 8, 19592,922,937 Hutzler Jan. 26, 19602,935,668 Robinson et al. May 3, 19602,995,686 Selvin Aug. 8, 19612,998,550 Collins et al. Aug. 29, 1961

United States Patent Office3,138,743Patented June 23, 1964Jack S. Kilby, Dallas, Tex., assignor to Texas Instru-ments Incorporated, Dallas, Tex., a corporation ofDelawareFiled Feb. 6, 1959, Ser. No. 791,60225 Claims. (Cl. 317-101)


Spring 2007 IEEE SSCS NEWSL 55

PEOPLE

Former SSCS officers andAdCom members Asad Abidi,Mark Horowitz, and Teresa

Meng were among 64 Americansand nine foreign associates electedin January to the National Academyof Engineering Class of 2007.

Election to the National Academyof Engineering is among the highestprofessional distinctions accordedto an engineer. Founded in 1964,the NAE now has 2,217 peer-elect-ed members and 188 foreign asso-ciates who are among the world’smost accomplished engineers.

Academy membership honorsthose who have made outstandingcontributions to engineeringresearch, practice, or education,and to the pioneering of new anddeveloping fields of technology,making major advancements in tra-ditional fields of engineering, ordeveloping/implementing innova-tive approaches to engineeringeducation.

The National Academy of Engi-neering (NAE) is a private, inde-pendent, nonprofit institutionchartered to provide engineeringleadership in service to the nation.In addition to its role as advisor tothe federal government, the NAEalso conducts independent studiesto examine important topics inengineering and technology. NAEmembers provide the expertise fornumerous projects focused on therelationships between engineer-ing, technology, and the qualityof life.

Asad A. Abidi, an elected mem-ber of the SSCS AdCom from 1998-2003 and past secretary who hasalso served the Society as a Distin-guished Lecturer, received the B.Scdegree with honors from ImperialCollege, London in 1976 and theM.S. and Ph.D. degrees in Electri-cal Engineering from the Universi-ty of California, Berkeley in 1978and 1981. He was at Bell Laborato-ries, Murray Hill, NJ from 1981 to1984 as a Member of TechnicalStaff in the Advanced LSI Develop-ment Laboratory. Since 1985, hehas been at the Electrical Engi-neering Department of the Univer-sity of California, Los Angeleswhere he is Professor.

His research interests are inCMOS RF design, data high-speedanalog integrated circuit design,conversion, and other techniquesof analog signal processing.

Dr. Abidi was the Program Sec-retary for ISSCC from 1984 to 1990,and General Chairman of the Sym-posium on VLSI Circuits in 1992.He was Secretary of the IEEE Solid-state Circuits Council from 1990 to1991. From 1992 to 1995, he wasEditor of the IEEE Journal of Solid-state Circuits. He has received the1988 TRW Award for InnovativeTeaching and the 1997 IEEE Don-ald G. Fink Prize Paper Award. Hewas a corecipient of the Best PaperAward at the 1995 European Solid-state Circuits Conference, receivedthe Design Contest Award at the1998 Design Automation Confer-

ence, and received the 1996 JackKilby Best Student Paper Award,,the 1997 Jack Raper Award forOutstanding Technology Direc-tions Paper from ISSCC.. He is anIEEE Fellow.

Mark Horowitz, an electedmember of the SSCS AdCom in1999-2001, is the Yahoo! Founder'sProfessor of Electrical Engineeringand Computer Science at StanfordUniversity. He received his BS andMS in Electrical Engineering fromMIT in 1978, and his Ph.D. fromStanford in 1984. Dr. Horowitz isthe recipient of a 1985 PresidentialYoung Investigator Award, and anIBM Faculty development award, aswell as the 1993 best paper awardat the International Solid State Cir-cuits Conference. In 1990, he tookleave from Stanford to found Ram-bus, Inc., an IP company that hasfocused on high-speed memoryinterfaces. This has led to numerouspatents in the area of both high-speed interface technology, andadvanced memory interfaces. In1999 he was a finalist for the WorldTechnology Award for his work ondeveloping the Rambus technology.He is an IEEE Fellow

Dr. Horowitz’s past researchwork has spanned a wide range ofareas in digital system design, fromworking on CAD tools to high-speed and low-power circuitdesign, to work in computer archi-tecture. Recently his researchgroup has worked on the design ofprocessors, memories and IO

Asad Abidi, Mark Horowitz and Teresa MengElected to U.S. National Academy of Engineering

Asad Ali Abidi,Professor, Electri-cal EngineeringDepartment, Uni-versity of Califor-nia, Los Angeles

for contributions to the developmentof integrated circuits for MOS RF com-munications.

Mark A. Horowitz,Professor of Elec-trical Engineeringand Computer Sci-ence, Stanford Uni-versity, Stanford,CA

for leadership in high-bandwidthmemory-interface technology andin scalable cache-coherent multi-processor architectures.

Teresa H. Meng,Reid Weaver Den-nis Professor ofElectrical Engi-neering, StanfordUniversity, Stan-ford, CA

for pioneering the developmentof distributed wireless networktechnology.


PEOPLE

56 IEEE SSCS NEWS Spring 200756 IEEE SSCS NEWS Spring 2007

devices. This work has lead to anumber of outstanding researchresults, from the highest speedCMOS IO (5Gb/s in a 0.5mmCMOS technology), to the lowestpower SRAM memory design.

In addition to his work on VLSI,Dr. Horowitz has led a number ofarchitecture programs, includingsome of initial work in RISCprocessor design. More recently heco-directed the FLASH project withJohn Hennessy. This program hasdemonstrated the feasibility of cre-ating a flexible memory controllerthat can support both DSM andmessage passing. His most recentproject was the design of a newcomputing framework that couldsupport a larger class of applica-tions, which led to the SmartMemory project.

Teresa H. Meng, an electedmember of the SSCS AdCom in2003-2005, is the Reid Weaver Den-nis Professor of Electrical Engineer-

ing at Stanford University. Herresearch activities during the first 10years at Stanford included low-power circuit and system design,video signal processing, and wire-less communications. She hasreceived many awards and honorsfor her research work at Stanford: anNSF Presidential Young InvestigatorAward, an ONR Young InvestigatorAward, an IBM Faculty Develop-ment Award, a Best Paper Awardand a Distinguished Lecturer Awardfrom the IEEE Signal ProcessingSociety, the Eli Jury Award from U.C.Berkeley, and awards from AT&T,Okawa Foundation and other indus-try and academic organizations.

In 1999, Dr. Meng took leavefrom Stanford and founded Ather-os Communications, Inc., whichprovides leading wireless systemsolutions for transparent connec-tions of data, video, and voicecommunications. As a result of thiseffort, Dr. Meng was named one of

the Top 10 Entrepreneurs in 2001by Red Herring, Innovator of theYear in 2002 by MIT Sloan SchooleBA, the CIO 20/20 Vision Awardin 2002, and the DEMO@15 World-Class Innovator Award in 2005. Shereturned to Stanford in 2000 tocontinue her research and teachingat the University.

Dr. Meng's current researchinterests focus on circuit optimiza-tion, neural signal processing, andcomputation architectures forfuture scaled CMOS technology.She has given plenary talks atmajor conferences in the areas ofsignal processing and wirelesscommunications. She is the authorof one book, several book chap-ters, and over 200 technical articlesin journals and conferences. Dr.Meng is a Fellow of the IEEE. Shereceived her M.S. and Ph.D. inEECS from the University of Cali-fornia at Berkeley and her B.S.from National Taiwan University.

Yannis P. Tsividis and Hugo De Man Receive IEEEField Awards at ISSCC 2007Katherine Olstein, SSCS Administrator, [email protected]

Yannis P. Tsividisreceived the IEEEGustav Robert Kirch-

hoff Award in a ceremonyduring the Plenary Sessionof ISSCC 2007 in San Fran-cisco on 12 February 2007.In the same ceremony,Hugo De Man, ProfessorEmeritus, Katholieke Univer-siteit Leuven, received theIEEE Donald O. PedersonAward in Solid-State Circuits.

IEEE President-Elect LewisTerman presented the Kirch-hoff award to Dr. Tsividis,the Charles Batchelor Memo-rial Professor of Electrical Engineer-ing at Columbia University, onbehalf of the IEEE Board of Direc-tors for his contributions to circuitsand MOS device modeling.

Terman said one nominator

wrote, “Yannis invented, alongwith his students, the MOSFET-Cfiltering approach in the 1980s. …This work had significant commer-cial impact as well as spurring onnew fields of research.”

According to a Tsividiscolleague, said Terman, “Dr.Tsividis’ textbook, ‘Opera-tion and Modeling of theMOS Transistor,’ along withhis constant preaching to theCAD community about theinadequacy of MOSFETmodels for analog design,was instrumental in the cre-ation of the models such asthe EKV and other compactmodels. It is ironic that thebest reference on MOS tran-sistor modeling was writtenby a circuits guy.”

De Man was acknowl-edged for leadership in solid-statecircuit design and integrated circuitdesign methodology.

Terman reported that one nomi-nator said, “In his leadership workwith the Esprit program, and then

Lewis Terman, IEEE President-Elect (right), presentedthe IEEE Gustav Robert Kirchhoff Award to Yannis P.Tsividis at the plenary session of the ISSCC 2007.



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with the EDAC/DATE conferences,just to name two, Professor DeMan has continued to push for astrong European presence indesign and in design technologyfor over three decades.”

Terman said an endorserremarked, “Another aspect of Pro-fessor De Man’s contribution toSolid State science concerns edu-cation. He played a leading role inthe development of a solid cur-riculum at Katholieke Universiteit,Leuven that takes advantage of histhorough background. Many gen-erations of students owe their I.C.system design and CAD educationprofiles to Professor De Man.”

In his acceptance remarks, DeMan said, “This award has a verydeep and special meaning to me,as Don Pederson together withRoger Van Overstraeten, were mygreat mentors. They have shapedmy professional and personal life.Without them I would not be

standing here. Fromthem I learned thatscientific and tech-nological researchonly flourishes when you surroundyourself with creative people, bet-ter than yourself, and motivatethem to work as a team to makethe most ambitious dreams cometrue. This award therefore is alsoan award to the many fine peo-ple that I had the privilege towork with.”

“Looking back at this, I feel thatthere is no greater reward for aprofessor than to see how yourstudents have become the techni-cal leaders of tomorrow. So I amdeeply grateful to my 60 and morePh.D. students and hundreds ofmaster students who really did thework and now are paving the wayto the future on all continents. Ican now retire without regret.”

The IEEE Gustav Robert Kirch-hoff Award is sponsored by the

IEEE Circuits and Systems Societyand recognizes outstanding contri-butions to the fundamentals of anyaspect of electronic circuits andsystems that has a long-term signif-icance or impact. The IEEE DonaldO. Pederson Award in Solid-StateCircuits is sponsored by the IEEESolid-State Circuits Society and rec-ognizes outstanding contributionsto solid-state circuits.

“IEEE and its predecessor soci-eties, the AIEE and the IRE, havebeen recognizing outstanding con-tributions for over a century,” saidTerman. “With these awards, theIEEE recognizes that these talentedand brilliant individuals also havehelped to further the mission of theIEEE to promote the creation ofnew technologies for the benefit ofhumanity and the profession.”

“My thanks go to my wife for supporting this foolishengineer spending day and night with technology and,like a drunk, promising it would be better next week.She has given up that illusion but not her support.Thanks Maria, and thanks to Annemie, my secretary for25 years for keeping order in my otherwise chaoticadministrative behavior.” Hugo De Man

Lewis Terman (right), presented the IEEE DonaldO.Pederson Award to Hugo De Man at the plenary ses-sion of the ISSCC 2007.

SSCS Nominees Recognized at ISSCC Plenary forElevation to Fellow 17 SSCS Members Join IEEE Fellow Class of 2006

Katherine Olstein, SSCS Adminstrator, [email protected]

At the ISSCC Awards Ceremo-ny on 12 February 2007 inSan Francisco, SSCS past

President and IEEE President-ElectLewis Terman congratulated mem-

bers of SSCS whom the Societynominated for elevation to IEEE Fel-low in the Class of 2006: KerryBernstein, Wanda Gass, TakayukiKawahara, Stefan Rusu, and

Masakazu Yamashina. Dr. SehatSutardja was unable to attend.

“IEEE Fellows are an elitegroup,” said Terman. “The IEEElooks to the Fellows for guidance


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58 IEEE SSCS NEWS Spring 200758 IEEE SSCS NEWS Spring 2007

and leadership as the world ofelectrical and electronic technolo-gy and information sciences con-tinues to evolve.”

Eleven more members of theSociety attained the distinction ofFellow on the recommendation ofother IEEE Societies:

Kenneth Kundert (CAS)Orly Yadid-Pecht (CAS)Athanasios Stouraitis (CAS)Luca Benini (CAS)Clark Nguyen (ED)Jayasimha Prasad (ED)Yuhua Cheng (ED)David Plant (LEO)Stefan Heinen (MTT)John Wood (MTT)Bumman Kim (MTT)

The IEEE Fellow Class of 2007comprises a total of 268 members.The distinction, conferred by theIEEE board of Directors, recog-nizes extraordinary contributionsto one or more fields of IEEE inter-est. No more than one-tenth of onepercent of the Institute member-ship may be elevated to Fellow ina given year.

Kerry Bernstein is a Senior Tech-nical Staff Member at the IBM T.J.Watson Research Center, YorktownHts, NY. He currently is Principal

Investigator for 3D integrationtechnology at IBM Research,exploring 3D design and architec-ture. Mr. Bernstein received theB.S. degree in electrical engineer-ing degree from Washington Uni-versity in St.Louis, and joined IBMin 1978. Mr. Bernstein’s work hasbridged technology and circuitdesign, and has explored the tech-nology sensitivities of high per-formance CMOS circuit topologies,the mitigation of delay variability,and soft-error modeling. He servedas lead technologist for IBM’s serv-er and PowerPC processor designsand for IBM’s external foundrycustomers. Mr. Bernstein has hadthe privilege of participating in theroll-out of fundamental device andinterconnect technologies through-out his career, such as CMOS, par-tially-depleted Silicon-On-Insulatordevices, and copper intercon-nects. He holds 50 U.S. patents inthe areas of high performance cir-cuits and technology. Mr. Bern-stein co-authored 2 college text-books with colleague and friendNorman Rohrer, and approximate-ly 100 papers or book chapters onhigh speed / low power CMOS. Heattributes any success he hasenjoyed to be due in large part toworking with wonderful people.Mr. Bernstein has served on theprogram committees for IEEEISSCC and Symposium on VLSIDesign. He derives fulfillment asan industrial mentor for studentsand research at SEMATECH,SRC/MARCO, DARPA, and for highschoolers interested in math/sci-ence/engineering careers. Mr.

Bernstein is a staff instructor atRUNN/Marine Biological Laborato-ries, Woods Hole, MA. He and hisfamily live in Northern Vermont.

Wanda Gass received a BSEEdegree in 1978 from Rice Universi-ty and MS degree in BiomedicalEngineering from Duke Universityin 1980. She has been with TexasInstruments since 1980 where sheis a TI Fellow. She was a key con-tributor in the development of thefirst programmable DSP at TI forwhich she holds several strategicpatents. During her career she hasdone work in VLSI design, algo-rithms for speech codecs, multi-processor system design forspeech recognition and image pro-cessing, silicon compilers for DSPfunctions, video compression VLSIarchitectures, and W-CDMA hard-ware and software implementa-tions. Currently she defines theinstruction set architecture forhigh-performance DSP processors.

She is an active member in theSignal Processing Society and theSolid-State Circuits Society. In theSSCS she has served as Member(1995-1999) and SubcommitteeChair (2000-2005) of ISSCC Inter-national Program Committee andis serving as elected member ofSSCS Ad Com. In the SPS she hasserved as Member (1990-1996)and Chair (1997-1999) of Designand Implementation of Signal Pro-cessing Systems Technical Com-mittee. She was General Chair ofthe Signal Processing SystemWorkshops in 2004.

She is a member of theFounder’s Circle for the Women ofTI Fund that promotes the educa-tion of girls in the fields of science,technology, engineering and math.

From left, Lewis Terman IEEE President-Elect and 2006 Fellows MasakazuYamashina, Stefan Rusu, Takayuki Kawahara, Wanda Gass, and Kerry Bernstein.Dr. Sehat Sutardja was unable to attend.

Kerry BernsteinIBM

for contributions tohigh performancecommon metaloxide semiconduc-tor circuit design

Wanda GassTexas Instruments,Inc.

for contributions todigital signal proces-sors and circuits



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She was inducted into the WITIHall of Fame in 2003 and is on theBoard of Directors for the non-profit organization, Alliance ofTechnology and Women. She ismarried to Richard and has twodaughters in the 11th and 8thgrades.

Takayuki Kawahara receivedB.S. and M.S. degrees in physics in1983 and 1985, and Ph.D. degreein electronics in 1993 from KyushuUniversity, Fukuoka, Japan.

In 1985, he joined CentralResearch Laboratory, Hitachi Ltd.Since then, he has made funda-mental contributions in many areasin the field of low-voltage low-power memories. As early as 1991,as a pioneer, he invented and initi-ated research and development ofcircuits to reduce the subthresholdcurrent of MOSFETs, a key issuetoday in low-voltage CMOS LSIdesigns. A distinctive circuit that heand his team invented and devel-oped was the gate-source self-reverse biasing circuit, which wasapplied to the word-driver block inthe world’s first 256-Mb DRAM. Healso pioneered the charge-recy-cling scheme; it is now widely rec-ognized to be applicable to variouslogic circuits. His team’s recentdevelopment is the back-gate-con-trolled thin BOX FD-SOI SRAMtechnology, a strong candidate fornext-generation CMOS technologythat results in reduced variationand dynamic control of the thresh-old voltage of MOSFET. Currently,his mission is exploring a new con-cept memory. Especially, his inten-tion is to develop the spin transfertorque memory for low power,high density universal memory.

He was a visiting researcher atElectronics Laboratory (LEG),Swiss Federal Institute of Technol-ogy, Lausanne (EPFL) from 1997 to1998. He was a guest editor ofMemory part of special issue ofJSSC, November 2002. He has beena member of the ISSCC programcommittee since 2000 (also execu-tive committee member as FE offi-cer since 2004), and a programcommittee member of the Sympo-sium on VLSI Circuits since 2003(also a secretary/publicity chair of2006/2007 JFE Circuits SymposiumCommittee).

Stefan Rusu (M’85-SM’01-F’07)received the MSEE degree from thePolytechnic University in Bucharest,Romania. He first joined Intel Corp.in 1984 working on data communi-cations integrated circuits. In 1988he joined Sun Microsystems work-ing on microprocessor design withfocus on clock and power distribu-tion, packaging, standard celllibraries, CAD and circuit designmethodology. He re-joined IntelCorp. in 1996 working on the glob-al circuit technology for several Ita-nium® and Xeon® processors. Heis presently a Senior Principal Engi-neer in Intel's Enterprise Micro-processor Group leading the tech-nology and special circuits designteam for the Xeon® MP ProcessorsFamily. His technical interests arehigh-speed clocking, power distri-bution, I/O buffers, power andleakage reduction, and high-speedcircuit design techniques. Stefanhas authored or co-authored morethan 75 papers on VLSI designmethodology and microprocessorcircuit technology. He holds 30U.S. patents with several morepending. He is a member of the

Technical Program Committee forthe ISSCC, ESSCIRC and A-SSCCconferences and an Associate Edi-tor of the IEEE Journal of Solid-State Circuits.

Dr. Sehat Sutardja has served asPresident of Marvell TechnologyGroup Ltd. since its inception andas Chairman of the Board andChief Executive Officer since 1995.In addition, he has served as Presi-dent, Chief Executive Officer and aDirector of Marvell Semiconductor,Inc. since its inception. From 1989until 1995, Dr. Sutardja served as amanager and principal projectengineer at 8X8, Inc., a designerand manufacturer of digital com-munications products. Dr. Sutardjaholds Master of Science and PhDdegrees in Electrical Engineeringand Computer Science from theUniversity of California at Berkeley.

Masakazu Yamashina receivedthe B.S., M.S. and Ph.D. degreesfrom the Tokyo Institute of Tech-nology, Japan, in 1982, 1984 and1993, respectively. In 1984 hejoined NEC Corporation inKawasaki, Japan, where he hasbeen a technical leader in theresearch and the development ofhigh-performance microprocessorcircuits such as video signalprocessors, high-speed micro-processors, dynamically reconfig-

Takayuki KawaharaCentral ResearchLaboratory, HitachiLtd.

for contributions tolow-voltage low-power random

access memory circuitsStefan RusuIntel Corporation

for contributions tohigh performancemicroprocessor cir-cuit technologies

Sehat SutardjaMarvell Semicon-ductor, Inc.

for leadership indesign and com-mercialization ofhigh-speed mixed-

signal common metal oxide semicon-ductors integrated circuits

MasakazuYamashinaNEC Electronics Corporation

for leadership in highperformance micro-processor circuits


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urable processors, and low powersingle-chip multiprocessors. From1989 through 1990, he was a vis-iting researcher at Stanford Uni-versity, where he worked on soft-ware to control autonomousrobot LSIs. Presently he is a gen-eral manager of the mobile LSIdivision in NEC Electronics andleading the development of thelow power microprocessors formobile devices.

Dr. Yamashina published 19ISSCC papers from 1987 to 2000.In 2003, he received a Top-10ISSCC author award in terms ofnumber of ISSCC papers in theISSCC’s 50-year history. He hasworked in the semiconductorindustry for 22 years and published246 technical publications, such asthe world’s first CMOS programma-ble video signal processor and lowpower multi-threading micro-processor. He has also been a vis-iting professor for the Tohoku Uni-versity and the Tokyo Institute of

Technology. He served IEEE as anadministrative committee memberof the IEEE Solid-State CircuitsSociety, executive committee mem-ber of ISSCC, symposium chair andprogram chair of the IEEE Sympo-

sium on VLSI Circuits, and guesteditor of IEEE Journal of Solid-StateCircuits.

SSCS members evaluated byother IEEE societies within theIEEE Fellow Class of 2006 are:

Huijsing, Makinwa, and Pertijs Receive JSSC 2005Best Paper Award

Drs. Michiel. A. P. Pertijs, KofiA. A. Makinwa, and JohanH. Huijsing were honored

at the Plenary Session of the ISSCCin San Francisco on 12 February forthe selection of their paper “ACMOS Smart Temperature SensorWith a 3σ Inaccuracy of ±0.1°Cfrom -55°C to 125°C” as the best inthe JSSC for the year 2005. It waspublished the December issue, andis available in IEEE XPlore. The edi-tors of the Journal award this prizeevery year.

K. Nagaraj, chief JSSC Editorsaid, “This paper describes a fullyintegrated CMOS temperature sen-sor achieving an accuracy of +/-0.1 % over the temperature rangeof -55 degrees C to 125 degrees C.Such high precision is achieved by

using several circuit techniquesincluding dynamic element match-ing, a chopped current gain inde-pendent PTAT bias circuit, and alow-offset second-order sigma-

delta ADC that combines chop-ping and correlated double sam-pling. It will have applications ininstrumentation, measurement andcontrol.”

(From left) Richard C. Jaeger, SSCS President with Dr. Johan H. Huijsing, Dr.Kofi A. A. Makinwa, Dr. Michiel A. Pertis and Laura Fujino, ISSCC Director ofPublications.



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Abstract—A smart temperaturesensor in 0.7 μm CMOS is accurateto within ± 0.1° C (3σ ) over thefull military temperature range of -55° C to 125 ° C. The sensor usessubstrate PNP transistors to meas-ure temperature. Errors resultingfrom nonidealities in the readoutcircuitry are reduced to the 0.01° Clevel. This is achieved by usingdynamic element matching, achopped current-gain independentPTAT bias circuit, and a low-offsetsecond-order sigma-delta ADC thatcombines chopping and correlateddouble sampling. Spread of thebase-emitter voltage characteristicsof the substrate PNP transistors iscompensated by trimming, basedon a calibration at one tempera-ture. A high trimming resolution isobtained by using a sigma-deltacurrent DAC to fine-tune the biascurrent of the bipolar transistors.

Kofi Makinwa holds degrees fromObafemi Awolowo University, Ile-Ife (B.Sc., M.Sc.), Philips Interna-tional Institute, Eindhoven (M.E.E.),and Delft University of Technology,Delft (Ph.D.). From 1989 to 1999,he was a research scientist atPhilips Research Laboratories,where he designed sensor systemsfor interactive displays, and analogfront-ends for optical and magnetic

recording systems. In 1999 hejoined Delft University of Technol-ogy, where he is currently an Asso-ciate Professor at the ElectronicInstrumentation Laboratory.

Dr. Makinwa holds nine USpatents, and has authored or co-authored over 40 technical papers.He has given tutorials at theEurosensors and IEEE Sensors con-ferences. He is on the programcommittees of several internationalconferences, including the Interna-tional Solid-State Circuits Confer-ence (ISSCC) and the InternationalSolid-state Sensors and ActuatorsConference (Transducers). Hismain research interests are in thedesign of precision analog circuit-ry, sigma-delta modulators andsmart sensors.

For his Ph.D. thesis, Dr. Makinwawas awarded the title of ‘SimonStevin Gezel’ by the Dutch Technolo-gy Foundation (STW). In 2005, hereceived a VENI award from theDutch Scientific Foundation (NWO).He is a co-recipient of the ISSCC 2006Jan van Vessem best paper award,the ISSCC 2005 Jack Kilby best stu-dent paper award, and the Journal ofSolid-State Circuits 2005 best paperaward. In 2007, he became a YoungFellow of the Royal NetherlandsAcademy of Arts and Sciences.

Michiel Pertijs received the M.Sc.and Ph.D. degrees in electricalengineering from Delft UniversityTechnology in 2000 and 2005,respectively. From 1997 to 1999 heworked part-time for EARS B.V.,Delft, The Netherlands, on theproduction and development of ahandheld photosynthesis meter.From 2000 to 2005 he worked as aresearch assistant at the ElectronicInstrumentation Laboratory ofDelft University, where he per-formed research on the subject ofprecision smart temperature sen-sors. In context of this research, hedeveloped several precision tem-perature sensors in cooperationwith Philips Semiconductors, Sun-

nyvale, California. Since August2005, he has worked for NationalSemiconductor in Delft. Hisresearch interests include analogand mixed-signal interface elec-tronics and smart sensors.

Johan H. Huijsing received theM.Sc. degree in electrical engineer-ing from Delft University of Tech-nology, Delft, The Netherlands, in1969, and the Ph.D.degree fromthe same university in 1981 for histhesis on operational amplifiers.

He joined the Faculty of ElectricalEngineering of Delft University ofTechnology in 1969, became fullProfessor in the chair of ElectronicInstrumentation in 1990, and hasbeen Professor Emeritus since 2003.From 1982 to 1983, he was a Seniorscientist at Philips Research Labora-tories, Sunnyvale, CA. After 1983, hewas a consultant for Philips Semi-conductors, Sunnyvale and after1998, a consultant for Maxim, Sun-nyvale. His research work isfocused on the systematic analysisand design of operationalamplifiers, analog-to-digital con-verters, and integrated smart sen-sors. He is author or co-author ofsome 200 scientific papers, 40patents and nine books, and co-edi-tor of 11 books.

Dr. Huijsing is a Fellow of IEEEfor contributions to the designand analysis of analog integratedcircuits. He was awarded the titleof ‘Simon Stevin Meester’ forApplied Research by the DutchTechnology Foundation. He isinitiator and co-chairman of theInternational Workshop onAdvances in Analog Circuit De-sign, which has been held annual-ly since 1992 in Europe. He was amember of the program commit-tee of the European Solid-StateCircuits Conference from 1992 to2002. He has been chairman ofthe Dutch STW Platform on Sen-sor Technology and chairman ofthe biennial National Workshopon Sensor Technology from 1991until 2002.

Fig. 1. Operating principle of thetemperature sensor.

Fig.13. Chip micrograph of the tem-perature sensor.


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Best Student Design Awards Presented at ISSCC 2007Bruce Hecht, SSCS Membership Chair, [email protected], and Katherine Olstein, SSCSAdministrator, [email protected]

The winners of the DAC and A-SSCC Student Design Contestsof 2006 presented their work

in two evening poster sessions atISSCC 2007 in San Francisco.

The A-SSCC prize winners werehonored at the conference inNovember, 2006. The DAC awardeeswill be formally acknowledged atthe 44th Design Automation Confer-ence in San Diego, California inJune, 2007.

48 papers were submitted from15 countries for the ten DACawards. “This was an excellentyear, “said Bill Bowhill, a Co-Chairof the contest. “The winners haveoutstanding designs. Many of thestudents showed demonstrationsof their designs at the conferencewhich generated much interestfrom the attendees.”

Award-winning projects werenot ranked for the first time thisyear due to past difficulties incomparing papers dealing withvery different topics and/or tech-nologies. There was no clear out-standing paper for “best overall,”said Kaushik Roy, DAC DesignCommunity Chair. “Since manyEMS/sensors and ADC paperswere submitted this year, moresupport from Data Converters andSensor ISSCC committees will beadded next year,” he said. TheDAC student contest is restricted todesigns originating in universityundergraduate or graduate coursework or research.

CHIP/SYSTEM OPERATIONALA Wireless Implantable Microsys-tem for Continuous Blood Glu-cose MonitoringMohammad M Ahmadi, Graham AJullien, University of Calgary,Canada

An amperometric glucose sen-sor, transpondor chip in 0.18μm

CMOS technology and externalreceiver are presented. Theimplantable sensor and transpon-der design supporting load modu-lation demonstrated promisingperformance: 132μA with 6bitaccuracy.

SYSTEM OPERATIONAL CATEGORYHBS: a Handheld Breast CancerDetector Based on FrequencyDomain Photon MigrationKeun Sik No et al. University ofCalifornia, Irvine, USA

This paper presents a non-inva-sive handheld breast cancer detec-tor using frequency domain pho-ton migration spectroscopy. Thereceiver is in heterodyne topologyand detects broadband-modulated(10MHz – 1GHz) signal. A per-formance similar to that of laserbased system is demonstrated

CHIP OPERATIONAL CATEGORYDesign of an Ultra-Low-VoltageUWB Baseband ProcessorVivienne Sze, Anantha Chan-

drakasan Massachusetts Institute ofTechnology, USA

A 100Mbps throughput UWBbaseband processor operating at asub-threshold supply voltage of0.4V is presented. This workdemonstrates the application ofsub-threshold design to high per-formance systems using parallelism.

An Energy-Efficient Reconfig-urable Multiprocessor IC forDSP Applications Guichang Zhong, Alan N Wilson,University of California, Los Ange-les, USA

This work presents a low-powerreconfigurable multiprocessor witha performance close to ASIC solu-tions while possessing a degree offlexibility.

A 94dB SFDR 78dB DR 2.2MHzBW Multi-bit Delta-Sigma Modu-lator with Noise Shaping DAC Jianzhong Chen, Yong Ping Xu,National University of Singapore,Singapore

The works presents a multi-bitlow-pass delta-sigma modulatoremploying a noise shaping dynam-ic matching technique thatimproves both SFDR and SNR.

A 230mV-to-500mV 375KHz-to-16MHz 32b RISC Core in0.18µm CMOS Chen Jian-Shiun, Yi-Ming Wang,Yu-Juey Chang, Jinn-Shyan Wang,Chingwei Yeh, Tien-Fu Chen,National Chung-Cheng UniversityTaiwan R.O.C

This work presents a low supplyvoltage, 230-500mV, RISC core with375KHz-1MHz clock frequencies. Theultra-low voltage CMOS techniquesuch as dynamic NP-swappable bodybias scheme is extensively studied.

Keun Sik No of UC Irvine explainedthat his hand-held breast cancerdetector “can actually see the insidecontents of the tissue,” unlike xraymammograms and MRI’s. In post-docwork he plans to make the devicesmaller and cheaper so it can beused by patients at home as often asevery hour or half hour to monitorthe progress of chemotherapy. Mr.No said he has been interested inelectronics “ever since I was a kid.”



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A 152mW/195mW MultimediaProcessor with Fully Program-mable 3D Graphics and MPEG/H.264/JPEG for Handheld DevicesJeong-Ho Woo, Ju-Ho Sohn, Hye-jung Kim, Jongcheol Jeong, EuljooJeong, Suk Joong Lee, Hoi-Jun YooKAIST, South Korea

This work presents a multimediaSoC including MPEG4 codec,H.264 decoder, JPEG codec, andfully programmable 3D graphicsengine. The proposed JPEG/MPEGhybrid design provides small areaand low power design. The SoCconsumes 152mW at 48MHz oper-ating frequency.

A 252Kgates/4.9Kbytes SRAM/71mW Multi-Standard VideoDecoder for High DefinitionVideo ApplicationsChih-Da Chien, Chien-Chang Lin,Yi-Hung Shih, He-Chun Chen,Chih-Wei Wang, Cheng-Yen Yu,Chih-Liang Chen, Ching-HwaCheng, Jiun-In GuoNational Chung-Cheng UniversityTaiwan R.O.C.Feng-chia University Taiwan R.O.C.

This paper presents a multi-stan-

dard video decoder supportingJPEG, MPEG-1,2,4, and H.264 forHD video applications. Activehardware sharing scheme and tech-niques that can reduce memorybandwidth are proposed. The chipconsumes 71.1mW at 120MHz/1Vand 7.9mW at 20MHz/0.8V.

A 152mW/195mW MultimediaProcessor with Fully Programma-ble 3D Graphics and MPEG/H.264/JPEG for Handheld DevicesJeong-Ho Woo, Ju-Ho Sohn, Hye-jung Kim, Jongcheol Jeong, EuljooJeong, Suk Joong Lee, Hoi-Jun YooKAIST, South Korea

This work presents a multimediaSoC including MPEG4 codec,H.264 decoder, JPEG codec, andfully programmable 3D graphicsengine. The proposed JPEG/MPEGhybrid design provides small areaand low power design. The SoCconsumes 152mW at 48MHz oper-ating frequency.

CONCEPTUAL [functional siliconshown at conference]The Scale Vector-Thread Processor Ronny Krashinsky, ChristopherBatten, Krste Asanovic, Massa-

chusetts Institute of Technology,USA

This work presents the scale vec-tor-thread processor as a complexi-ty-effective solution for embeddedcomputing. An efficient design flowand low power design techniquesare thoroughly explored. It demon-strates the potential performance ofthe vector-thread unit.

The A-SSCC posters were:A 1.5 MS/s 6-bit ADC with 0.5VSupplySimone Gambini, Jan Rabaey, UCBerkeley

A TCAM-based Periodic EventGenerator for Multi-Node Man-agement in the Body SensorNetworkSungdae Choi, Kyomin Sohn, Jooy-oung Kim, Jerald Yoo, Hoi-JunYoo, Kaist, Daejeon Korea

A 0.98 to 6.6 GHz Tunable Wide-band VCO in a 180 nm CMOSTechnology for ReconfigurableRadio TransceiverTusaku Ito, Hirotaka Sugarawa,Kenichi Okada, Kazuya MasuTokyo Institute of Technology

“Vector-threaded architecture is able to exploit both dataparallel vector computation and act as a highly multi-threaded engine,” said designer Ronny Krashinsky of MIT.“We wanted to find a flexible architecture that could exe-cute many different types of embedded applications likegraphics, network processing, and cryptography.”

“The basic interface to the architecture is virtual proces-sors; each typically executes one iteration of a loop,” hesaid. “If it’s a vectorizable loop, it’s executed purely withvector instructions. But if the loop has conditional opera-tions, then each of those virtual processors can take aconditional branch to direct their own control flow. So theoverhead of repeatedly executing blocks of instructionsgets amortized.”

Christopher Batten, who created the high bandwidth memory system to support Krashinsky’s execution unit, said, “Ialways wanted to do hardware - chip design. When I came to MIT, I thought we’d be doing chips right away. But ittook six years before we actually built a chip. That took about two years, but it was worthwhile because a lot of ourinitial area and energy claims were validated by doing it.”

This was a small-scale project, Batten said. “Two students, less expensive, very hands on. We got to do everything. Itwas a lot of fun.”

“One of the cool things about doing this is that I get to come to ISSCC,” he concluded. “It’s so different from the con-ferences I go to. There’s a whole lot more industry people here. It’s a whole different community.”



Lanzerotti Honored by IEEE Women in EngineeringSociety of New YorkVLSI Designer Named Engineer of the Year 2006

Dr. Mary Yvonne Lanzerottireceived the Engineer of theYear 2006 award from the

NY Section of the IEEE Women inEngineering (WIE) Society at theIEEE New York Section Annual Din-ner Dance in New York City on Feb-ruary 10th. She received the award“In recognition of her outstandingtechnical and service contributionsto the engineering profession andpromotion of women in the scienceand technology disciplines.”

Dr. Lanzerotti is a Research StaffMember at the IBM T.J. WatsonResearch Center in YorktownHeights, NY. She received an A.B.degree from Harvard in 1989, anM. Phil. Degree from the Universi-ty of Cambridge in 1991, and theM.S. and Ph.D degrees from Cor-nell in 1994 and 1997, respectively.

She joined IBM in 1996. She iscurrently in the VLSI Design Depart-ment, where her research interestsinclude analysis of POWER6 timing-

critical paths and the design andimplementation of on-chip intercon-nections for the POWER4. Dr.Lanzerotti is a member of the IEEESpectrum Advisory Board and mem-ber of the IEEE Solid-State CircuitsSociety, where she is the co-editor ofthe society Newsletter, and has beenthe driving force behind its currentmakeover. She is also a member ofthe IEEE Lasers and Electro-OpticsSociety (LEOS), where she has beenan elected member of the Board ofGovernors (2003-2005) and Execu-tive Editor (2001-2006) and Associate

Editor (1995-2000) of the LEOSNewsletter.

In addition to her technical work,Dr. Lanzerotti has lectured on thesteps engineers and scientist can taketo improve their professional devel-opment at the NY Section of the IEEEWIE. These steps been identified bythe American Physical Society (APS)Committee on Careers and Profes-sional Development and are given inthe first Professional DevelopmentResource Guide that list resourcesidentified as important for the profes-sional development of today’s engi-neers and scientists. This guide isposted on the APS website atwww.aps.org/careers/index.cfm. Dr.Lanzerotti is also a member of theAPS Women Speakers List posted atwww.aps.org/programs/women/speakers/ and participates in NationalEngineers Week, visiting local schoolswith other IBM scientists attractingfemale students to engineering, sci-ence, and information technology.

Congratulations New Senior Members34 Elected in January and FebruaryKhalid Abed Mississippi Section

Lars Bengtsson Sweden Section

Paul Berndt Seattle Section

Lucien Breems Benelux Section

Michael Brooks Buenaventura Section

Arthur Cappon Dallas Section

Vivek De Oregon Section

Sher Fang Dallas Section

Roland Gesche Germany Section

P Govindacharyulu Hyderabad Section

Mustafa Guvench Maine Section

Nikos Haralabidis Greece Section

Ronald Hickling Buenaventura Section

Joe Howell Eastern Idaho Section

Cosmin Iorga Buenaventura Section

Kannan Krishna Oregon Section

J Marcos Laraia Eastern Idaho Section

Ming-Kin Law Toronto Section

See Lee Dallas Section

Adrian Leuciuc Baltimore Section

Wolf-Ekkehard Matzke Germany Section

Harry Mcintyre Coastal Los Angeles Section

Makoto Nagata Kansai Section

Robert Neidorff New Hampshire Section

Takao Onoye Kansai Section

Gregory Pauls Pikes Peak Section

Sameh Rehan Egypt Section

John Safran Mid-Hudson Section

Boon Eu Seow Malaysia Section

David Standley Buenaventura Section

Simon Tam Oakland-East Bay Section

Joseph Walsh Eastern Idaho Section

Kazuya Yamamoto Kansai Section

Kevin Zhang Oregon Section

PEOPLE

The body sensor processor devised by Sungdae Choi, an A-SSCC award winner, can beused at home for monitoring and transmitting bio-signals to health care profession-als. He envisions that with this device “even healthy people will be able to catchsymptoms of abnormal health conditions” and have them automatically forwarded forfollow-up.

“When I was very young, I was interested in making something work as I desired,” hesaid. “So I decided in my mind to become a doctor, a kind of doctor. I wanted to con-tribute to human life. My dream came true. Now I have another dream, to make someuseful gadget for people and every person will use the gadget I made.”



PEOPLE

Perhaps the most annoyingthing about reports is the waythey gobble up time. First,

writers spend hours sketching thecomplex background of the projectand describing results in sufficientdetail to impress higher-ups withthe thoroughness of the work. (Ifthe facts aren’t impressive enough,fancy wording must come to therescue, at further cost in writingtime.) Then readers groan as theytry in vain to find shortcuts throughthe thicket of irrelevant or bafflingdetail and convoluted language.Nobody is happy, important infor-mation gets lost, and a lot of timedisappears into a black hole.

Some writers learn from suchmistakes and scratch out most ofthe irrelevant and confusing thingsthey put into their draft before theysend it out. Now the writing takeseven longer for them, but at leasttheir readers are better off.

Isn’t there a way to avoid all thewaste of time from the start? Yes—and it’s as simple as respectingthree commonsense laws:1. Don’t make your readers read

any thing they don’t want toknow.

2. Don’t write down things you’llend up deleting.

3. Don’t make the reader read any-thing twice.

Reimolds’ Law #1: Don’t MakeYour Readers Read AnythingThey Don’t Want To KnowNo matter how much you’d like toget upper-management readers toappreciate the intricacies of yourwork, they will only resent beingheld up by technical details or puffylanguage. So save them time byincluding only significant informationand keeping the language simple.

How do you achieve this? Bypreparing an outline based on ananalysis of reader needs. The needsanalysis takes the form of an imag-inary dialogue with each readergroup. Begin by noting the ques-tions of the primary reader, thenthose of other readers. Answer thequestions in list form and you havean outline of the significant points.Anything else you’re burning toadd doesn’t belong in the report.

Reimolds’ Law #2: Don’t WriteDown Things You’ll End Up DeletingMany writers begin the draftingprocess by expanding their datatables into detailed results,expanding those further in a dis-cussion section, then adding somedetailed background as an intro-duction, and finally trying someconclusions and a summary. Atthat point, they may begin to spotirrelevant details and start thetedious cutting process.

Instead, begin the wholeprocess with the summary. Thisanswers the reader’s first question:“What are you trying to tell me?”(For instance: Our new teamworkapproach to the problem withabsenteeism has shown significant-ly better results than previous one-on-one confrontations.) Thenexplain or back up that main mes-sage only as much as needed foryour readers. When did the absen-teeism problem begin? How didyou try to solve it in the past? Whatdid you do differently with theteam approach? What do yourfindings suggest? What obstaclesremain? What are the next steps foryou and the readers?

When your main message is inplace, you can judge easily whichdetails serve it and which detract

from it or add nothing important.By contrast, when you start withthe details, you miss the yardstickfor measuring relevance, and over-writing is inevitable.

Reimolds’ Law #3: Don’t Makethe Reader Read Anything TwiceReaders don’t like having to rereada sentence because it is unclear,ambiguous, or deliberately con-structed so as to require parsingtwice (that’s the drawback ofwords like former, latter, andrespectively). Look at your style. Isit more like A than B? Then it’s timeto work on clarity and simplicity!A. From consideration of these facts,

the probability presents itself thatthe unfavorable work environ-ment on Project X, as opposed tothe more propitious circum-stances surrounding the efforts onProject Y, in no small way imped-ed the presence and effectivecontributions of team members ofthe former, leading inescapably tothe noticeable problem of absen-teeism therein, versus the latter.

B. findings suggest that the poorworking conditions on Project Xcontributed greatly to the prob-lem of absenteeism on that proj-ect. Project Y, which had betterworking conditions, did nothave this problem.

Cheryl and Peter Reimold have beenteaching communication skills to engi-neers, scientists, and businesspeople for20 years. Their firm, PERC Communi-cations (+1 914 725 1024, [email protected]), offers businesses con-sulting and writing services as well ascustomized in-house courses on writ-ing, presentation skills, and on-the-job communication skills. Visit theirweb site at www.allaboutcommunica-tion.com.

TOOLS: How to Write Readable Reports and WinningProposalsPart 3: Save Readers and Yourself Precious Time

By Peter and Cheryl Reimold, www.allaboutcommunication.com


CHAPTERS


New SSCS Chapters in Tainan and South Brazil Seoul and Santa Clara Chapters Host Talks by S. Kang, M. Pedram, and M. Horowitz

With the assistance of SSCSChapters Chair Jan Vander Spiegel, Wilhelmus

Van Noije, a Professor in the Elec-tronic Systems Engineering depart-ment at the Polytechnical School ofthe University of Sao Paulo, spear-headed the formation of a new SSCSChapter in South Brazil.

Dr. Noije was one of 40 atten-dees at the Society’s Chapter ChairLuncheon and Meeting in SanFrancisco on 13 February 2007.

An SSCS Chapter in southernTaiwan was founded by Prof.Chua-Chin Wang of National SunYat-Sen University in Kaohsiung.His description of the circum-stances that led to the formation ofthe Society’s second Taiwanesechapter, and his story of how hegained local support for it, may befound in this issue.

Seoul Chapter Hears S. Kang onBioelectronics and M. Pedram onCharge-recycling MTCMOSChulwoo Kim, Korea University,[email protected]/SSCS Seoul hosted two lec-tures by SSCS Distinguished Lectur-ers in 2006.

Prof. Steve Kang, University ofCalifornia, Santa Cruz presented aninteresting paper entitled, “Bioelec-tronics, Its Status and Prospectus” atKorea University on 12 August 2006.

In this talk, the current status of

biomimetic microelectronic sys-tems, laboratory-on-a-chip (LoC),and energy scavenging forimplantable devices were discussedwith development of CAD modelsand simulation tools for biologicalcircuits, biomimetic systems, andtheir hybrid structures. About 100people attended the seminar. Thelecture was followed by a dinnermeeting to give chapter members achance to get together with the lec-turer and to have extended conver-sations on selected topics.

Prof. Massoud Pedram, Universi-ty of Southern California, presenteda talk entitled, "Charge-recyclingMTCMOS: Circuit Techniques andDesign Automation Algorithms” atCOEX, Seoul on 26 October 2006.25 people attended the seminar. Hespoke about a charge recyclingMTCMOS technique that cuts theenergy consumption for mode tran-

sitions in half while preserving thewakeup delay and reducing theground bounce level in the targetcircuit. At a chapter meeting afterhis presentation, Prof. Pedram gaveseveral good tips to improve chap-ter activities such as DL seminars,homepage management, organiz-ing international conference, etc.

Mark Horowitz Speaks in SantaClara on “Rethinking Analog” Santa Clara Valley Chapter Host10 Events in 2006 Dan Oprica, IEEE Santa Clara Val-ley Executive Committee AwardsChair; IEEE SCV Solid State CircuitsSociety Chapter Programs Chair,[email protected]

On 27 March 2007, Dr. MarkHorowitz of Stanford Universityaddressed the chapter on the topicof Rethinking Analog: Digitally Dri-ven Analog Design.

Abstract: As we continue to scaleCMOS technology, more chips inte-grate a small amount of mixed signalcircuitry on their large digital dies.Since transistors are getting worse,and the specs for the analog are get-ting tighter, all these blocks usenumerous cheap digital gates to"improve" their analog performance.This talk will discuss a new researchprogram we are starting at StanfordUniversity to try to rethink analogdesign. The first step is to realizethat digital correction is here to stay,

From left, Richard C. Jaeger, SSCS Pres-ident, Jan Van der Spiegel, SSCS Chap-ters Chair and Wilhelmus Van Noije,Chair of SSCS-South Brazil in conver-sation at the SSCS Chapter Luncheon.

SSCS-Seoul chapter members from left: Prof. ChulwooKim, Prof. Suki Kim, Prof. Sung-Mo Kang, Prof. SangsigKim, Prof. Cheol Jin Lee, and Prof. Jinyong Chung.

From left: Seoul chapter Vice President Jeong-Taek Kong, Prof.Jin-Ku Kang, Prof. Kwang Sub Yoon, Prof. Shin-Il Lim, Prof.Massoud Pedram, Mr. Sung-Hoon Bae, Prof. Hong-June Park,Mr. Young-Wook Yu and Prof. Chulwoo Kim at COEX, Seoul on26 October 2006.



Southern Taiwan a Growing Hubof Semiconductor Activity Although Taiwan has renown asone of the power houses globallyin the semiconductor industry, themajor spotlight has focused onnorthern Taiwan. The key factor isthe success of Science Park inHsinchu (eweb.sipa.gov.tw/en/index.jsp); many heavy weightsemiconductor foundries are locat-ed in the Science Park or nearby.Due to the magnetic effect of sucha success, a similar phenomenonis found in the Taiwan academiccircle. The focal point of semicon-ductor research, including ICdesign and process technology,has long been dominated bythose universities located close tothe Science Park, e.g., NTU(National Taiwan University),NCTU (National Chiao Tung Uni-versity), and NTHU (NationalTsing Hua University).

However, ever since the NationalSi-Soft Project, propelled by the Tai-wan authority, kicked off in 2002and Southern Taiwan Science Park(STSP, which is located in TainanCounty, www.stsipa.gov.tw/web/)

was officially founded in 2003,many semiconductor companieshave either established branchoffices or foundries in STSP. Inthe mean time, many potentialresearchers and engineers havescattered over the soil of southernTaiwan, either becoming faculty ofuniversities nearby, e.g., NationalCheng Kung University (NCKU),National Sun Yat-Sen University(NSYSU), and National ChungCheng University (CCU), or engi-neers in the branches of semicon-ductor companies.

Therefore, it seemed to be theright moment to set up a solid-state circuit forum to enhance theinfluence of IEEE as well as SSCSin this area.

How the Tainan Chapter BecameReality In late 2006, when I discussed thepossibility of founding a new Chap-ter of SSCS with one of my col-leagues, Prof. Tzyy-Sheng Horng, heencouraged me to get such a greatidea going. Besides, he advised meto inform graduates of our instituteto join SSCS such that SSCS would

become a significant forum in thearea of southern Taiwan.

Then I contacted Prof. Shen-Iuan Liu, who is the acting SSCChapter of IEEE Taipei Section,and Prof. Chorng-Huang Wang,who has long been involved withSSCS, to ask for their adviceregarding the ups and downs of anew Chapter in southern Taiwan.Both of them gave me every warmand positive response, and evensuggested that I attend 2006 A-SSCC in Hangzhou, China, duringNov. 13~15, 2006, to meet commit-tee members of SSCS. However,due to my tight schedule at thatmoment, I did not make the trip.Nevertheless, I also consulted sev-eral professors in different univer-sities who were members of SSCSand involved in different SSCS-endorsed conferences to learnwhat they thought about thenecessity of such new Chapter. Tomy surprise, almost everyone waslooking forward to seeing such aforum. These professors include:Prof. Ming-Hwa Shew and Prof.Ya-Hsin Hsueh of National YunlinUniversity of Science & Technolo-

A Chapter Is Born in Southern Taiwan Prof. Chua-Chin Wang, National Sun Yat-Set University, Kaohsiung, Taiwan, ccwang@hinet

and is pretty cheap. So the firstresearch question is can we buildmostly “digital” analog subsystems,and are there power/design timeadvantages in this approach. Sincethere will be some analog circuitrythat remains, the second researchquestion is to try to create a designsystem that makes using mixed-signalblocks more like using digital macros-- each cell comes with a validationscript, and a set electrical rules check-ers that ensure the design assump-tions are actively checked every timeit is used. Our goal in this section is tocreate robust mixed signal cells thatcan be used in many differentdesigns. More importantly this toolshould provide management feed-

back on when redesign of an analogcell is really needed, and prevent sim-ple chip errors from reappearingwhen a new designer redesigns anexisting block.

A profile of Dr. Horowitz may befound in the SSCS Newsletter ofNovember 2005: www.ieee.org/ por-tal/pages/sscs/05Nov/Horowitz.html

Santa Clara Solid-State CircuitsChapter concluded another successfulyear in 2006: We held ten well-attend-ed technical meetings. As ProgramsChair, I always tried to bring topics ofgreat interest to our audience and toinvite the best speakers we can get.We have been quite successful.

We held our officers election for

2007. I was able to convince LuizFranca-Neto, a very good profession-al and a friend of mine to volunteerfor our chapter as an officer. Healready serves in the MTT chapter. Ialso had success as Santa Clara Val-ley IEEE Executive CommitteeAwards Chair. One of my proposalsfor IEEE Region 6 Awards was ful-filled: National Semiconductorreceived the R6 Company of the Year2006 Award for Community Service.I organized a nice Ceremony andgranted the Award to the Companydesignated VP of Engineering.

I speak for all our IEEE mem-bers in thanking you for support-ing our Chapter.

Best wishes for 2007!

CHAPTERS


CHAPTERS


gy, Prof. Po-Ming Lee of SouthernTaiwan University of Technology,Prof. Chingwei Yeh and Prof.Shuenn-Yuh Lee of NationalChung-Cheng University, Prof. Bin-Da Brian Liu and Prof. Kuen-JongLee of National Cheng Kung Uni-versity.

Besides searching for supportfrom university campuses, I alsoturned my eyes to local semicon-ductor industrial links, particu-larly IC design houses. Dr. Yih-Long Tseng and Mr. Hon-YuanLeo of Himax Display, Inc.( w w w . h i m a x d i s p l a y . c o m )expressed their interest in support-ing SSCS activities, as did Mr. Tian-Hau Chen of Himax Technologies,Inc. (www.himax.com.tw). HimaxDisplay, Inc. and Himax Technolo-gies, Inc., founded and owned byChi Mei Optoelectronics (CMO,www.cmo.com.tw), are among thetop five TFT-LCD manufacturers inthe world. The former is an ICdesign house focused on LCOSand related products, while the lat-ter is one of the major suppliers ofLCD driver IC world wide. Besidesthese IC design houses, BeeDarTechnology Inc. and Etrend Elec-tronics, Inc., both located in STSP,are possible partners that we canapproach.

Defiining the Chapter’s Mission Many research-oriented universi-ties or colleges are located aroundSTSP: •National Cheng Kung University •National Sun Yat-Sen University •National Chung-Cheng University •National Yunlin University of Sci-ence & Technology

•National Kaohsiung University •National Kaohsiung First Univer-sity of Science & Technology

•Southern Taiwan University ofTechnology

•Kun Shan University Lots of faculty in the EE or CS

departments in these universities orcolleges have thrown great effort

into the advanced research topic ofIC circuit and system designs.

Moreover, STSP itself is a welldeveloped industrial community.Notably, a total of over 6,000 engi-neers/managers with MS or Ph. D.degrees are spread around almost100 high-tech companies. Quite agreat portion of the elite RD taskforce could be SSC-related or atleast semiconductor-related. Thefollowing companies are consid-ered to be highly correlated toSSCS areas. •TSMC •Applied Materials Taiwan, Ltd. •BeeDar Technology Inc. •MPI Probe Inc. ST Branch •Taiwan Shintex Technology Co.,Ltd.

•Chip MOS Technologies Inc.Tainan Plant

•LAM Research Co., Ltd. •Etrend Electronics, Inc. •Acute Technology Corp.

A forum steered by IEEE SSCSwould be considered a good plat-form for the companies insideSTSP and the universities to knoweach other, especially becausemore IC-design houses are expect-ed to emerge due to the promotionand encouragement of the govern-ment-driving National Si-Soft Pro-ject. I’d like to see SSCS play a sig-

nificant role in this area. But first we need to enhance the

visibility of SSCS such that its poten-tial contribution may be appreciated.As the founder of this new Chapter,I hope to proceed with several ini-tiatives to introduce people to eachother in the area of SSCS:1. Invite distinguished researchers/

lectures to southern Taiwan 2. Establish an email list of members 3. Set up a website for the Chapter 4. Co-sponsor IEEE-sponsored

conferences/symposiums 5. Hold workshops for members

Hopefully, the number of SSCSmembers can be increased signifi-cantly in the end of the term of thefirst Chapter Chair. In the longrun, I certainly hope the Chapterbecomes a great organization insouthern Taiwan.

About the AuthorChua-Chin Wang(M’90, SM’07) wasborn in Taiwan in1962. He received theB.S. degree in Electri-cal Engineering fromNational Taiwan Uni-

versity in 1984, and the M.S. andPh.D. degrees in Electrical Engi-neering from State University ofNew York in Stony Brook in 1988and 1992, respectively. In 1992, hejoined the Department of ElectricalEngineering, National Sun Yat-SenUniversity, Kaohsiung, Taiwan. Hehas been a professor since 1998 inthe same department. His recentresearch interests include lowpower and high speed logic circuitdesign, VLSI design, neural net-works, and interfacing I/O circuits.

He served as member of thetechnical committees of MST,Nano-Giga, VLSI Systems & Appli-cations of IEEE CAS Society since2006. In 2007, he was invited toserve as an Associate Editor ofVLSI Design. He is also the Gener-al Chair of 2007 VLSI/CAD Symp.in Taiwan.

Geographic locations of STSP andnearby universities in Southern Taiwan



CONFERENCES

Four books popular at recentISSCC meetings were best sellers atISSCC 2007:

CMOS: Circuit Design, Layout,and Simulation, 2nd Edition byR. Jacob Baker was a conferencebest seller for the third year in arow. According to comments bythe publisher, “this comprehensivepresentation of CMOS integratedcircuit design navigates readersthrough the process of imple-menting a chip from the physicaldefinition to the design and simu-lation of the finished product.”(www.ieee.org/portal/pages/sscs/04Oct/Books-SSCS.html)

Understanding Delta-Sigma DataConverters by Richard Schreierand Gabor C. Temes, also fromWiley, has been a top ISSCC sellersince 2005. In a review in the SSCSNewsletter of September 2005, IanGalton said, “It provides a ‘one-stopshop’ for engineers who want acomprehensive introduction to the

field of delta-sigma data converters.The authors are top researchers inthe field with extensive industrialand academic experience in delta-sigma data converter design. Theyare also excellent teachers, withvast experience lecturing the finepoints of delta-sigma data converterdesign to both university studentsand practicing engineers. As aresult, the book is well polished,easy to understand, and provides asolid and broad introduction to thefield.” www.ieee.org/portal/pages/sscs/05Sept/Schreier_and_Temes.html

Analog Design Essentials byWilly Sansen, which was Springer’stop seller at ISSCC 2006, “containsall topics of importance to the ana-log designer which are essential toobtain sufficient insights to do athorough job,” according to thepublisher’s website. “The bookstarts with elementary stages inbuilding up operational amplifiers.The synthesis of opamps is covered

in great detail. Many examples areincluded, operating at low supplyvoltages. Chapters on noise, distor-tion, filters, ADC/DACs and oscilla-tors follow,” all based on theauthor’s extensive experience inteaching. Slides are included on aCD-ROM as PDF files.

The Design of CMOS Radio-Fre-quency Integrated Circuits 2ndEdition, by Thomas H. Lee, wasone of the two top sellers forCambridge University Press atISSCC 2006 and sold comparably atthe conference in 2007.

Further commentary on the Leeand Sansen books may be found inthe SSCS newsletter review of bestsellers at ISSCC 2006: www.ieee.org/portal/pages/sscs/06Mar/Best_Sell-ers_at_ISSCC.html

Conference “Sleepers”Danielle Christensen, EngineeringEditor at Oxford University Press,had a hunch that Music and Math-ematics: From Pythagoras to Frac-

Classic Books Remain Best Sellers at ISSCC 2007Books on Music and Mathematics and Advanced Excel are Sleepers

Katherine Olstein, SSCS Administrator, [email protected]

CMOS: Circuit Design,Layout, and Simula-tion, 2nd Edition by R.Jacob Baker (Wiley-IEEEPress, 2004) ISBN: 978-0-471-70055-5, USD 99.95www.wiley.com

Understanding Delta-Sigma Data Convertersby Richard Schreier andGabor C. Temes, (Wiley-IEEE Press, 2004) ISBN:978-0-471-46585-0, USD99.95.

Analog Design Essentials, The SpringerInternational Series inEngineering and Com-puter Science, Vol. 859by Willy Sansen(Springer, 2nd printing,2006) ISBN: 978-0-387-25746-4, USD 99.00www.springer.com

The Design of CMOSRadio-Frequency Integrated Circuits,Second Editionby Thomas H. Lee (Cambridge, 2003) (ISBN-13: 9780521835398,USD 80www.cambridge.org


CONFERENCES


tals, by John Fauvel, RaymondFlood, and Robin Wilson, might beof interest at ISSCC but did notimagine it would turn out to beOxford’s best seller. www.oup.com

Equally surprising was Oxford’ssecond best seller: AdvancedExcel for Scientific Data Analysisby Robert de Levie. It is about“how you hot-wire Excel to dounusual things,” Ms. Christensensaid. De Levie, a chemist, is theauthor of more than 160 papers inanalytical chemistry and electro-chemistry and several books,including an early SpreadsheetWorkbook for Quantitative Chemi-cal Analysis (McGraw-Hill, 1992)and a textbook on the Principles ofQuantitative Chemical Analysis(McGraw-Hill 1997), according tothe Oxford website. He taught ana-lytical chemistry and electrochem-istry for 34 years at Georgetown

University and is now an emeritusprofessor associated with BowdoinCollege in Brunswick, Maine

The runaway best seller for Cam-bridge University Press wasElectromagnetics for High-Speed Analog and Digital Com-munication Circuits, by Ali M.Niknejad, University of California,Berkeley, ISBN-13: 9780521853507,USD 85.00, available March 2007.This news came as a surprise tothe author. “Most people wouldeasily admit to disliking E&M orhave good horror stories about anE&M professor in college whodrove them crazy,” he said in anemail interview, “but it's becom-ing so important in the design ofhigh frequency/high data rate cir-cuits and the IC community isbecoming aware of it.”

According to Cambridge, thebook “begins with a review of thebasics (the origin of resistance,capacitance, and inductance) andprogresses to more advanced top-ics such as passive device designand layout, resonant circuits,impedance matching, high-speedswitching circuits, and parasiticcoupling and isolation techniques.Using examples and applications inRF and microwave systems, theauthor describes transmission lines,transformers, and distributed cir-cuits and reviews state-of-the-artdevelopments in Si based broad-band analog, RF, microwave, andmm-wave circuits.”

An article by Prof. Niknejad isfeatured in this issue of the SSCSnewsletter.

Other top sellers at ISSCC 2007were:

Cambridge University PressWireless Communications, byAndrea, Goldsmith (2005) ISBN-13:9780521837163, £40.00.

Elsevier (www.elsevier.com)VLSI Test Principles and Architec-tures, by Laung-Terng Wang, Syn-Test Technologies, Inc., Sunnyvale,CA, USA, Cheng-Wen Wu, NationalTsing Hua University, Hsinchu, Tai-wan, Xiaoqing Wen, Kyushu Insti-tute of Technology, Fukuoka, Japan(2006) ISBN-13: 978-0-12-370597-6;USD 59.95. A reviewer on the Else-vier website said, “This is the mostrecent book covering all aspects ofdigital systems testing. It is a “mustread” for anyone focused on learn-ing modern test issues, test research,and test practices.” The book soldwell because testing represents“more than 50% of the developmentcycle these days,” said CharlesGlaser, Elsevier’s ISSCC representa-tive. Elsevier has more testing bookscoming, he said.

Elsevier’s second and third topconference sellers were:Demystifying Switched Capaci-tor Circuits, by Mingliang Liu(2006) ISBN-13: 978-0-7506-7907-7USD 59.95.Networks on Chips by GiovanniDe Micheli, Ecole PolytechniqueFederale de Lausanne, Switzerland,edited by Luca Benini, Universityof Bologna, Italy (2006) ISBN-13:978-0-12-370521-1, USD 59.95.

McGraw-Hill (www.mhprofes-sional.com)Charge Pump Circuit Design byFeng Pan and Tapan Samaddar(2006) ISBN: 007147045X /9780071470452, USD 99.95 sold best.This book is “The first-ever guide todesigning and implementing chargepumps for today’s low-cost, high-performance mobile devices,” saidNicole J. LeBlanc, McGraw-Hill’smarketing manager.Phase Locked Loops: Design,Simulation and Applications5 by

Music and Mathematics: FromPythagoras to Fractals, by JohnFauvel, Raymond Flood, andRobin Wilson (Oxford, 2006)ISBN-13: 9780199298938, USD32.50.

Advanced Excel for ScientificData Analysis by Robert de Levie(Oxford, 2004) ISBN-13:9780195152753, USD 59.50.



CONFERENCES

Roland E. Best (2003) ISBN0071412018 USD 79.95) “remains theyardstick by which all other circuitreferences are measured,” Ms.LeBlanc said. Roland E. Best is a“world-renowned authority withexperience enough to know thequestions you would ask.” McGraw-Hill will publish the 6th edition of thisclassic reference in September 2007.Embedded Core Design withFPGAs by Zainalabedin Navabi(2006) ISBN 0071474811, USD99.95. Prentice Hall(www.prenhall.com)

The Art of Analog Layout, byAlan Hastings (2005, ISBN-13: 780131464100, USD 131.00).

Digital Integrated Circuits, byJan M. Rabaey, Anantha Chan-drakasan, and Borivoje Nikolic (2003, ISBN-13: 9780130909961,USD 135.00).

Solid State Electronic Devices,by Ben Streetman, University ofTexas at Austin and Sanjay Banerjee, University of Texas atAustin (2006, ISBN-13: 9780131497269, USD $135.00).

SpringerData Converters by Franco Mal-oberti (2007) ISBN: 978-0-387-32485-2A, 99.00).RF System Design of Trans-ceivers for Wireless Communica-tions by Qizheng Gu (1st ed., 2005.Corr. 2nd printing, 2006, ISBN: 978-0-387-24161-6 USD 89.95).

Wiley-IEEE Press Physics of SemiconductorDevices, 3rd Edition by Simon M.Sze, Kwok K. Ng (2006) ISBN: 978-0-471-14323-9, US $125.00.

“Digital RF: Fundamentally a NewTechnology or Just MarketingHype?” was the title of Tuesdaynight’s evening session at ISSCC2007. This panel promised to high-light the classic battle of digital vs.analog, and I always like a goodfight to end a long day of sessions.

With moderator Tom Lee givinga rousing “Welcome Geeks” intro-duction to the packed room, Iknew the discussion would belively. As the crowd settled down,

it was clear the analog and RFdesigners would put up a goodfight against the invasion of digital.

In their opening remarks, thewell-known panelists quickly dif-fered on the first question posed“What is Digital RF?”

Rudolf Koch from Infineonpointed out that up to 20 radios ona chip was imminent, and thecomplexity of design may be alle-viated by digital techniques. Pro-fessor Asad Abidi and Intel’s Krish-

namurthy Soumyanath (Souyma)agreed that a true digital RF solu-tion should mean SoftwareDefined Radios or CognitiveRadios – that uses DSP techniquesto make a highly flexible universalradio.

Dave Welland from Silicon Labswas unimpressed with today’s dig-ital radio that took the low fre-quency parts and turned them dig-ital and would only be awestruckif the LNA or VCO that are tradi-

Digital and Analog Designers Spar at ISSCC EveningPanel SessionAlice Wang, Senior Member of Technical Staff - Texas Instruments, [email protected]

Multiple radios on a chip is imminent from Infineon, saidISSCC panelist Rudof Koch.

According to Professor Asad Abidi and Intel’s KrishnamurthySoumyanath (Souyma), a true digital RF solution shouldmean Software Defined Radios or Cognitive Radios.


CONFERENCES


tionally difficult to design wentdigital.

Satoshi Tanaka from Hitachimulled over the difficulty of design-ing RF circuits in Deep Submicrontechnologies with their digitalnoise, low voltage levels and com-plexity. Very quickly the openingstatements degraded into “TheWorld versus Texas Instruments”(who coined the term “DigitalRadio Processor (DRP)”). BogdanStaszewski from TI proposed thatthe definition of Digital RF meantthe ability to scale RF from node-to-node like digital and stood behindthe fact that the “marketing hype”can’t refute that DRP is already atvolume production in 90nm.

The floor was opened to theaudience whose questions rangedfrom how to educate students both

in digital and analog to wonderinghow many on-chip inductors arereally needed for those 20+ radios(Abidi=3, Souyma=1). The conver-sation also turned to the businessside – how to fill fabs, how tokeep your high margins for analogvs. low margins on digital, andtime-to-market for new RF stan-dards. It was clear that everyone inthe audience had a pretty strongopinion because proponents anddenigrators alike stepped to themike to wax on about “digital RF”in their lives.

At the end of the night no onewanted the fight to end as moder-ator Tom Lee closed out the ses-sion. With no real conclusion, theanswer is not “zero” or “one”(excuse the pun) and the debatewill rage on about digital RF, reali-

ty or marketing hype?The panelists’ topics were:

• Asad Abidi (UCLA) “SDR: OnceObjecf of Derision, Real Todaywith Digital RF”

• Rudolf Koch (Infineon, Munich,Germany) “Digital High Frequen-cy or High Frequency Marketing?”

• Krishnamurthy Soumyanath (Intel,Hillsboro, Oregon) “Digital Tech-niques will Imporve Multi CommIntegrated Circuits”

• R. Bogdan Satszewski (TI, Dal-las, TX) “Winning Recipe: DigitalTurns RF and RF Turns Digital”

• Satoshi Tanaka (Hitachi, Tokyo,Japan) “Fusion of standard RFAnalog and Digital are Essentialfor Future RF LSI”

• David Welland (Silicon Laborato-ries, Austin, TX) “Some Assem-bly Required”

VLSI Circuits Symposium Celebrates 20thAnniversary in JuneSreedhar Natarajan, [email protected]

The International Symposiumon VLSI Circuits will be heldon June 14-16th, 2007 at the

Rihga Royal Hotel, Kyoto, Japan.The Symposium consists of threedays of technical presentations andinformal evening rump sessions onVLSI circuit design. Following thetradition of the past several years,the Circuit Symposium will followthe Technology Symposium at thesame location.

This year will mark the 20thanniversary of the first Circuit Sym-posium. The Symposium hasestablished itself as a major inter-national forum for presenting andexchanging important ideas andnew developments in VLSI circuitdesign. The scope of the Sympo-sium covers all aspects of VLSI cir-cuits, including signal processing,digital, processors, FPGAs, analog& mixed signal RF circuits, memo-ry circuits, and has been expandedto include new concepts in VLSIdesign, such as MEMS, novel mem-

ory, quantum computing. The cir-cuit innovations to be presented atthis Symposium will form the foun-dation for future developmentsand advances in the semiconductorindustry. Contributions to the Sym-posium come from both industryand academia around the world.

This year the technical programcommittee reviewed 342 submis-sions to the conference and chose103 papers for presentation and

publication at the Symposium.Paper selections were based ontechnical quality and impact to thedesign community, with represen-tation from industrial and academ-ic institutions from around theworld. Considering the changingtechnological demands, we hopeyou will attend and participate indiscussions at the technical ses-sions, rump sessions and shortcourses, featuring new and innova-

From left, Kazuo Yano, Circuits Symposium Program Chair, Stephen Kosonocky,Circuits Symposium Co-Chair, Katsu Nakamura , Circuits Symposium ProgramCo-Chair, and Sreedhar Natarajan, Publicity Chair, met at ISSCC 2007 to planthe June Symposium on VLSI Circuits.



CONFERENCEStive discussions of leading-edgeconcepts at this conference.

About the VenueThe Rihga Royal Hotel is locatedwest of Kyoto, the old capital ofJapan, which attracts many visitorsfrom all over the world. The JRKyoto station was totally renovatedand modernized in 1997, so nowyou can enjoy the combination of amodern station building along withthe traditional Kyoto cityscape. Forfurther information, please visit theWeb site of the Kyoto ConventionBureau (which also provides a lookat the history and culture of Kyoto)at web.kyoto-inet.or.jp/org/hel-lokcb/index.html.

Technical HighlightsPapers to be presented at the Sym-posium will cover latest and inter-esting circuit design concepts fordigital, memory, analog, wireless,and wireline applications. Thehighlights include: • A number of multicore and con-

figurable SoC implementationsincluding an HDTV real timeencoding SoC, a multi-purposeconfigurable SoC with nine CPUsand two Matrix processors, anLDPC decoder design, and a het-erogeneous multicore, dynami-cally-reconfigurable with twoCPUs and two Dynamic Recon-figurable Processors. (Session 2)

• High frequency design takes sev-eral forms in the High Perfor-mance Processing session. Thissession has a wide variety ofpapers from a 65nm 5.1Ghzrouter chip, a FIR filter with on-chip 1Ghz resonant clock in fullyASIC flow, and synthesizabledesigns to reach 4Ghz. (session 5)

• Applications such as softwaredefined radios, ultra-widebandradio and hard-disk drivesrequire high sampling rateADCs. Multiple papers discusstime interleaving and a flashdesign to realize gigahertz sam-pling rate ADCs targetedtowards digital-TV and satellitereceivers, as well as UWB radios

followed by a high speed DACfor backplane communication.Most designs are at state-of-the-art 90nm technologies that posethe additional challenge ofdesigning at lower supply volt-age. (Session 7)

• The state of the art microproces-sors and SOCs (System On aChip) require the K-bit order ofelectrical-fuse-memory-array onthe die as well as the high-den-sity of SRAM cells fabricated bydeep submicron CMOS tech-nologies. To overcome thesechallenges, interesting circuittechniques will be reported inthe 2007 Symposium. (Session 8)

• IBM will demonstrate a >10Xdensity compact eFUSE pro-grammable array configured as a4Kb one-time programmableROM. The 1T1R cell size is only6.2μm2 using 65nm SOI CMOS.On the SRAM side, a novel fail-ure model of multi-bit-errorcaused by a neutron inducedsingle event upset will be report-ed and relaxed ECC guidelineswill be given by Infineon Tech-nologies. (Session 8)

• “MM-Wave Building Blocks”focusing on millimeter waveCMOS RFIC designs for high-speed communication and radarapplications. (Session 17)

• The Dynamic and Non-VolatileMemory session will host themost advanced state of the artdevelopments in architectureand circuit techniques in DDR3DRAM’s, MLC NAND Flash,Phase Change Memory, andEmerging Memory TechnologyDevices such as the CBRAM.(Session 18)

• Various innovative clock genera-tion schemes like PLLs, DLL andtime-to-digital converters arecovered in multiple sessions.

• The SRAM session discusses var-ious embedded SRAM cachearrays to support low-voltageand high-speed operation, atand beyond 65nm technology.Industry is shifting focus to 8TSRAM designs instead of con-

ventional 6T SRAMs to achievelow voltage functionality. TheSRAM session discusses variousdual port 8T SRAMs and 65nmSOI SRAMs. (Session 24)

Invited SpeakersInvited papers presented by aca-demic and industry leaders arealways the pinnacle of the Sympo-sium, focusing on both technicaland business implications of tech-nological changes.

This year’s symposium includesfour invited talks by distinguishedspeakers. Their titles, listed inalphabetical order by speakername, are: • “Future of microprocessors

enabling game consoles,” byJeff Brown (IBM)

• “Future vision of mobile phonetechnology as the driver of thisindustry,” by Koji Chiba (NTTDocomo)

• “Fundamental Limits of PowerConsumption in Analog Cir-cuits,” by Prof. Hae-Seung Lee(MIT)

• “Recent rapid progress in organ-ic, printable, foldable electron-ics” by Prof. Takao Someya (Uni-versity of Tokyo).

Rump SessionsEvening rump sessions are organ-ized around controversial topicsand experts are invited to presenttheir divergent views. All aspectsof the controversy are explored,and a spirited discussion ensues;active audience participation isencouraged! This year the rump

Tadahiro Kuroda, Symposium Chair(left), with plenary speaker Hae-Seung (Harry) Lee.


CONFERENCES


session topics for the Circuits Sym-posium are:(1) CMOS scaling: Where will

economics set the “end ofthe line”?Continued scaling is largelybeing driven by the fact thatscaling is still reducing the costof a transistor, a trend that isquickly changing as toolingand fabrication challengesmultiply. Where will econom-ics set the “end of the line”?What players or markets willdetermine this “end of the line”scaling node?

(2) Analog scaling and SoC inte-grationIn this special evening sessionfour speakers with very differ-ent backgrounds will discussthe impact of technology scal-ing on analog and RF design.How can we still design effi-cient analog circuits in nanome-ter CMOS and what are thedesign challenges in this scal-ing? What technology shouldwe choose for RF: BiMOS orCMOS and SiP or SoC?

Special Feature: Joint Rump Ses-sion (Technology and Circuits)A special feature of the Symposiumis the one-day overlap in the

schedules for the InternationalSymposium on VLSI Technologyand the Symposium on VLSI Cir-cuits. This is an excellent opportu-nity to meet with members of theopposite discipline to share experi-ences, issues, and ideas for futureimprovements. In addition, there isalso a joint rump session organizedby members of both the Circuitsand Technology committees. Thisyear’s topic is “Is compact model-ing measuring up to the challengeof the DFM era?”

VLSI Circuits Short CourseVivek De of Intel and MasayukiMizuno of NEC have organized anexcellent one-day Short Course,“Design for Variability in Logic,Memory and Microprocessors” onWednesday, 13 June, 2007. TheShort Course includes talks byexperts in the field, coveringdesign techniques for managingvariability.

This is a condensed one-daycourse intended to give attendeesan excellent overview of the topicas well as to provide the latestdevelopments in the area. This isa rare opportunity to hear timelypresentations describing work in atechnical area given by recog-nized leading practitioners and

researchers who teach others todo what they do best.

VLSI Symposium WorkshopHiroki Ishikuro and Foster Dai haveorganized an excellent workshop on“Advanced Topics on Multi-StandardWireless Transceiver RFIC Designs.“This workshop will be held on 15June, 2007. This tutorial includes talksby experts in the field starting with adiscussion on multi-com radios formulti-standard coexistence continuingto focus on multi-band RF front-endand multi-band frequency synthesisRFIC designs. The second half of theworkshop presents advanced topicsincluding software defined radio, dig-ital-video-broadcast receivers, andMIMO wireless transceiver SoC’s.

Further InformationFor questions about hotel reserva-tions contact:Rihga Royal Hotel KyotoHorikawa-Shiokoji, Shimogyo-ku,Kyoto 600-8237, Japan Tel: +81-75-341-1121Fax: +81-75-341-3073

For registration and other informa-tion, visit the VLSI Symposia homepage at: www.vlsisymposium.orgor see more contact information inthe SSCS Events Calendar.

In the article entitled “The Second A-SSCC ConsidersChallenges for the e-Life” in the Winter ’07 issue, thecaption under the picture of the A-SSCC student

design contest winners mistakenly read as if their left toright position indicated their rank. The A-SSCC StudentDesign contest is not ranked. All three were winners withno ranking.

SSCS Members at ISSCC Receive Replacement DVDArchive DisksThe SSC Digital Archive pair of DVDs distributed to SSCSmembers at the ISSCC was mislabeled: The disk misla-

beled “Update 2006” actually contains all the files from1955 to 2000. And the disk mislabeled “Foundations”contains all the most recent files from 2001 through 2006.

Replacement disks were mailed to postal addressesprovided at the time of ISSCC registration. The newdisks are date-stamped with a “March 2007 Issue” to dif-ferentiate them from the erroneous disks and can bestored in the original jewel case.

If you are an SSCS member who attended the ISSCCand have not received your replacement disks, pleasecontact [email protected] and provide your member num-ber and postal address.

Corrections



CONFERENCES

Mark your calendar andmake reservations for the2007 IEEE RFIC Sympo-

sium (www.RFIC2007.org ) to beheld in Honolulu, Hawaii fromJune 3rd through June 5th. RFIC issponsored by the IEEE Solid-StateCircuits, Microwave Theory andTechniques (MTT), and ElectronicDevices Societies.

Once again, this year’s RFICSymposium continues its traditionas the premier conference show-casing the latest advancements andinnovations in RF integrated cir-cuits, wireless sub-systems, broad-band communications, and circuittechnology for emerging wirelessapplications. The symposium con-tinues to provide a forum for someof the most innovative advance-ments from both industry and aca-demia.

Plenary Session to Focus on Wire-less and Future RF ApplicationsA Plenary Session will be held onSunday evening, with keynoteaddresses given by two renownedindustry leaders. The first speaker,Charles Persico, Senior Vice Presi-dent of Engineering at QualcommInc. will present a talk entitled“Wireless Convergence - Your

Phone is Not Just a Phone Any-more.” The second speaker,Dwight C. Streit, Ph.D., Vice Presi-dent, Electronics Technology,Northrop Grumman Space Tech-nology, will discuss “TechnologyDirections for Future RF Applica-tions.” Three student paperawards will also be presented inthe Plenary Session. The highlyanticipated RFIC Reception willfollow immediately after the Ple-nary Session, providing a relaxingtime for all to mingle with oldfriends and catch up on the latestnews.

Program to Offer a Vast Array ofRFIC Technology

The vitality of the RFIC commu-nity appears stronger than ever, asan all-time record number of man-

uscripts were submitted to thisyear’s conference. The TechnicalProgram Committee worked dili-gently to provide a superior venuefor this vast array of RFIC technol-ogy. The symposium will feature15 workshops and tutorials onSunday, June 3rd. In addition, 30oral sessions, an Interactive Forum,and two panel sessions will begiven on Monday and Tuesday,covering nearly all facets of RFICtechnology.

When you think of the wordHawaii, what first comes to mind?Sunshine, beautiful beaches,snorkeling, and a great place tovisit are immediate thoughtsmany of us would have. In addi-tion to all of this, add one morethought: three days of some ofthe most remarkable RFIC tech-nology to be found anywhere inthe world.

On behalf of the RFIC TechnicalProgram Committee, we look for-ward to seeing you at the 2007RFIC Symposium. Mahalo.

Luciano Boglione, RFIC General Chair

Tina Quach & Jenshan Lin,RFIC Technical Program

Chairs

Persico and Streit to Speak at RFIC Symposium inHonolulu, 3-5 June 2007 David, Ngo, RFIC 2007 Publicity Chair



CEDA CurrentsNews from the IEEE Council on Electronic Design Automation

CEDA Distinguished SpeakerVideos AvailableIEEE CEDA announces onlinevideos of talks by distinguishedspeakers, available at www.ieee-ceda.org/lectures.html. Recentadditions include a talk by FrancesA. Houle of the IBM AlmadenResearch Center on professionalethics, one by Janusz Rajski onembedded deterministic test, andZhenhai Zhu’s “A Fast StochasticIntegral Equation Solver for Model-ing the Rough Surface Effects.”

IEEE Fellows Elected in 2006 forCEDA-Related ActivitiesThese individuals have been elect-ed as IEEE Fellows for contribu-tions in the following CEDA-relat-ed areas.• Luca Benini, University of

Bologna, Bologna, Italy: Designtechnologies for low-powerdesign of integrated circuits andsystems

• Bhargab B. Bhattacharya, IndianStatistical Institute, Calcutta: Test-ing and design of digital ICs

• Abhijit Chatterjee, Georgia Insti-tute of Technology, Atlanta: Test-ing of analog and mixed-signalcircuits

• Anirudh Devgan, Magma DesignAutomation, Austin: Electricalanalysis, and simulation of ICs

• Kenneth S. Kundert, Designer’sGuide Consulting, Los Altos:Simulation and modeling of ana-log RF and mixed-signal circuits

• Sandip Kundu, University ofMassachusetts, Amherst: Designof IC test methods

• Gaetano Palumbo, University ofCatania, Catania, Italy: Analysisand design of high-performanceanalog and digital circuits

• Ruchir Puri, IBM Thomas J. Wat-son Research Center, YorktownHeights: Automated logical andphysical design of electronic cir-cuits

• Jose Schutt-Aine, University ofIllinois, Urbana: Modeling andsimulation of distributed circuitswith applications to signalintegrityThis is not a complete list of the

2007 IEEE Fellows. We apologize inadvance for any omissions. Pleasesee www.ieee.org/web/aboutus/fel-lows/new-fellows.html for the com-plete list.

IEEE TAB Approves CouncilCosponsorship of the IEEE PhilKaufman AwardThe IEEE Technical Activities Board(TAB) approved CEDA sponsorshipof the Phil Kaufman Award for Dis-tinguished Contributions to Elec-tronic Design Automation jointlywith the EDA Consortium. Thisaward honors an individual whohas significantly impacted the fieldof electronic design through contri-butions in electronic designautomation (EDA).

CEDA is also cosponsoring aDonald O. Pederson Award forthe best paper in IEEE Transac-tions on Computer-Aided Designof Integrated Circuits and Systemsand the William J. McCalla Awardfor the best paper at ICCAD, andprovides nominations and inputfor the IEEE Piore Award. Togeth-er, these awards represent excel-lent mechanisms to recognizecontributions from our communi-ty. Please send your suggestionsand nominations to CEDA admin-istrator Barbara Wehner [email protected].

Upcoming EventsDesign, Automation and Test inEurope Conference (DATE)16-20 April 2007Nice, Francewww.date-conference.com

16th International Workshopon Logic & Synthesis (IWLS)30 May - 1 June 2007San Diego, Calif.www.iwls.orgPaper submissions deadline: 3March 2007

5th ACM-IEEE InternationalConference on Formal Methodsand Models for Codesign (MEM-OCODE)30 May - 1 June 2007Nice, Francememocode.irisa.fr

7th International Forum onApplication-Specific Multi-Processor SoC (MPSoC)25-29 June 2007tima.imag.fr/mpsocHyogo, Japan

15th VLSI-SOC15-17 October 2007Atlanta, GA, USAwww.vlsisoc2007.gatech.edu

For more information regardingsponsorship of conferences andmeetings, contact Richard Smith,[email protected].

CEDA Currents is a publication ofthe IEEE Council on Electronic DesignAutomation. Please send contribu-tions to Kartikeya Mayaram([email protected]) or PreetiRanjan Panda ([email protected]).

SSCS NEWS



IEEE SSCS will Focus on Strategic Planning in 2007AdCom Highlights

At its biannual meeting on 11 February, 2007 in San Francisco, the Sold-State Circuits Society AdCom votedto launch a process to set goals and a strategic directions for the Society and to participate in a newly organ-ized Council on Engineering Management.

Ad Hoc Committee Formed for Goal SettingWith the Society 10 years old in 2007, Society Presi-dent Dick Jaeger charged the AdCom to articulateSociety goals. Some Society activities have steadilygrown in the last decade, while others have shownwide swings.

The Journal page count, the numbers of Chaptersand the number of technically co-sponsored meetingshave all shown steady growth. The Journal page counthas increased from 2,000 to 3,100 pages, while Chap-ters have grown from none to 59 and technically co-sponsored meetings have grown from 5 to 11.

In contrast to the steady growth of these activities,Society financial reserves, which reflect general finan-cial markets dipped from their previous 1999 high of$3.25 million to $1.1 million in 2002, but havereturned to an even higher level of $4 million.

Membership, on the other hand, peaked in 2001 at14,500 members, but has declined to 11,000 in 2006,the approximate size of the Society when it wasformed in 1997. This drop in membership is believedto be a measure of the success of IEEEXplore in sup-plying technical articles through employer subscrip-tions rather than individual memberships. Engineersinterested in the field of Solid-State Circuits continueto read the Journal of Solid-State Circuits in record

numbers, which can be verified by download countsof pdf files in Xplore. But readers no longer have tojoin SSCS to read the Journal online if their employ-er subscribes, saving out-of-pocket money whilebenefiting from the support of industry and academ-ic subscriptions.

These trends deserve closer examination. AtJaeger’s suggestion, the AdCom agreed to launchan AdHoc Committee to focus on goals and strate-gic directions for the Society. Appointed chair ofthe new committee, Rakesh Kumar (also SSCSTreasurer) said that two areas of AdCom concernthat the committee may address are maintainingthe quality of the Society’s sponsored conferencesand publications and devising “out of the box”ways to increase membership. The AdHoc commit-tee will be comprised of a representative fromeach of the four standing AdCom committees(Meetings, Publications, Membership, Education)plus two or three at-large members. The group willprepare an initial report with recommendations forthe AdCom in August.

What’s new at the IEEE Board?IEEE 2007 President-Elect Lew Terman gave a shortreport on the main focus items and new directions

SSCS AdCom members who met in San Francisco on 11 Feb. 2007 were: Top row, from left: Jan Sevenhans, Domine Leeanarts,Paul Hurst, Bram Nauta, Kevin Kornegay. Third row, from left: David Johns, Mehmet Soyuer, Rakesh Kumar, C.K. Wang, Un-KuMoon, Larry Starr, Sreedhar Natarajan, Tadahiro Kuroda, Anne O’Neill, K. Nagaraj. Second row, from left, Bruce Hecht, HarryLee, Bill Bidermann, C.K. Ken Yang, Takayasu Sakurai, Anantha Chandrakasan, John Corocoran, Terri Fiez, Akira Matsuzawa.Front row, from left: Katherine Olstein, Wanda Gass, Ali Hajimiri, Tom Lee, Dick Jaeger, Steve Lewis, Lew Terman, Willy Sansen.

SSCS NEWS



which he sees at the IEEE Board of Directors level for2007. He noted that the IEEE Board meetings wouldbe held during the week of February 12th, and therewould be more information available after the meet-ings. The main items from IEEE Board meetings arereported to IEEE members through the Institute. Hisreport follows:

Past-President Mike Lightner is continuing his focusin two areas he initiated in 2007. The first is IEEEmembership. He started investigation of an alternativemembership model with different levels of benefitsand cost. Surveys have been made of current mem-bers (all grades), former members, and non-members.Given a choice, there is no single benefit everyonewants, and over 100 benefits that at least some mem-bers want. The current focus is on evaluating thealternative models and their financial impact.

Past-President Lightner is also heading the effort toestablish a formal presence in China. While the IET(formerly the IEE in the UK) was able to register itselfas a not-for-profit organization, the China governmentis now holding up such registrations indefinitely. Apossible alternative is to register as a for-profit organ-ization until the not-for-profit status becomes avail-able. This does not appear to have any downside, butis being looked at closely.

2007 President Leah Jamieson is focusing on threeareas: membership, strategic planning, and more effi-cient board meetings and board series. Membershipincludes growth of the overall Institute membership,the increasing percentage of non-US members, reten-tion of student members after graduation, and Societymembership. Membership was the subject of a facili-tated strategic planning meeting attended by around40 volunteer leaders from across the Institute duringthe Board Series week, focusing on the value of mem-bers, their role in IEEE, and long term goals.

Two half-day sessions have been set aside at theBoard Series for strategic planning, one on member-ship, noted above, and the other on long term plan-ning for the Institute. The latter was preceded by twofacilitated sessions, and the sessions are expected tocontinue at the two remaining 2007 Board meetings.The goal is to develop a clear view of where IEEEshould be in 10-15 years, how it should get there, andwhat are the more focused shorter term actions to getthere. It is expected that the plan will be reviewedyearly. President Jamieson’s focus on strategic plan-ning is very welcome, as it has not been receiving suf-ficient attention.

Efficient IEEE Board Meetings are very important,since they are the three times a year the IEEE Boardgets together for face-to-face meetings and interac-tion. Under the new approach, the more importantitems are moved to the beginning of the meeting toensure that they are addressed early. Current sched-

uling has the Board and ExCom meeting on Wednes-day and Sunday, requiring Board members to stay theintervening days, a major inconvenience. The prosand cons of scheduling the Board meetings for Satur-day and Sunday are being investigated.

Other items:• A new New Initiatives process that allows submis-

sion and rapid approval/funding of new initiativesaround the year, and adds a new category of SeedGrants at a much lower level of funding to allowquick exploration of high risk pilot programs.

• A proposal to restructure the Infrastructure Over-sight Committee with an increased membership,three year terms, and the requirement for memberfinancial expertise. The committee will be chargedwith delving deeply into the IEEE Indirect Infra-structure Charge (overhead), the rise of which hasbeen a concern to IEEE operating units.

• A new method of funding the Indirect InfrastructureCharge, based on taking a fraction of the IEEEpackaged products net (primarily from Xplore/IEL).This is expected to be revenue neutral for 2008.

• The new Business Management System (BMS) is ontrack for roll-out for the 2008 renewal cycle. This isa complete revision of the business software usedfor membership related activities, sales, and Insti-tute information.

• A new method of funding for the Foundation,Awards Board, and History Center, which involvesbudgeting up to 1.5% of the average reserves overthe previous three years. This is revenue neutral for2008. Including the 3% for New Initiatives, thisgives IEEE a “spending rule” of 4.5% of the Institutereserves.

• Expert Now is off to an excellent start and will beavailable to members this year. The Education Activ-ities Board is doing a strong world-wide effort onaccreditation. EAB also has a strong focus on attract-ing pre-college students to science, engineering, andIT, and is working with universities to develop cur-ricula leading to degrees in the Services area.

• Financially, 2007 was the fourth good year in a rowfor the IEEE, with the addition of about US$30M tothe reserves bringing them to just over US$200M.Reserves have more than doubled since the lowpoint of US$91M at the end of 2002. The need fora long range plan on the growth and/or wise use ofreserves is apparent.

SSCS Joins the new Engineering ManagementCouncilRakesh Kumar reported on the IEEE Board’s approvalof the change of the IEEE Engineering ManagementSociety to the Engineering Management Council. Themajor difference between IEEE Societies and Councils isthat Societies have members, while technical Councils

SSCS NEWS



do not have members, but are governed by representa-tives from the IEEE societies which are members of theCouncil; thus a Council is made up of the member soci-eties. IEEE technical Councils generally deal with disci-plines which are broadly spread across a number ofSocieties. In this case, the EMS governance felt thatengineering management is a skill that transcends spe-cific technical disciplines, and Council status would putthem in a more favorable position to impact the fullspectrum of IEEE societies and members.

In recent surveys, IEEE members have put man-agement skill high on their list of important careergoals, along with computer skills, communication,and circuits and systems skills, as Robert A. Lutz, for-mer President and Chairman of Chrysler Corporation,pointed out in “Engineers……. Write it up.”

The Engineering Management Council will improvethe opportunity to help members expand beyond thetechnical area through training and awareness of leader-ship, management, and communication issues. SSCSjoins 10 other IEEE Societies in forming the new Council.The other Societies are: Aerospace and Electronic Sys-tems (AES), Circuits and Systems (CAS), CommunicationsSociety (ComS), Computer Society (CS), Electron Devices(EDS), Industrial Electronics (IES), Lasers and Electro-Optics (LEOS), Reliability (Rel), Signal Processing (SPS),and the Systems, Man, and Cybernetics Society (SMC).

The Journal and ConferencesThe Journal and Conferences continue to be the Soci-ety’s core vehicles to disseminate the latest in IC cir-cuits, and they are the primary focus of SSCS AdCom.Bernhard Boser, the Publications Committee Chair,reported on the excellent time to publication and man-agement of Nagaraj, the editor-in-chief of the JSSC,one of the fastest turnarounds in IEEE. AdCom votedthat the JSSC plan for 3,100 published pages for 2008.Bram Nauta of University of Twente, Netherlands willbe the next JSSC Editor beginning next summer.

Because SSCS sponsored conferences have animportant goal to provide new and unique results, amanuscript should not be submitted to more than one

at a time. Bill Bidermann will draft a pre-publicationpolicy for SSCS AdCom consideration, that willrequire authors to state they are not engaging in mul-tiple submissions. When approved by the AdCom atits meeting next September, the policy will be appli-cable to all the Society’s conferences.

The Meetings Committee, Chaired by AnanthaChandrkasan, reviewed metrics for 7 of SSCS 11 tech-nically co-sponsored conferences and endorsed threeupcoming.• BCTM 2007, the Bipolar/BiCMOS Circuits and

Technology Meeting which in 2008 will be collo-cated with the Compound Semiconductor IC Sym-posium (CSICS) in 2008

• DATE 2008, the Design Automation and Test inEurope

• Hot Chips 2007 – a Symposium on high-perform-ance chips sponsored by the IEEE Computer Soci-ety and its Technical Committee on Microproces-sors and Microcomputers.For more news of SSCS conferences check out the

online database:www.ieee.org/portal/pages/sscs/conf_list/conf_200

7.html

Society President Dick Jaeger (at left) attended the VLSI DesignSymposium in Bangalore, India in January 2007 with SreedharNatarajan (center), liaison between ISSCC and the conference,and Navakant Bhat (at right), the founder of the Bangalorechapter. They are standing in front of the ISSCC 50th Anniver-sary Musuem display at VLSI, which also traveled to the A-SSCC in November 2006 meeting in Hangzhou, China.

Call for Nominees for SSCS AdministrativeCommittee Election Petition Deadline is 1 August

Each year SSCS elects five members to the gover-nance of the Society on the Administrative Com-mittee (AdCom). The Bylaws of the Society guar-

antee a choice for members in the election by requiringthat the Nominations Committee prepare a slate of aminimum of 8 candidates for the 5 positions. SSCS mem-bers interested in running or nominating others musttheir recommendations along with their reasons for sug-

gesting a candidate to the Chair of the NominationsCommittee, Stephen H. Lewis, ([email protected]),by the end of February of the year of the election. Studentmembers are not eligible to run or vote. The NominationsCommittee begins its work in spring and will announcethe slate of candidates in the summer SSCS News.

The election is in the fall. The five nominees receiv-ing the highest number of votes of the Society mem-

SSCS NEWS



bership will be elected.There is also a petition process for interested parties

who are not endorsed by the Nominations Committee.

Nominees by PetitionAfter the announcement in the summer issue of the SSCSNews, of the slate of candidates from the NominationsCommittee, there is an opportunity to add petition candi-dates to the ballot. The statement of intent to begin thepetition process must arrive at the Society Executive office([email protected]) by August 1. It must be submittedwith the knowledge and agreement of the nominee. Thepetition candidate’s eligibility will be verified. The petitionprocess itself can be completely managed online underthe administration of the IEEE Corporate Office. Any soci-ety voting member who wishes to sign such petition maydo so electronically. A link to the petition site will be pro-vided on the SSCS website, sscs.org. Once a petitioner isposted on the site, he or she will remain up to receiveendorsement signatures for 30 days.

The number of signatures required is defined by IEEEBylaw I-308.16, as 2% of SSCS voting members at the timethe petition process begins. This is expected to be approx-imately 140 signatures. Such petitions must be submittedwith the knowledge and agreement of the nominee.

SSCS Bylaws are currently being revised to harmo-nize with these new IEEE petition procedures. IEEE

Bylaws for petition candidates were revised in 2005and supersede the previous Society rules.

AdCom Member Duties and ResponsibilitiesElected AdCom members are expected to attend thetwo administrative meetings each year. Much of theCommittee’s work is carried on by email, telephone,and fax throughout the year. The AdCom oversees theoperations of chapters, publications and conferencesincluding the Journal of Solid-State Circuits, the Inter-national Solid-State Circuits Conference, the CustomIntegrated Circuits Conference, the VLSI Circuits Sym-posium, and the Asia Solid-State Circuits Conference. Inaddition, the Society cosponsors or technically cospon-sors a number of other conferences and meetings.

The AdCom has responsibility for overseeing theseand for other potential future technical activities with-in the Society's field of interest.

Terms of Office• The term of office is three years beginning 1 Janu-

ary 2008. • AdCom members may be reelected to a second

consecutive term. Members who miss two consecutive AdCom meet-

ings shall be dropped from membership in the absenceof extenuating circumstances.

IEEE Partners with Knowlegde Master, Inc. to OfferMicroelectronics Courses in Mandarin Chinese

PISCATAWAY, NJ, 18 December 2006 - The IEEEhas partnered with Knowledge Master, Inc. tooffer IEEE members courses specific to microelec-

tronics, semiconductors, and integrated circuit design inMandarin Chinese. This partnership fulfills two impor-tant objectives of the IEEE: to serve the community ofpractitioners in the area of microelectronics – one of themost important, highly expanding, and technically excit-ing fields of electrical engineering – as well as to servea segment of IEEE’s practitioner population that residesin China.

Founded in 2004, Knowledge Master Microelectron-ics Institute, Inc. is a provider of online career devel-opment courses for Chinese or Chinese Americanworking professionals through its website at Knowl-edgeOnDemand.com.

Primarily focusing on the information services andinternet technologies industry, Knowledge Master,Inc., a California-based e-learning company, hasdeveloped a unique, on-demand content delivery sys-tem built around Macromedia Breeze and Flash tech-nologies. The system lets students hear the professor’svoice as it walks them through interactive slides, as ifthey were sitting in the same classroom. It also letsstudents control their own pace of learning with a full

set of controls to pause, rewind, repeat, skip andsearch through their lectures.

Knowledge Master’s curriculum features 26 coursestotaling more than 25,000 animated slides in Englishwith 350+ hours of voice-over narration in MandarinChinese. The courses are developed by Dr. Wen-Ching Chang, an internationally-renowned professorof microelectronics, specializing in RFIC, CMOS, ana-log IC, optoelectronics and wireless communications.Dr. Chang has taught more than 30,000 college stu-dents and working professionals over the past 20years in Taiwan.

“I am highly honored to be affiliated with IEEE, andam excited about the opportunity to offer our full libraryof online courses to Chinese-speaking IEEE members toassist them in their professional career development,”stated Dr. Wen-Ching Chang, CEO. “We hope our richcontent, combined with our easy to use interface willgive IEEE members the freedom and power to learn attheir own pace, on their own schedule.”

“As a working professional in the IC design indus-try for 15 years and then having learned with Dr.Chang for six months, I started to realize what thecore concepts and analysis skills of microelectronicswere all about,” said Mr. Hong-Yuan Yang, a senior

SSCS NEWS



analog IC design engineer from Holtek Corporation inTaiwan, who gave this testimony to the public duringthe 2006 Taiwan Microelectronics Conference.

The IEEE’s Educational Partner Program, exclusive-ly for IEEE members, offers on-line degree programs,certifications and courses at up to a 10 percent dis-count. The partners are a carefully selected numberof universities and corporations reviewed andapproved by highly qualified IEEE volunteers toensure members receive the most effective learning

resources. The goal of the IEEE education program isto ensure the growth of skill and knowledge amongthe technical profession and to foster individual com-mitment to continuing education among the engi-neering and scientific community, the general public,and the more than 365,000 IEEE members in approx-imately 150 countries.

To access courses, have free preview offered byKnowledge Master Microelectronics Institute, or toreview other partners, visit www.ieee.org/partners.

Call for Nominations: SSCS Predoctoral Fellowships2007 – 2008Due Date is 1 May, 2007

Nominations for the Society’sPredoctoral Fellowships insolid-state circuits are due on

1 May, 2007 for the academic year2007-2008. The one-year awards willprovide $15,000 for tuition, up to$8000 in addition for fees, and a grantof $2,000 to the department in whichthe recipient is registered. A maxi-mum of two awards will be made.

Last year’s predoctoral fellowswere Chinmaya Mishra of TexasA&M University and Peter H. R.Popplewell of Carleton University,Ottawa Canada.

Fellowship awards are availableworld-wide. Applicants must havecompleted at least one year of graduate study, be in aPh.D. program in the area of solid-state circuits, andbe a member of IEEE. The award will be made on thebasis of academic record and promise, dissertationresearch program, and need.

Applications should be in electronic format andmust include the following items:

A Short (one-page) Biography - including IEEEmembership number.

Academic Records - including a copy of all rele-vant undergraduate and graduate transcripts.

Graduate Study Plans - including a summary ofwhat has been completed and what is planned (about

2 pages is appropriate), plus a listof any publications authored orco-authored. A copy of each pub-lication is desirable. Work thatmust be done to complete thegraduate program of study shouldbe explained -- why it is impor-tant, and what is novel about itsapproach -- as well as the impor-tance of SSCS predoctoral fellow-ship support toward completionof the doctoral degree.

Letters of Recommendation -At least two letters of recommen-dation are required; one should befrom the principal advisor. Theseletters should address academic

record, accomplishments and promise, graduate studyresearch program, and need.

Deadline: 1 May 2007Please email your application materials to: [email protected]. Electronic file submission is preferred, but if paper

files are all you can provide, either fax them to +1732-981-3401 or mail to:

IEEE-SSCS Executive OfficePredoctoral Fellowship445 Hoes LanePiscataway, NJ 08854

President Richard C. Jaeger presentedSSCS Predoctoral Fellowship certificatesto Mr. Popplewell (left) and Mr. Mishraduring the plenary session Awards Pro-gram at ISSCC 2007 in San Francisco.

SSCS NEWS



Presubmission Professional Editing Services for IEEEAuthorsDawn Melley, Director, Editorial Services, IEEE Periodicals

In conjunction with a TAB Periodicals subcommittee,chaired by Jacek Zurada, and in response to the inter-est you expressed at the April 2006 Panel of Editors

meeting in Montreal, IEEE Publishing Operations has part-nered with one of our established vendors, SPi PublisherServices, to offer presubmission professional editing serv-ices to IEEE authors, beginning immediately.

SPi provides scientific, technical and medical pub-lishers with a high quality, end-to-end outsourcing solu-tion. Their multi-country delivery platform harnessesthe talent of more than 3,500 content and BPO special-ists. Located in the US, Europe and the Philippines,these specialists copyedit and typeset more than 1 mil-lion pages per year for over 600 journals. SPi has pro-vided content tagging and editing services to IEEE Pub-lishing Operations since 2002.

An author who would like assistance with Englishgrammar and usage prior to submitting their manuscriptto an IEEE publication for review or during the reviewprocess can now go directly to www.prof-

editing.com/ieee/ to submit a manuscript for copy edit-ing. The SPi copy editors will edit for grammar, usage,organization, and clarity, querying potentially substan-tive revisions as necessary. An author can use the serv-ice, at their own expense, as often as desired. Cost esti-mates are available immediately on line. Edited manu-scripts will generally be returned to the author withintwo weeks of submission.

Please help us to publicize this service by adding theabove information to your Information for Authors doc-ument as well as to your manuscript submission site, ifapplicable. We will publish the information in the Toolsfor Authors section of the IEEE website.

If you would like additional information about thisnew service, please feel free to contact me directly.

Dawn MelleyDirector, Editorial Services, IEEE Periodicals445 Hoes Lane, Piscataway, NJ 08855+1 732 562 [email protected]


ProvenPOWERFUL

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445 Hoes Lane Piscataway, NJ 08854

SSCS SPONSORED MEETINGS2007 Symposium on VLSI Circuitswww.vlsisymposium.org14–16 June 2007Kyoto, JapanContact: Phyllis Mahoney, [email protected] Business Center for Academic Societies,Japan,[email protected]

2007 Custom Integrated Circuits Conferencehttp://www.ieee-cicc.org/16–19 September 2007San Jose, CA, USAPaper deadline: 9 April 2007Contact: Ms. Melissa [email protected]

2007 A-SSCC Asia Solid-State Circuits Conferencewww.a-sscc.org/12–14 November 2007Jeju Island, KoreaPaper deadline: 11 June 2007Contact: : [email protected]

2007 ISSCC International Solid-State Circuits Conferencewww.isscc.org3– 7 February 2008 San Francisco, CA, USAPaper deadline: 17 September 2007Contact: Courtesy Associates, [email protected]

SSCS PROVIDES TECHNICAL CO-SPONSORSHIP 2007 Design, Automation and Test inEuropewww.date-conference.com/conference/next.htm16–20 April, 2007Acropolis, Nice, FranceContact: [email protected]

2007 International Symposium on VLSITechnology, Systems and Applications(VLSI-TSA) vlsidat.itri.org.tw25 Apr - 27 Apr 2007 Hsinchu, Taiwan Contact: Ms. Stacey C.P. [email protected]

2007 International Symposium on VLSIDesign, Automation and Test (VLSI-DAT) vlsidat.itri.org.tw25 Apr - 27 Apr 2007 Hsinchu, Taiwan Contact: Elodie J.F. [email protected]

2007 Radio Frequency Integrated Circuits Symposium www.rfic2007.org3–8 June 2007Honolulu, HawaiiContact: Dr. Luciano [email protected]

2007 Design Automation Conferencewww.dac.com4–8 June 2007San Diego, CA, USAContact: Kevin Lepine, Conference [email protected]

Hot Chipswww.hotchips.org11 Sep - 13 Sep 2007 Palo Alto, CA, USAPaper Deadline: 25 March 2007Contact: John Sell, [email protected]

ESSCIRC/ESSDERC 2007 - 37th European SolidState Circuits/Device Research Conferenceswww.essscirc.org11 Sep - 13 Sep 2007 Munich, GermanyContact: Mr. Philip [email protected]

2007 IEEE Integrated Circuit Ultra-WideBandICUWB www.icuwb2007.org30 Sep - 02 Oct 2007 Singapore Paper Deadline: 18 March 2007Contact: Michael Y.W. Chia, [email protected]

2007 IEEE Bipolar/BiCMOS Circuits andTechnology Meeting - BCTM www.ieee-bctm.org30 Sep - 02 Oct 2007 Boston Marriott Long Wharf, Boston, MA Contact: Ms. Janice [email protected]

2007 IEEE Compound SemiconductorIntegrated Circuit Symposium (CSICS)(Formerly GaAs IC Symposium)www.csics.org14 Oct – 17 Oct 2007Portland, ORPaper Deadline: 7 May 2007Contact: William Peatman [email protected]

2007 IEEE/ACM International Conferenceon Computer-Aided Design (ICCAD) www.iccad.com/future.html04 Nov - 08 Nov 2007 DoubleTree Hotel, San Jose, CA Paper Deadline: 11 April 2007Contact: Ms. Kathy [email protected]

SSCS EVENTS CALENDARAlso posted on www.sscs.org/meetings

SSCS IEEE SOLID-STATE CIRCUITS SOCIETY NEWS is published quarterly by the Solid-State CircuitsSociety of The Institute of Electrical and Electronics Engineers, Inc. Headquarters: 3 Park Avenue, 17thFloor, New York, NY 10016-5997. $1 per member per year (included in society fee) for each member ofthe Solid-State Circuits Society. This newsletter is printed in the U.S.A. Application to mail Periodicalspostage rates is pending at New York, NY and at additional mailing offices.Postmaster: Send address changes to SSCS IEEE Solid-State Circuits Society News, IEEE, 445 Hoes Lane,Piscataway, NJ 08854. ©2007 IEEE. Permission to copy without fee all or part of any material without acopyright notice is granted provided that the copies are not made or distributed for direct commercialadvantage and the title of publication and its date appear on each copy. To copy material with a copy-right notice requires specific permission. Please direct all inquiries or requests to IEEE Copyrights Man-ager, IEEE Service Center, 445 Hoes Lane, Piscataway, NJ 08854. Tel: +1 732 562 3966.

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[email protected] make sure you receive an email alert, keepyour email address current at sscs.org/e-news

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