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Marvell. Moving Forward Faster

Doc. No. MV-S108780-U0 Rev. B

July 2013

Document Classification: Proprietary Information

Marvell 88MC200 Microcontroller

Datasheet

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For more information, visit our website at: www.marvell.comDisclaimerNo part of this document may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopying and recording, for any purpose, without the express written permission of Marvell. Marvell retains the right to make changes to this document at any time, without notice. Marvell makes no warranty of any kind, expressed or implied, with regard to any information contained in this document, including, but not limited to, the implied warranties of merchantability or fitness for any particular purpose. Further, Marvell does not warrant the accuracy or completeness of the information, text, graphics, or other items contained within this document. Marvell products are not designed for use in life-support equipment or applications that would cause a life-threatening situation if any such products failed. Do not use Marvell products in these types of equipment or applications. With respect to the products described herein, the user or recipient, in the absence of appropriate U.S. government authorization, agrees: 1) Not to re-export or release any such information consisting of technology, software or source code controlled for national security reasons by the U.S. Export Control Regulations ("EAR"), to a national of EAR Country Groups D:1 or E:2; 2) Not to export the direct product of such technology or such software, to EAR Country Groups D:1 or E:2, if such technology or software and direct products thereof are controlled for national security reasons by the EAR; and, 3) In the case of technology controlled for national security reasons under the EAR where the direct product of the technology is a complete plant or component of a plant, not to export to EAR Country Groups D:1 or E:2 the direct product of the plant or major component thereof, if such direct product is controlled for national security reasons by the EAR, or is subject to controls under the U.S. Munitions List ("USML"). At all times hereunder, the recipient of any such information agrees that they shall be deemed to have manually signed this document in connection with their receipt of any such information. Copyright 2013. Marvell International Ltd. All rights reserved. Marvell, the Marvell logo, Moving Forward Faster, Alaska, Fastwriter, Datacom Systems on Silicon, Libertas, Link Street, NetGX, PHYAdvantage, Prestera, Raising The Technology Bar, The Technology Within, Virtual Cable Tester, and Yukon are registered trademarks of Marvell. Ants, AnyVoltage, Discovery, DSP Switcher, Feroceon, GalNet, GalTis, Horizon, Marvell Makes It All Possible, RADLAN, UniMAC, and VCT are trademarks of Marvell. All other trademarks are the property of their respective owners.

88MC200 Microcontroller Datasheet

Doc. No. MV-S108780-U0 Rev. B Copyright 2013 MarvellPage 2 Document Classification: Proprietary Information July 2013

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Table of Contents

Copyright 2013 Marvell Doc. No. MV-S108780-U0 Rev. BJuly 2013 Document Classification: Proprietary Information Page 3

Table of Contents

1 Product Overview ........................................................................................................................231.1 Introduction .....................................................................................................................................................23

1.2 Features ..........................................................................................................................................................24

1.3 Pin Descriptions ..............................................................................................................................................261.3.1 Pinout................................................................................................................................................26

1.4 Feature Descriptions .......................................................................................................................................391.4.1 ARM Cortex-M3 CPU Core ..............................................................................................................391.4.2 Embedded SRAM .............................................................................................................................391.4.3 In-Package Flash..............................................................................................................................391.4.4 Boot ROM .........................................................................................................................................391.4.5 AHB Bus Matrix ................................................................................................................................391.4.6 Power, Reset and Clock Control.......................................................................................................391.4.7 Direct Memory Access (DMA)...........................................................................................................391.4.8 General Purpose IO (GPIO) .............................................................................................................401.4.9 Watchdog Timer (WDT)....................................................................................................................401.4.10 Real Time Clock (RTC).....................................................................................................................411.4.11 General Purpose Timers...................................................................................................................411.4.12 Advanced Encryption Standard (AES) Engine .................................................................................411.4.13 Cyclic Redundancy Check (CRC).....................................................................................................421.4.14 General Purpose ADC ......................................................................................................................421.4.15 Analog Comparators.........................................................................................................................421.4.16 DAC ..................................................................................................................................................431.4.17 UART ................................................................................................................................................431.4.18 I2C ....................................................................................................................................................431.4.19 QSPI Interface .................................................................................................................................441.4.20 SSP...................................................................................................................................................441.4.21 SDIO .................................................................................................................................................451.4.22 USB ..................................................................................................................................................45

1.5 Part Ordering...................................................................................................................................................45

2 Processor Overview ....................................................................................................................492.1 Overview .........................................................................................................................................................49

2.1.1 Cortex M3 Features ..........................................................................................................................492.1.2 Memory Protection Unit (MPU).........................................................................................................492.1.3 Nested Vectored Interrupt Controller (NVIC) ....................................................................................492.1.4 SysTick Timer ...................................................................................................................................50

88MC200 MicrocontrollerDatasheet


3 I/O Configuration ........................................................................................................................513.1 Pinmux Alternate Functions ............................................................................................................................51

3.1.1 GPIO_0 (Offset=0x0) ......................................................................................................................523.1.2 GPIO_1 (Offset=0x4) ......................................................................................................................523.1.3 GPIO_2 (Offset=0x8) ......................................................................................................................533.1.4 GPIO_3 (Offset=0xC) .....................................................................................................................533.1.5 GPIO_4 (Offset=0x10) ....................................................................................................................543.1.6 GPIO_5 (Offset=0x14) ....................................................................................................................543.1.7 GPIO_6 (Offset=0x18) ....................................................................................................................553.1.8 GPIO_7 (Offset=0x1C) ...................................................................................................................553.1.9 GPIO_8 (Offset=0x20) ....................................................................................................................563.1.10 GPIO_9 (Offset=0x24) ...................................................................................................................563.1.11 GPIO_10 (Offset=0x28) ..................................................................................................................573.1.12 GPIO_11 (Offset=0x2C) .................................................................................................................573.1.13 GPIO_16 (Offset=0x40) ..................................................................................................................583.1.14 GPIO_17 (Offset=0x44) ..................................................................................................................583.1.15 GPIO_18 (Offset=0x48) ..................................................................................................................593.1.16 GPIO_19 (Offset=0x4C) .................................................................................................................593.1.17 GPIO_20 (Offset=0x50) ..................................................................................................................603.1.18 GPIO_21 (Offset=0x54) ..................................................................................................................603.1.19 GPIO_22 (Offset=0x58) ..................................................................................................................603.1.20 GPIO_23 (Offset=0x5C) .................................................................................................................613.1.21 GPIO_24 (Offset=0x60) ..................................................................................................................613.1.22 GPIO_25 (Offset=0x64) ..................................................................................................................623.1.23 GPIO_26 (Offset=0x68) ..................................................................................................................633.1.24 GPIO_27 (Offset=0x6C) .................................................................................................................633.1.25 GPIO_28 (Offset=0x70) ..................................................................................................................643.1.26 GPIO_29 (Offset=0x74) ..................................................................................................................643.1.27 GPIO_30 (Offset=0x78) ..................................................................................................................653.1.28 GPIO_32 (Offset=0x80) ..................................................................................................................653.1.29 GPIO_33 (Offset=0x84) ..................................................................................................................663.1.30 GPIO_34(Offset=0x88) ..................................................................................................................663.1.31 GPIO_35(Offset=0x8C) ..................................................................................................................673.1.32 GPIO_40(Offset=0xA0) ...................................................................................................................673.1.33 GPIO_41(Offset=0xA4) ...................................................................................................................683.1.34 GPIO_42(Offset=0xA8) ...................................................................................................................693.1.35 GPIO_43 (Offset=0xAC) .................................................................................................................693.1.36 GPIO_44 (Offset=0xB0) ..................................................................................................................703.1.37 GPIO_45 (Offset=0xB4) ..................................................................................................................703.1.38 GPIO_50 (Offset=0xC8) .................................................................................................................713.1.39 GPIO_51 (Offset=0xCC) .................................................................................................................713.1.40 GPIO_52 (Offset=0xD0) .................................................................................................................723.1.41 GPIO_53 (Offset=0xD4) .................................................................................................................723.1.42 GPIO_54 (Offset=0xD8) .................................................................................................................733.1.43 GPIO_55 (Offset=0xDC) .................................................................................................................733.1.44 GPIO_56 (Offset=0xE0) ..................................................................................................................743.1.45 GPIO_57(Offset=0xE4) ...................................................................................................................743.1.46 GPIO_58 (Offset=0xE8) ..................................................................................................................753.1.47 GPIO_59 (Offset=0xEC) .................................................................................................................753.1.48 GPIO_60 (Offset=0xF0) ..................................................................................................................763.1.49 GPIO_61 (Offset=0xF4) ..................................................................................................................763.1.50 GPIO_62 (Offset=0xF8) ..................................................................................................................773.1.51 GPIO_63 (Offset=0xFC) .................................................................................................................773.1.52 GPIO_64 (Offset=0x100) ................................................................................................................783.1.53 GPIO_65 (Offset=0x104) ................................................................................................................78

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3.1.54 GPIO_66 (Offset=0x108) ................................................................................................................793.1.55 GPIO_68 (Offset=0x110) ...............................................................................................................793.1.56 GPIO_72 (Offset=0x120) ................................................................................................................803.1.57 GPIO_73 (Offset=0x124) .................................................................................................................803.1.58 GPIO_74 (Offset=0x128) ................................................................................................................813.1.59 GPIO_75 (Offset=0x12C) ...............................................................................................................813.1.60 GPIO_76 (Offset=0x130) ................................................................................................................823.1.61 GPIO_77 (Offset=0x134) ................................................................................................................823.1.62 GPIO_78 (Offset=0x138) ................................................................................................................833.1.63 GPIO_79 (Offset=0x13C) ...............................................................................................................833.1.64 I/O Padding .....................................................................................................................................84

4 System Control ............................................................................................................................874.1 Overview .........................................................................................................................................................87

4.2 Features ..........................................................................................................................................................87

4.3 Register Description........................................................................................................................................87

5 Power, Reset, and Clock Control ...............................................................................................895.1 Overview .........................................................................................................................................................89

5.2 Power Supply ..................................................................................................................................................895.2.1 Power Pins........................................................................................................................................905.2.2 I/O Power Configuration ...................................................................................................................915.2.3 AON Domain.....................................................................................................................................92

5.2.3.1 Ultra Low-Power Comparator .............................................................................................925.2.3.2 Brownout Detection ............................................................................................................93

5.3 Power Modes ..................................................................................................................................................93

5.4 Power Mode Transitions .................................................................................................................................96

5.5 Wake-up Sources............................................................................................................................................975.5.1 Wake-up from PM1 Mode.................................................................................................................975.5.2 Wake-up from PM2/3/4 Modes .........................................................................................................975.5.3 Reset Controller ................................................................................................................................98

5.6 Clock Controller...............................................................................................................................................985.6.1 Overview ..........................................................................................................................................985.6.2 Clock Sources...................................................................................................................................995.6.3 SFLL ...............................................................................................................................................1015.6.4 Cortex-M3 Core Clock and Bus Clock ............................................................................................1015.6.5 UART Clocks ..................................................................................................................................1025.6.6 AUPLL for Audio Clock and USB Clock..........................................................................................1025.6.7 CAU Clock ......................................................................................................................................1035.6.8 GPT Clock ......................................................................................................................................104

5.6.8.1 GPT Sampling Clock ........................................................................................................1045.6.9 Clock Output ...................................................................................................................................104

5.7 Register Description......................................................................................................................................105

6 Memory Map, Interrupts and AHB Bus Fabric ........................................................................1076.1 Overview .......................................................................................................................................................107

6.2 Memory Map .................................................................................................................................................107

6.3 Interrupts .......................................................................................................................................................110

6.4 AHB Bus Fabric.............................................................................................................................................113



7 Direct Memory Access Controller (DMA) ................................................................................1177.1 Overview .......................................................................................................................................................117

7.2 Features ........................................................................................................................................................1177.2.1 DMA Operation ..............................................................................................................................1177.2.2 DMA Block Diagram .......................................................................................................................1177.2.3 Basic Definitions .............................................................................................................................1187.2.4 Peripheral Burst Transaction Requests ..........................................................................................119

7.2.4.1 Watermark Level and Transmit FIFO Underflow..............................................................1217.2.4.2 Choosing the Transmit Watermark Level .........................................................................1217.2.4.3 Selecting DEST_MSIZE and Transmit FIFO Overflow.....................................................1237.2.4.4 Receive Watermark Level and Receive FIFO Overflow...................................................1237.2.4.5 Choosing the Receive Watermark Level ..........................................................................1237.2.4.6 Selecting SRC_MSIZE and Receive FIFO Underflow......................................................124

7.2.5 Interrupt ..........................................................................................................................................1247.2.6 DMA Channel Mapping...................................................................................................................1257.2.7 Operation Mode ..............................................................................................................................125

7.3 Register Descriptions ....................................................................................................................................126

8 Real Time Clock (RTC) ..............................................................................................................1278.1 Overview .......................................................................................................................................................127

8.2 Functional Description...................................................................................................................................1278.2.1 Counter Clock .................................................................................................................................1278.2.2 Counting Mode ...............................................................................................................................1288.2.3 Counter Update Mode ....................................................................................................................1288.2.4 Interrupt ..........................................................................................................................................128

8.3 Programming Notes ......................................................................................................................................1288.3.1 Initialization .....................................................................................................................................1288.3.2 UPP_VAL........................................................................................................................................129


9 General Purpose Timers (GPT) ................................................................................................1319.1 Overview .......................................................................................................................................................131

9.2 Functional Description...................................................................................................................................1319.2.1 Counter ..........................................................................................................................................133

9.2.1.1 Counter Clock...................................................................................................................1339.2.1.2 Counting Mode .................................................................................................................1339.2.1.3 Counter Update Mode ......................................................................................................134

9.2.2 Interrupt ..........................................................................................................................................1349.2.3 Channel Operation Modes..............................................................................................................135

9.2.3.1 Counter Match Register 0 and 1 (CMR0 and CMR1).......................................................1359.2.3.2 No Function Mode ............................................................................................................1359.2.3.3 Input Capture Mode..........................................................................................................1359.2.3.4 One-Shot Pulse Mode ......................................................................................................1369.2.3.5 One-Shot Edge Mode.......................................................................................................1379.2.3.6 Pulse-Width Modulation (PWM) Edge-Aligned Mode.......................................................1389.2.3.7 Pulse-Width Modulation (PWM) Center-Aligned Mode ....................................................139

9.2.4 ADC Trigger ...................................................................................................................................1419.2.5 DAC Trigger ....................................................................................................................................142

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9.3 Programming Notes ......................................................................................................................................1439.3.1 Initialization .....................................................................................................................................1439.3.2 UPP_VAL........................................................................................................................................1449.3.3 User Request Register ...................................................................................................................144


10 Secure Digital Input/Output (SDIO Controller)........................................................................14510.1 Overview .......................................................................................................................................................145

10.2 Signal Descriptions .......................................................................................................................................145

10.3 Controller Operation......................................................................................................................................14610.3.1 Operation ........................................................................................................................................148

10.3.1.1 Data Transfers..................................................................................................................148

10.4 Commands and Operations ..........................................................................................................................14910.4.1 Overview.........................................................................................................................................149

10.4.1.1 Read/Write Commands ....................................................................................................14910.4.2 Controller Functional Description....................................................................................................150

10.5 Interrupts .......................................................................................................................................................152

10.6 Clock Control.................................................................................................................................................153

10.7 Data FIFOs....................................................................................................................................................15310.7.1 Command Response Register........................................................................................................15310.7.2 Receive Data FIFO Configuration...................................................................................................15410.7.3 Transmit Data FIFO Configuration..................................................................................................15410.7.4 DMA and Programmed I/O .............................................................................................................154

10.8 Low-Power Mode Operation .........................................................................................................................155

10.9 Card Communication Protocol ......................................................................................................................15510.9.1 PIO Operation.................................................................................................................................15510.9.2 DMA Operation ...............................................................................................................................15610.9.3 Abort Transaction ...........................................................................................................................157

10.9.3.1 Synchronous Abort ...........................................................................................................157


11 USB OTG Interface Controller ..................................................................................................15911.1 Features ........................................................................................................................................................159

11.2 Internal Bus Interface ....................................................................................................................................16011.2.1 DMA Engine....................................................................................................................................16011.2.2 Dual Port RAM Controller ...............................................................................................................16111.2.3 Protocol Engine ..............................................................................................................................16111.2.4 Port Controller.................................................................................................................................161


11.4 Functional Description...................................................................................................................................16211.4.1 Host Data Structure ........................................................................................................................162

11.5 USB Controller Operation .............................................................................................................................16311.5.1 FIFO Operation in Device Mode .....................................................................................................163

11.5.1.1 Streaming Mode ...............................................................................................................16311.5.1.2 Additional Notes on TX FIFO Buffering IN Endpoints ...................................................16411.5.1.3 Non-Streaming Mode .......................................................................................................16511.5.1.4 FIFO Operation in Host Mode ..........................................................................................165

11.5.2 Clock Control and Enables .............................................................................................................16811.5.3 Programming Guidelines ................................................................................................................168




12 WatchDog Timer (WDT) ............................................................................................................16912.1 Functional Description...................................................................................................................................169

12.1.1 Counter Operation ..........................................................................................................................16912.1.2 Interrupt ..........................................................................................................................................16912.1.3 System Reset .................................................................................................................................17012.1.4 Reset Pulse Length ........................................................................................................................170

12.2 Initialization Sequence ..................................................................................................................................170


13 Quad Serial Peripheral Interface (QSPI) Controller ................................................................17313.1 Overview .......................................................................................................................................................173

13.2 Features List .................................................................................................................................................173

13.3 Block Diagram...............................................................................................................................................173

13.4 IO Description ...............................................................................................................................................174

13.5 Functional Description...................................................................................................................................17413.5.1 Basic Operation ..............................................................................................................................17413.5.2 Serial Flash Data Format ................................................................................................................175

13.6 Usage Models and Programming Notes ......................................................................................................182

13.7 QSPI0 Interface to In-package Serial Flash..................................................................................................18213.7.1 Basic Read to Serial Flash Without DMA and Using Polling ..........................................................182

13.7.1.1 Page Program to Serial Flash Without DMA and Using Polling .......................................182


14 In-Package Flash .......................................................................................................................18514.1 Overview .......................................................................................................................................................185

14.2 Features ........................................................................................................................................................185

14.3 Block Diagram..............................................................................................................................................186

14.4 Functional Description...................................................................................................................................18714.4.1 QSPI0 Interface ..............................................................................................................................187

14.4.1.1 Standard SPI Operation ...................................................................................................18714.4.1.2 Dual SPI Operation ..........................................................................................................18714.4.1.3 Quad SPI Operation .........................................................................................................187

14.4.2 Write Protection ..............................................................................................................................18714.4.2.1 Write Protect Features .....................................................................................................187

Table of Contents


14.5 Control and Status Registers ........................................................................................................................18814.5.1 Status Register ...............................................................................................................................188

14.5.1.1 BUSY................................................................................................................................18814.5.1.2 Write Enable Latch (WEL)................................................................................................18814.5.1.3 Block Protect Bits (BP2, BP1, BP0) .................................................................................18814.5.1.4 Top/Bottom Block Protect (TB).........................................................................................18814.5.1.5 Sector/Block Protect (SEC) ..............................................................................................18814.5.1.6 Complement Protect (CMP) .............................................................................................18814.5.1.7 Status Register Protect (SRP1, SRP0) ............................................................................18914.5.1.8 Erase/Program Suspend Status (SUS) ............................................................................18914.5.1.9 Security Register Lock Bits (LB3, LB2, LB1)....................................................................18914.5.1.10Quad Enable (QE) ...........................................................................................................189

14.5.2 Instructions .....................................................................................................................................19214.5.2.1 Instruction Set Table 1 (Erase, Program Instructions) 1 ..................................................19414.5.2.2 Instruction Set Table 2 (Read Instructions) ......................................................................19514.5.2.3 Instruction Set Table 3 (ID, Security Instructions) ............................................................196

15 General Purpose Input Output (GPIO).....................................................................................19715.1 Overview .......................................................................................................................................................197

15.2 GPIO Block Diagram.....................................................................................................................................197

15.3 GPIO Function Description ...........................................................................................................................19715.3.1 GPIO Ports ....................................................................................................................................19715.3.2 I/O Control ......................................................................................................................................19815.3.3 GPIO Interrupt ................................................................................................................................19815.3.4 External Interrupts .........................................................................................................................198

15.4 GPIO Register ...............................................................................................................................................199

16 Advanced Encryption Standard (AES) ....................................................................................20116.1 Features ........................................................................................................................................................201

16.2 Functional Description...................................................................................................................................20116.2.1 AES Operational Flow ....................................................................................................................20116.2.2 AES Configuration ..........................................................................................................................20216.2.3 Data Access Method.......................................................................................................................20316.2.4 Starting the AES Engine .................................................................................................................20316.2.5 Interrupt Request ............................................................................................................................20316.2.6 Partial Code Support ......................................................................................................................20416.2.7 Error Status Check .........................................................................................................................20416.2.8 Output Vector..................................................................................................................................20416.2.9 AES Operation Pseudo Code .........................................................................................................205

16.3 References for AES Standard.......................................................................................................................206


17 Cyclic Redundancy Check (CRC) ............................................................................................20717.1 Overview .......................................................................................................................................................207

17.2 Features ........................................................................................................................................................207

17.3 CRC Operation Flow .....................................................................................................................................207


18 Universal Asynchronous Receiver Transmitter (UART) ........................................................20918.1 Overview .......................................................................................................................................................209



18.2 Block Diagram...............................................................................................................................................209

18.3 Function Description .....................................................................................................................................21018.3.1 External Signal Descriptions ..........................................................................................................21018.3.2 Protocol...........................................................................................................................................21118.3.3 SIR Protocol....................................................................................................................................21118.3.4 FIFO Access ...................................................................................................................................21218.3.5 Calculating Baud Rates ..................................................................................................................21318.3.6 Interrupts.........................................................................................................................................21318.3.7 DMA Support .................................................................................................................................21318.3.8 Auto Flow Control ..........................................................................................................................214


19 Inter-Integrated Circuit (I2C).....................................................................................................21719.1 Overview .......................................................................................................................................................217

19.2 Features ........................................................................................................................................................217


19.4 Operation ......................................................................................................................................................21819.4.1 I2C Block Diagram..........................................................................................................................21819.4.2 I2C Bus Terminology ......................................................................................................................218

19.5 I2C Behavior .................................................................................................................................................21919.5.1 START and STOP Generation .......................................................................................................220

19.5.1.1 Combined Formats...........................................................................................................22119.5.2 I2C Protocols ..................................................................................................................................221

19.5.2.1 START and STOP Conditions..........................................................................................22119.5.2.2 Addressing Slave Protocol ...............................................................................................22119.5.2.3 Transmitting and Receiving Protocol................................................................................222

19.5.3 Multiple Master Arbitration ..............................................................................................................22419.5.4 Clock Synchronization ....................................................................................................................22419.5.5 Operation Modes ............................................................................................................................225

19.5.5.1 Slave Mode Operation......................................................................................................22519.5.5.2 Master Mode Operation....................................................................................................228

19.5.6 I2C.CLK Frequency Configuration..................................................................................................22919.5.6.1 Calculating High and Low Counts ....................................................................................229

19.5.7 DMA Controller Interface ................................................................................................................230


20 Synchronous Serial Protocol (SSP).........................................................................................23120.1 Overview .......................................................................................................................................................231

20.2 Features ........................................................................................................................................................231

20.3 External Signal Descriptions .........................................................................................................................231

Table of Contents


20.4 Operation ......................................................................................................................................................23220.4.1 FIFO Operation...............................................................................................................................232

20.4.1.1 Parallel Data Formats for FIFO Storage...........................................................................23320.4.1.2 FIFO Operation in Packed Mode......................................................................................23320.4.1.3 Trailing Bytes in RXFIFO..................................................................................................233

20.4.2 Using Programmed I/O Data Transfers ..........................................................................................23420.4.3 Using DMA Data Transfers.............................................................................................................23420.4.4 Data Formats ..................................................................................................................................234

20.4.4.1 Serial Data Formats for Transfer to/from Peripherals.......................................................23420.4.4.2 TI-SSP Format Details .....................................................................................................23520.4.4.3 Motorola SPI Format Details ............................................................................................237

20.4.5 Programmable Serial Protocol (PSP) Format .................................................................................24020.4.5.1 High Impedance on SSPx_TXD .......................................................................................244

20.4.6 Network Mode.................................................................................................................................24720.4.6.1 Network Mode Registers ..................................................................................................248

20.4.7 I2S Emulation Using SSP ...............................................................................................................249


21 Analog Digital Converter (ADC) ...............................................................................................25321.1 Overview .......................................................................................................................................................253

21.2 Features ........................................................................................................................................................253

21.3 External Signal Description ...........................................................................................................................253

21.4 ADC Functional Description ..........................................................................................................................25421.4.1 ADC Block Diagram........................................................................................................................25421.4.2 ADC On-Off Control and Conversion Trigger .................................................................................25521.4.3 ADC Input .......................................................................................................................................25521.4.4 Input Range ....................................................................................................................................25721.4.5 Temperature Measurement ............................................................................................................25721.4.6 ADC Reference Voltage .................................................................................................................25821.4.7 ADC Throughput and Resolution....................................................................................................25921.4.8 ADC Conversion Results ................................................................................................................25921.4.9 ADC Interrupts ................................................................................................................................26121.4.10 ADC Calibration ..............................................................................................................................26121.4.11 DMA Request .................................................................................................................................26221.4.12 Battery Monitor ...............................................................................................................................26221.4.13 External Trigger from GPT..............................................................................................................262


22 Digital Analog Converter (DAC) ...............................................................................................26322.1 Overview .......................................................................................................................................................263

22.2 Features ........................................................................................................................................................263




22.4 DAC Configuration ........................................................................................................................................26322.4.1 Synchronous Mode.........................................................................................................................26422.4.2 Asynchronous Mode .......................................................................................................................26522.4.3 Sinusoidal Waveform Generation ..................................................................................................26522.4.4 Triangle Waveform Generation.......................................................................................................266

22.4.4.1 Up and Down Mode..........................................................................................................26622.4.4.2 Up Mode...........................................................................................................................266

22.4.5 Noise Generation............................................................................................................................26722.4.6 DMA Request .................................................................................................................................26722.4.7 Event Trigger from GPT or GPIO ...................................................................................................267

22.5 Registers Description ....................................................................................................................................267

23 Analog Comparator (ACOMP) ..................................................................................................26923.1 Overview .......................................................................................................................................................269

23.1.1 Features..........................................................................................................................................269


23.3 Functional Description...................................................................................................................................27023.3.1 ACOMP0/1 Control Signals ............................................................................................................270

23.3.1.1 Warmup Time...................................................................................................................27023.3.1.2 Response Time ................................................................................................................27023.3.1.3 Hysteresis.........................................................................................................................270

23.3.2 Comparator Output .........................................................................................................................27123.3.2.1 Asynchronous Comparison Output at Register ................................................................27123.3.2.2 Synchronous/Asynchronous Comparison Output at GPIO ..............................................27123.3.2.3 Comparison Output Inversion...........................................................................................272

23.3.3 Comparator Output Edge Detection ...............................................................................................27223.3.4 Interrupt ..........................................................................................................................................274


24 Boot ROM ..................................................................................................................................27724.1 Overview .......................................................................................................................................................277

24.2 Boot ROM Flow Charts ................................................................................................................................27724.2.1 Loading Code Through UART ........................................................................................................28124.2.2 Loading Code Directly from Flash ..................................................................................................28124.2.3 PM3 Wakeup ..................................................................................................................................281

24.3 Flash Image Format ......................................................................................................................................28124.3.1 BootInfo/Section Header.................................................................................................................28224.3.2 Code Image ....................................................................................................................................28424.3.3 Retention Data Format ...................................................................................................................285

24.4 UART Download Protocol .............................................................................................................................285

25 Electrical, Mechanical and Thermal Specifications ...............................................................28725.1 Package Information .....................................................................................................................................287

25.2 Maximum Ratings and Operating Conditions................................................................................................29125.2.1 Absolute Maximum Ratings ............................................................................................................29125.2.2 Operating Conditions ......................................................................................................................292

Table of Contents


25.3 Electrical Characteristics...............................................................................................................................29325.3.1 DC Voltage and Current Characteristics.........................................................................................29325.3.2 I/O Port Characteristics...................................................................................................................29325.3.3 Clock Characteristics ......................................................................................................................29425.3.4 Power and Brownout Detection ......................................................................................................29525.3.5 ADC Electrical Characteristics ........................................................................................................29725.3.6 Analog Temperature Sensor Characteristics..................................................................................30025.3.7 ACOMP Electrical Characteristics ..................................................................................................30125.3.8 DAC Electrical Characteristics ........................................................................................................30225.3.9 AC Electrical Characteristics ..........................................................................................................304

25.3.9.1 SSP Timing Diagram and Specifications..........................................................................30525.3.9.2 QSPI Timing Diagram and Specifications .......................................................................30525.3.9.3 SDIO Timing Diagram and Specifications ........................................................................30625.3.9.4 RESETn Pin Specification................................................................................................307

Appendix A: 88MC200 Microcontroller Register Tables........................................................................................A-1

List of Figures


List of Figures

1 Product Overview ............................................................................................................................ 23Figure 1: 88MC200 Block Diagram..................................................................................................................24Figure 2: 88MC200 QFN88 Pinouts.................................................................................................................27Figure 3: 88MC200 QFN68 Pinout ..................................................................................................................28Figure 4: 88MC200 Microcontroller Package Markings for 88-Pin Part ...........................................................46Figure 5: Part Ordering Number ......................................................................................................................46

2 Processor Overview ........................................................................................................................ 49

3 I/O Configuration ............................................................................................................................ 51Figure 6: I/O Padding Structure .......................................................................................................................85

4 System Control ................................................................................................................................ 87

5 Power, Reset, and Clock Control ................................................................................................... 89Figure 7: 88MC200 MCU Power Supply Overview..........................................................................................89Figure 8: Power Mode Transitions ...................................................................................................................97Figure 9: High-Level Clocking Diagram .........................................................................................................100

6 Memory Map, Interrupts and AHB Bus Fabric ............................................................................ 107Figure 10: System Memory Map Diagram .......................................................................................................108Figure 11: Bus Matrix Interconnection .............................................................................................................114

7 Direct Memory Access Controller (DMA) .................................................................................... 117Figure 12: DMA Block Diagram .......................................................................................................................118Figure 13: Breakdown of DMA Transfer into Burst Transactions.....................................................................120Figure 14: Breakdown of DMA Transfer into Single and Burst Transactions...................................................121Figure 15: Case 1 Watermark Levels where IC_DMA_TDLR = 2....................................................................122Figure 16: Case 2 Watermark Levels where IC_DMA_TDLR = 6....................................................................122Figure 17: I2C Receive FIFO ...........................................................................................................................124

8 Real Time Clock (RTC) .................................................................................................................. 127Figure 18: RTC Block Diagram ........................................................................................................................127Figure 19: Count-up Mode ...............................................................................................................................128

9 General Purpose Timers (GPT) .................................................................................................... 131Figure 20: GPT Block Diagram ........................................................................................................................132Figure 21: Clock Source Selection...................................................................................................................133Figure 22: Count Up Mode...............................................................................................................................134Figure 23: Input Capture ..................................................................................................................................136Figure 24: One-Shot Pulse ..............................................................................................................................137Figure 25: One-Shot Edge ...............................................................................................................................138



Figure 26: PWM Edge-Aligned ........................................................................................................................139Figure 27: PWM Center-Aligned ......................................................................................................................141Figure 28: ADC Trigger for (a) PWM Edge-Aligned and (b) PWM Center-Aligned..........................................142Figure 29: DAC Trigger for (a) PWM Edge-Aligned and (b) PWM Center-Aligned..........................................143

10 Secure Digital Input/Output (SDIO Controller) ............................................................................ 145Figure 30: SDIO Controller Block Diagram ......................................................................................................146Figure 31: Interaction of Typical SDIO System................................................................................................147

11 USB OTG Interface Controller ...................................................................................................... 159Figure 32: USB Controller Block Diagram .......................................................................................................160Figure 33: End Point Queue Head Organization .............................................................................................162Figure 34: Periodic Schedule Organization .....................................................................................................163

12 WatchDog Timer (WDT)................................................................................................................. 169Figure 35: Interrupt Generation........................................................................................................................170Figure 36: Counter Restart and System Reset ................................................................................................170

13 Quad Serial Peripheral Interface (QSPI) Controller .................................................................... 173Figure 37: Block Diagram of the QSPI Controller ............................................................................................174Figure 38: Frame of Data Format for Serial Flash Access...............................................................................175Figure 39: Non-DMA Mode Read Flow............................................................................................................178Figure 40: Non-DMA Mode Write Flow ............................................................................................................179Figure 41: DMA Mode Write Flow....................................................................................................................180Figure 42: DMA Read Flow..............................................................................................................................181

14 In-Package Flash ........................................................................................................................... 185Figure 43: Serial Flash Memory Block Diagram...............................................................................................186Figure 44: Status Register (1)..........................................................................................................................190Figure 45: Status Register (2)..........................................................................................................................190

15 General Purpose Input Output (GPIO) ......................................................................................... 197Figure 46: General Purpose I/O Block Diagram ..............................................................................................197

16 Advanced Encryption Standard (AES) ........................................................................................ 201Figure 47: AES Operational Flow ....................................................................................................................202

17 Cyclic Redundancy Check (CRC)................................................................................................. 207

18 Universal Asynchronous Receiver Transmitter (UART) ............................................................ 209Figure 48: Block Diagram ................................................................................................................................210Figure 49: Serial Data Structure ......................................................................................................................211Figure 50: SIR Data Format.............................................................................................................................212Figure 51: Auto Flow Control Block Diagram...................................................................................................214Figure 52: Auto RTS Timing ............................................................................................................................215Figure 53: Auto CTS Timing ............................................................................................................................215

19 Inter-Integrated Circuit (I2C) ......................................................................................................... 217

List of Figures


Figure 54: I2C Block Diagram.........................................................................................................................218Figure 55: Master/Slave and Transmitter/Receiver Relationship.....................................................................219Figure 56: Data Transfer on the I2C Bus .........................................................................................................220Figure 57: START and STOP Condition ..........................................................................................................221Figure 58: 7-Bit Address Format ......................................................................................................................222Figure 59: 10-Bit Address Format....................................................................................................................222Figure 60: Master-Transmitter Protocol ...........................................................................................................223Figure 61: Master-Receive Protocol ................................................................................................................223Figure 62: Multiple Master Arbitration ..............................................................................................................224Figure 63: Multi-Master Clock Synchronization ...............................................................................................225

20 Synchronous Serial Protocol (SSP)............................................................................................. 231Figure 64: Texas Instruments Synchronous Serial Frame Protocol (Single Transfers) ...................................236Figure 65: Texas Instruments Synchronous Serial Frame Protocol (Multiple Transfers).................................237Figure 66: Motorola SPI Frame Protocol (Single Transfers) ............................................................................238Figure 67: Motorola SPI Frame Protocol (Multiple Transfers)..........................................................................239Figure 68: Motorola SPI Frame Protocols for SPO and SPH Programming (SPH Set)...................................239Figure 69: Motorola SPI Frame Protocols for SPO and SPH Programming (SPH Cleared)............................240Figure 70: Programmable Serial Protocol Format ...........................................................................................243Figure 71: Programmable Protocol Format (Consecutive Transfers) ..............................................................244Figure 72: TI SSP with SSP_SSCR1[TTE] = 1 and SSP_SSCR1[TTELP]] = 0...............................................244Figure 73: TI SSP with SSP_SSCR1[TTE] = 1 and SSP_SSCR1[TTELP] = 1................................................245Figure 74: Motorola* SPI with = 1 and = 0..............................................................................................................................245Figure 75: PSP Format with SSP_SSCR1[TTE] = 1, SSP_SSCR1[TTELP] = 0, and

SP_SSCR1[SFRMDIR] = 1.............................................................................................................246Figure 76: PSP Format with SSP_SSCR1[TTE] = 1, and either SSP_SSCR1[TTELP] = 1, or ............................

SSP_SSCR1[SFRMDIR] = 0247Figure 77: Network Mode (Example Using 4 Time Slots) ................................................................................248Figure 78: Network Mode and PSP Frame Format..........................................................................................249Figure 79: Normal I2S Format .........................................................................................................................250Figure 80: MSB-Justified I2S Format...............................................................................................................251

21 Analog Digital Converter (ADC) ................................................................................................... 253Figure 81: ADC Block Diagram........................................................................................................................255Figure 82: ADC Temperature Sensor Mode with External Diode ....................................................................258

22 Digital Analog Converter (DAC) ................................................................................................... 263Figure 83: Synchronous Mode.........................................................................................................................264Figure 84: Sinusoidal Waveform Generation ...................................................................................................265Figure 85: Full Triangle Generation Mode .......................................................................................................266Figure 86: Half Triangle Generation Mode.......................................................................................................267

23 Analog Comparator (ACOMP) ...................................................................................................... 269Figure 87: Comparator Hysteresis ...................................................................................................................271Figure 88: Comparator Output Edge Detection ..............................................................................................273



Figure 89: Interrupt ..........................................................................................................................................275

24 Boot ROM ...................................................................................................................................... 277Figure 90: Boot ROM Flow Chart 1..................................................................................................................278Figure 91: Boot ROM Flow Chart 2..................................................................................................................279Figure 92: Boot ROM Flow Chart 3..................................................................................................................280Figure 93: Flash Image Memory Mapping .......................................................................................................282

25 Electrical, Mechanical and Thermal Specifications....................................

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