88f6710, 88f6707, and 88f6w11 functional...

Marvell. Moving Forward Faster

Doc. No. MV-S107979-U0, Rev. B

May 26, 2014, Preliminary

Document Classification: Proprietary Information

88F6710/6707/6W11 Functional Specifications

88F6710, 88F6707, and 88F6W11ARMADA® 370 SoCFunctional Specifications – Unrestricted

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88F6710/6707/6W11 Functional Specifications

Doc. No. MV-S107979-U0 Rev. B Copyright © 2014 MarvellPage 2 Document Classification: Proprietary Information May 26, 2014, Preliminary

http://www.marvell.com http://www.marvell.com

Revision History

Copyright © 2014 Marvell Doc. No. MV-S107979-U0 Rev. BMay 26, 2014, Preliminary Document Classification: Proprietary Information Page 3

Revision History

Table 1: Revision History

Revision Date CommentsRev. B May 26, 2014 Unrestricted Release

Rev. A May 15, 2014 Unrestricted Release

88F6710/6707/6W11 Functional Specifications – Unrestricted


Table of ContentsRevision History ....................................................................................................................................... 3

Preface ..................................................................................................................................................... 22

1 Product Overview ...................................................................................................................... 29

2 Functional Overview ................................................................................................................. 352.1 Marvell® Core Processor .............................................................................................................................. 35

2.2 Level-2 Cache ............................................................................................................................................... 36

2.3 System Considerations ................................................................................................................................. 36

2.4 BootROM Firmware ...................................................................................................................................... 36

2.5 Coherency Fabric .......................................................................................................................................... 37

2.6 Interrupt Controller ........................................................................................................................................ 37

2.7 Timers, Counters, and Watchdog ................................................................................................................. 37

2.8 CPU Debug Capabilities ............................................................................................................................... 38

2.9 DDR3 SDRAM Controller .............................................................................................................................. 38

2.10 NAND Flash Controller (NFC) Version 1.0/2.0 .............................................................................................. 38

2.11 Device Bus Controller ................................................................................................................................... 39

2.12 Ethernet Networking Controller ..................................................................................................................... 39

2.13 PCI Express Interface ................................................................................................................................... 40

2.14 Universal Serial Bus (USB 2.0) Interface ...................................................................................................... 40

2.15 Serial-SATA (SATA) II Interface .................................................................................................................... 41

2.16 Serial Peripheral Interface (SPI) ................................................................................................................... 42

2.17 2-Channels Time-Division Multiplexing (TDM) Unit ....................................................................................... 42

2.18 Secure Digital Input/Output (SDIO) Controller .............................................................................................. 42

2.19 Audio Unit ...................................................................................................................................................... 43

2.20 Inter-Integrated Circuit Interface (I2C) ........................................................................................................... 43

2.21 UART Interface ............................................................................................................................................. 43

2.22 Real Time Clock (RTC) ................................................................................................................................. 44

2.23 General Purpose I/Os (GPIO) Ports .............................................................................................................. 44

2.24 Power Management ...................................................................................................................................... 44

2.25 High-Speed Integrated SERDES Interface ................................................................................................... 45

2.26 Cryptographic Engines and Security Accelerators (CESA) ........................................................................... 45

2.27 XOR Engines ................................................................................................................................................ 45

3 Address Map .............................................................................................................................. 463.1 Internal Address Map .................................................................................................................................... 46

3.2 Marvell® Core Processor Address Decoding ................................................................................................ 47

Table of Contents


3.3 PCI Express Address Decoding .................................................................................................................... 54

3.4 XOR DMA Address Decoding ....................................................................................................................... 57

3.5 Ethernet Networking Controllers Address Decoding ..................................................................................... 57

3.6 USB Address Decoding ................................................................................................................................ 58

3.7 SATA Address Decoding .............................................................................................................................. 58

3.8 Security Accelerator Address Decoding ........................................................................................................ 58

3.9 SDIO Address Decoding ............................................................................................................................... 58

3.10 I2C Address Decoding .................................................................................................................................. 59

3.11 Accessing the L2/SRAM from Mbus Masters ................................................................................................ 59

4 Internal Architecture ................................................................................................................. 614.1 Coherency Fabric .......................................................................................................................................... 63

4.2 DRAM Controller Interface Interconnect ....................................................................................................... 65

4.3 Mbus Interconnect ......................................................................................................................................... 65

4.4 Transaction Ordering .................................................................................................................................... 69

5 System Considerations ............................................................................................................. 725.1 Data Integrity ................................................................................................................................................. 72

5.2 Multiplexed Interfaces ................................................................................................................................... 77

5.3 PCI Express Reference Clock Output ........................................................................................................... 77

5.4 Big and Little Endian Byte Ordering .............................................................................................................. 78

6 BootROM Firmware ................................................................................................................... 816.1 Features ........................................................................................................................................................ 81

6.2 Functional Description ................................................................................................................................... 82

6.3 General Considerations ................................................................................................................................ 82

6.4 Address Decoding and Memory Management Unit (MMU) Operations ........................................................ 82

6.5 Boot Image Format ....................................................................................................................................... 83

6.6 BootROM Firmware Boot Sequence ............................................................................................................. 88

6.7 BootROM Firmware Boot Options ................................................................................................................. 96

7 Marvell® Core Processor ........................................................................................................ 101

8 Level-2 Cache .......................................................................................................................... 1028.1 Features ...................................................................................................................................................... 103

8.2 L2 Cache Requests Types .......................................................................................................................... 103

8.3 L2 Cache Functional Description ................................................................................................................ 107

8.4 Error Handling ............................................................................................................................................. 111

8.5 Events Monitor Counters ............................................................................................................................. 113

8.6 Power Management .................................................................................................................................... 114

9 Timers, Counters, and Watchdog .......................................................................................... 1159.1 Features ...................................................................................................................................................... 116



9.2 Functional Description ................................................................................................................................. 116

10 Main Processor Interrupt Controller (MPIC) ......................................................................... 11810.1 Features ...................................................................................................................................................... 119


11 CPU CoreSight™ Debug Capabilities .................................................................................... 13211.1 Functional Description ................................................................................................................................. 132

11.2 CPU Debug Capabilities ............................................................................................................................. 134

11.3 Memory Map for CoreSight Components .................................................................................................... 135

11.4 References .................................................................................................................................................. 136

12 DRAM Controller ...................................................................................................................... 13912.1 Feature List ................................................................................................................................................. 139


12.3 Transaction Data Path ................................................................................................................................ 141

12.4 Arbitration and Ordering .............................................................................................................................. 145

12.5 DRAM Timing Parameters .......................................................................................................................... 148

12.6 DRAM Burst ................................................................................................................................................ 150

12.7 DRAM Bank Interleaving ............................................................................................................................. 151

12.8 DRAM Open Pages ..................................................................................................................................... 151

12.9 DRAM Refresh ............................................................................................................................................ 152

12.10 DRAM Initialization ...................................................................................................................................... 152

12.11 DRAM Operation Mode Register ................................................................................................................. 153

12.12 Power Save Options ................................................................................................................................... 154

12.13 DRAM Topologies ....................................................................................................................................... 156

12.14 DRAM Clocking .......................................................................................................................................... 157

12.15 DRAM Address/Data Drive .......................................................................................................................... 158

12.16 DRAM Read Data Sample .......................................................................................................................... 158

12.17 On-Die Termination (ODT) .......................................................................................................................... 159

12.18 DRAM Calibration ....................................................................................................................................... 160

13 8-bit NAND Flash Interface Version 1.0 ................................................................................. 16213.1 NAND Flash Types ..................................................................................................................................... 162

13.2 Software Responsibilities ............................................................................................................................ 162

13.3 NAND Flash Interface Read Timing Parameters ........................................................................................ 163

13.4 NAND Flash Interface Write Timing Parameters ......................................................................................... 165

13.5 NAND Flash Interface Timing Parameter Limitations .................................................................................. 166

14 NAND Flash Controller (NFC) Version 2.0 ............................................................................. 16714.1 Features ...................................................................................................................................................... 167

14.2 NAND Flash Interface ................................................................................................................................. 169

14.3 NAND Flash Connectivity ............................................................................................................................ 169

Table of Contents


14.4 Operation .................................................................................................................................................... 171

14.5 Usage Models ............................................................................................................................................. 188

15 Device Bus Controller ............................................................................................................. 20115.1 Features ...................................................................................................................................................... 202


15.3 Address Multiplexing ................................................................................................................................... 205

15.4 Device Bus Timing ...................................................................................................................................... 206

15.5 Data Pack/Unpack and Burst Support ........................................................................................................ 209

15.6 READYn Support ........................................................................................................................................ 209

15.7 Additional Device Interface Signaling .......................................................................................................... 211

16 Ethernet Networking Controller ............................................................................................. 21516.1 Features ...................................................................................................................................................... 218

16.2 Networking Controller Modes Overview ...................................................................................................... 219


16.4 Queues Management .................................................................................................................................. 225

16.5 Receive Frame Processing—Hardware Parser Mode ................................................................................ 238

16.6 Marvell® Header Support ............................................................................................................................ 241

16.7 Distributed Switching Architecture (DSA) Tag Support ............................................................................... 244

16.8 Wake On LAN (WOL) Modes and Events ................................................................................................... 248

16.9 Interrupts ..................................................................................................................................................... 250

16.10 Transmit Queues Arbitration and Bandwidth Limitation .............................................................................. 251

16.11 Transmit Queues Egress Jitter Pacing (EJP) Arbitration ............................................................................ 258

16.12 Illegal Received Frames .............................................................................................................................. 261

16.13 I/O Cache Coherency .................................................................................................................................. 261

17 1G/2.5G Ethernet MAC ............................................................................................................ 26217.1 Functional Description ................................................................................................................................. 262

17.2 Retransmission (Collision) ........................................................................................................................... 263

17.3 CRC Generation .......................................................................................................................................... 263

17.4 Network Interface (10/100/1000 Mbps) ....................................................................................................... 263

17.5 Input Signal Forcing .................................................................................................................................... 266

17.6 Auto-Negotiation in Different MII/GMII/RGMII Modes ................................................................................. 266

17.7 Data Blinder ................................................................................................................................................ 266

17.8 Inter-Packet Gap ......................................................................................................................................... 267

17.9 Backpressure Mode .................................................................................................................................... 267

17.10 Flow Control ................................................................................................................................................ 267

17.11 Serial Management Interface (SMI)—Ethernet MAC .................................................................................. 269

17.12 Port MIB Counters ....................................................................................................................................... 269



18 PCI Express Interface (PCIe) 2.0 ............................................................................................ 27718.1 Features ...................................................................................................................................................... 277


18.3 Link Initialization .......................................................................................................................................... 279

18.4 Master Memory Transactions ...................................................................................................................... 280

18.5 Master I/O Transactions .............................................................................................................................. 280

18.6 Master Configuration Transactions ............................................................................................................. 280

18.7 Target Memory Transactions ...................................................................................................................... 281

18.8 Target I/O Transactions .............................................................................................................................. 281

18.9 Target Configuration Transactions .............................................................................................................. 281

18.10 Target Special Cases .................................................................................................................................. 282

18.11 Messages .................................................................................................................................................... 282

18.12 Message Signaled Interrupt (MSI) Support ................................................................................................. 284

18.13 Locked Transactions ................................................................................................................................... 284

18.14 Arbitration and Ordering .............................................................................................................................. 284

18.15 PCI Express Register Access ..................................................................................................................... 285

18.16 Hot Reset .................................................................................................................................................... 286

18.17 Error Handling ............................................................................................................................................. 286


18.19 Loopback Modes ......................................................................................................................................... 290

18.20 Peer-to-Peer Traffic ..................................................................................................................................... 292

19 Universal Serial Bus (USB 2.0) Interface ............................................................................... 29319.1 USB Controller Features ............................................................................................................................. 294

19.2 USB PHY Features ..................................................................................................................................... 294


20 Serial-ATA (SATA) II Interface ................................................................................................ 29520.1 Features ...................................................................................................................................................... 296

20.2 SATA Functional Description ...................................................................................................................... 296

20.3 EDMA Functional Description ..................................................................................................................... 297

20.4 Built-In Self Test (BIST) .............................................................................................................................. 317

20.5 Vendor Unique Frames ............................................................................................................................... 318

21 Serial Peripheral Interface (SPI) ............................................................................................. 31921.1 Features ...................................................................................................................................................... 320


21.3 SPI Modes ................................................................................................................................................... 321

21.4 Indirect Access ............................................................................................................................................ 322

21.5 Direct Mode ................................................................................................................................................. 323

Table of Contents


22 2-Channel Time Division Multiplexing (TDM2C) Unit ........................................................... 32722.1 Features ...................................................................................................................................................... 328


22.3 TDM Protocol Specification ......................................................................................................................... 330

23 Secure Digital Input/Output (SDIO) Controller ...................................................................... 34123.1 Features ...................................................................................................................................................... 342


24 Audio (I2S / S/PDIF) Interface ................................................................................................. 34824.1 Features ...................................................................................................................................................... 349

24.2 Recording Data Flow ................................................................................................................................... 351

24.3 Playback Flow ............................................................................................................................................. 355

24.4 Error Handling ............................................................................................................................................. 360

24.5 Audio Unit Memory Structure ...................................................................................................................... 361

25 Inter-Integrated Circuit Interface (I2C) ................................................................................... 36525.1 Features ...................................................................................................................................................... 366

25.2 I2C Bus Operation ....................................................................................................................................... 366

25.3 I2C Functional Description .......................................................................................................................... 367

25.4 I2C Serial ROM Initialization ........................................................................................................................ 372

26 Universal Asynchronous Receiver/Transmitter (UART) Interface ...................................... 37326.1 Features ...................................................................................................................................................... 374


26.3 Programmable Baud-Rate Generator ......................................................................................................... 376

27 General Purpose Input/Output Ports ..................................................................................... 37827.1 Features ...................................................................................................................................................... 378


27.3 GPIO Control Registers .............................................................................................................................. 378

27.4 GPIO Interrupts ........................................................................................................................................... 379

28 Power Management ................................................................................................................. 38328.1 Features ...................................................................................................................................................... 384


28.3 CPU Power Management ........................................................................................................................... 385

28.4 CPU Subsystem Power Management ......................................................................................................... 388

28.5 Waking Options ........................................................................................................................................... 388

28.6 Thermal Management ................................................................................................................................. 390

28.7 Hardware Idle Profiling ................................................................................................................................ 391

28.8 Unit Specific Power Management Options .................................................................................................. 392

28.9 Debug During Power Management (CoreSight) .......................................................................................... 392



28.10 Power Management Registers .................................................................................................................... 392

29 High-Speed Integrated SERDES Interface ............................................................................ 39329.1 Features ...................................................................................................................................................... 393

29.2 Configuring a MAC-SERDES Interface for PCIe Mode ............................................................................... 393

29.3 Assigning a SERDES Lane to the Relevant MAC ....................................................................................... 394

30 Cryptographic Engines and Security Accelerator (CESA) .................................................. 39930.1 Features ...................................................................................................................................................... 399

30.2 Theory of Operation .................................................................................................................................... 401

30.3 Functional Description—Cryptographic Engine ........................................................................................... 401

30.4 Functional Description—TDMA Engine ....................................................................................................... 417

30.5 Functional Description—Security Accelerator ............................................................................................. 421

30.6 Enhanced Flow Description ........................................................................................................................ 430

31 XOR Engine .............................................................................................................................. 43431.1 Features ...................................................................................................................................................... 434


31.3 XOR Engine Modes of Operation ................................................................................................................ 436

31.4 Descriptor Chain Format ............................................................................................................................. 438

31.5 Address Decoding ....................................................................................................................................... 442

31.6 Arbitration .................................................................................................................................................... 443

31.7 XOR Engine Programming .......................................................................................................................... 444

31.8 Burst Limit ................................................................................................................................................... 450

31.9 Errors and Interrupts ................................................................................................................................... 450

31.10 Performance Optimization ........................................................................................................................... 451

32 Real-Time Clock (RTC) ............................................................................................................ 45232.1 Features ...................................................................................................................................................... 452


A 88F6710/6707/6W11 Register Set ........................................................................................... 501A.1 Register Description......................................................................................................................................501A.2 CPU Sub-system Registers...........................................................................................................................503A.3 DRAM Controller Registers ...........................................................................................................................595A.4 NAND Flash Registers ..................................................................................................................................665A.5 Device Bus Registers....................................................................................................................................694A.6 Ethernet Controller Registers ........................................................................................................................703A.7 PCI Express 2.0 Registers ............................................................................................................................815A.8 USB 2.0 Registers.........................................................................................................................................891A.9 Serial-ATA Host Controller (SATAHC) Registers..........................................................................................899A.10 Serial Peripheral Interface (SPI) Registers ...................................................................................................964A.11 Time Division Multiplexing (TDM) Registers .................................................................................................972A.12 Secure Digital Input-Output (SDIO) Registers...............................................................................................996

Table of Contents


A.13 Audio Interface Registers............................................................................................................................1026A.14 Inter-Integrated Circuit Interface (I2C) Registers ........................................................................................1051A.15 UART Registers ..........................................................................................................................................1056A.16 GPIO Registers ...........................................................................................................................................1067A.17 MPP Registers ............................................................................................................................................1074A.18 Power Management Unit (PMU) Registers .................................................................................................1076A.19 Cryptographic Engine Registers .................................................................................................................1078A.20 XOR Engine Registers ................................................................................................................................1105A.21 Real Time Clock (RTC) Registers ...............................................................................................................1121A.22 Miscellaneous Registers .............................................................................................................................1125A.23 IP Configuration Registers ..........................................................................................................................1138A.24 Clock Complex Registers ............................................................................................................................1144



List of TablesRevision History ....................................................................................................................................... 3

Table 1: Revision History ................................................................................................................................ 3

Preface ..................................................................................................................................................... 22Table 2: Related Documents ........................................................................................................................ 22

1 Product Overview ........................................................................................................................... 29Table 3: 88F6710, 88F6707, and 88F6W11 Device Similarities and Differences ........................................ 30

2 Functional Overview ....................................................................................................................... 35

3 Address Map ................................................................................................................................... 46Table 4: Internal Address Map ...................................................................................................................... 46Table 5: CPU Interface Mbus Decoding Units IDs and Attributes ................................................................. 49Table 6: Marvell® Core Processor Default Address Map ............................................................................. 51Table 7: Units IDs and Attributes .................................................................................................................. 55

4 Internal Architecture ....................................................................................................................... 61Table 8: Primary Clock Domains .................................................................................................................. 61

5 System Considerations .................................................................................................................. 72Table 9: ECC Code Matrix ............................................................................................................................ 72

6 BootROM Firmware ........................................................................................................................ 81Table 10: MMU Virtual-to-Physical Address Translation Table ...................................................................... 83Table 11: Main Header Format ....................................................................................................................... 85Table 12: Binary (BIN) Header ....................................................................................................................... 86Table 13: Register Set (REG) Header Format ................................................................................................ 87Table 14: BootROM Error Messages .............................................................................................................. 95Table 15: Bad Block Indicators per NAND Flash Cell Type ............................................................................ 97

7 Marvell® Core Processor ............................................................................................................. 101

8 Level-2 Cache ................................................................................................................................ 102Table 16: General Memory Level-2 Cache Requests ................................................................................... 104Table 17: Core Special Maintenance Instruction L2 Requests ..................................................................... 106

9 Timers, Counters, and Watchdog ............................................................................................... 115

10 Main Processor Interrupt Controller (MPIC) ............................................................................... 118Table 18: Internal Interrupts Mapping ........................................................................................................... 128Table 19: SoC Errors Mapping ..................................................................................................................... 131

List of Tables


11 CPU CoreSight™ Debug Capabilities ......................................................................................... 132Table 20: Summary of CoreSight Memory Mapped Registers in v7 Mode ................................................... 136

12 DRAM Controller ........................................................................................................................... 139Table 21: DDR3 DRAM Addressing ............................................................................................................. 146Table 22: DDR3 Address Multiplex for 16-bit Interface, = 0 ................................................. 147Table 23: DDR3 Address Multiplex for 16-bit Interface, = 1 ................................................. 148Table 24: DRAM Timing Parameters ............................................................................................................ 149Table 25: DDR3 Address Mirroring Mapping Table ...................................................................................... 156

13 8-bit NAND Flash Interface Version 1.0 ...................................................................................... 162Table 26: NAND Flash Timing Limitations .................................................................................................... 166

14 NAND Flash Controller (NFC) Version 2.0 .................................................................................. 167Table 27: NAND Attribute Definitions ........................................................................................................... 168Table 28: Chip Select Assignment ................................................................................................................ 169Table 29: Command Format ......................................................................................................................... 172Table 30: Spare Area Used for ECC ............................................................................................................ 173Table 31: Even Data Stream ........................................................................................................................ 174Table 32: Odd Data Stream .......................................................................................................................... 174Table 33: ECC Byte Placement .................................................................................................................... 175Table 34: Small Block Page Allocation ......................................................................................................... 177Table 35: Large Block Page Allocation ......................................................................................................... 178Table 36: 4-KB Physical or Logical Page Allocation Using 2-KB Chunks ..................................................... 179Table 37: Read 2 KB MLC Page .................................................................................................................. 183Table 38: Read 4 KB MLC Page .................................................................................................................. 184Table 39: Program (Write) 2 KB MLC Page ................................................................................................. 185Table 40: Program (Write) 4 KB MLC Page ................................................................................................. 186

15 Device Bus Controller .................................................................................................................. 201

16 Ethernet Networking Controller .................................................................................................. 215Table 41: Acceleration Mode Combinations ................................................................................................. 219Table 42: Networking Controller Modes and Features ................................................................................. 219Table 43: Transmit Descriptor—Offset 0 ...................................................................................................... 228Table 44: Transmit Descriptor—Offset 4 ...................................................................................................... 230Table 45: Transmit Descriptor—Offset 8 ...................................................................................................... 230Table 46: Transmit Descriptor—Offset C ...................................................................................................... 230Table 47: Transmit Descriptor—Offset 10 .................................................................................................... 231Table 48: Transmit Descriptor—Offset 14 .................................................................................................... 231Table 49: Transmit Descriptor—Offset 18 .................................................................................................... 232Table 50: Transmit Descriptor—Offset 1C .................................................................................................... 232Table 51: Receive Descriptor—Offset 0 ....................................................................................................... 234Table 52: Receive Descriptor—Offset 4 ....................................................................................................... 236Table 53: Receive Descriptor—Offset 8 ....................................................................................................... 237Table 54: Receive Descriptor—Offset C ....................................................................................................... 237



Table 55: Receive Descriptor—Offset 10 ..................................................................................................... 237Table 56: Receive Descriptor—Offset 14 ..................................................................................................... 237Table 57: Receive Descriptor—Offset 18 ..................................................................................................... 238Table 58: Receive Descriptor—Offset 1C ..................................................................................................... 238Table 59: Marvell Header Fields ................................................................................................................... 242Table 60: DSA Tag Fields (TO_CPU Format) .............................................................................................. 245Table 61: DSA Tag Fields (FORWARD Format) .......................................................................................... 246Table 62: Token Rate Configuration Examples ............................................................................................ 255Table 63: Token Bucket Attributes ................................................................................................................ 256Table 64: Bandwidth Limitation Configuration Example for a 5-ns (200 MHz) TCLK ................................... 257

17 1G/2.5G Ethernet MAC ................................................................................................................. 262Table 65: Definitions for MAC MIB Counters ................................................................................................ 270

18 PCI Express Interface (PCIe) 2.0 ................................................................................................. 277Table 66: Supported Message Groups—Root Complex Mode .................................................................... 282Table 67: Supported Message Groups—Endpoint Mode ............................................................................. 283Table 68: Physical Layer Error List ............................................................................................................... 286Table 69: Data Link Layer Error List ............................................................................................................. 287Table 70: Transaction Layer Error List ......................................................................................................... 287

19 Universal Serial Bus (USB 2.0) Interface .................................................................................... 293

20 Serial-ATA (SATA) II Interface ..................................................................................................... 295Table 71: Disc Status LED State Settings .................................................................................................... 297Table 72: EDMA CRQB Data Structure Map ................................................................................................ 310Table 73: CRQB DW0—cPRD Descriptor Table Base Low Address ........................................................... 311Table 74: CRQB DW1—cPRD Descriptor Table Base High Address .......................................................... 311Table 75: CRQB DW2—Control Flags ......................................................................................................... 311Table 76: CRQB DW3—Data Region Byte Count ........................................................................................ 312Table 77: CRQB DW4—ATA Command ...................................................................................................... 312Table 78: CRQB DW5—ATA Command ...................................................................................................... 312Table 79: CRQB DW6—ATA Command ...................................................................................................... 313Table 80: CRQB DW7—ATA Command ...................................................................................................... 313Table 81: ePRD Table Data Structure Map .................................................................................................. 314Table 82: ePRD DWORD 0 .......................................................................................................................... 314Table 83: ePRD DWORD 1 .......................................................................................................................... 314Table 84: ePRD DWORD 2 .......................................................................................................................... 315Table 85: ePRD DWORD 3 .......................................................................................................................... 315Table 86: EDMA CRPB Data Structure Map ................................................................................................ 316Table 87: CRPB ID Register ......................................................................................................................... 316Table 88: CRPB Response Flags Register .................................................................................................. 316Table 89: CRPB Time Stamp Register ......................................................................................................... 316

List of Tables


21 Serial Peripheral Interface (SPI) .................................................................................................. 319

22 2-Channel Time Division Multiplexing (TDM2C) Unit ................................................................ 327Table 90: Time Division Multiplexing (TDM) Interface Signals ..................................................................... 329

23 Secure Digital Input/Output (SDIO) Controller ........................................................................... 341Table 91: Software Flow ............................................................................................................................... 345

24 Audio (I2S / S/PDIF) Interface ....................................................................................................... 348Table 92: Audio Unit Memory Bit Description ............................................................................................... 364

25 Inter-Integrated Circuit Interface (I2C) ........................................................................................ 365Table 93: I2C Control Register Bits ............................................................................................................... 368Table 94: I2C Status Codes .......................................................................................................................... 369

26 Universal Asynchronous Receiver/Transmitter (UART) Interface ........................................... 373Table 95: Typical Baud Rates, TCLK = 200 MHz ......................................................................................... 376Table 96: Typical Baud Rates, TCLK = 200 MHz ......................................................................................... 376

27 General Purpose Input/Output Ports .......................................................................................... 378

28 Power Management ...................................................................................................................... 383Table 97: CPU Core Power Modes .............................................................................................................. 385Table 98: CPU Core Power Management Registers Pointers ...................................................................... 392

29 High-Speed Integrated SERDES Interface .................................................................................. 393Table 99: PCIe Pipe Configurations ............................................................................................................. 394Table 100: PHY MODE and REF_FREF_SEL Setting ................................................................................... 395Table 101: SEL_BITS Setting ......................................................................................................................... 396Table 102: REFCLK_SEL Setting ................................................................................................................... 396Table 103: PIN_PHY_GEN Setting ................................................................................................................ 397Table 104: PCIe Pipe Configurations ............................................................................................................. 397Table 105: Completion Indications ................................................................................................................. 398

30 Cryptographic Engines and Security Accelerator (CESA) ....................................................... 399Table 106: DES Command Register Status Bits and Their Meaning ............................................................. 407Table 107: DES Encryption / Decryption Write Operation Result ................................................................... 408Table 108: AES128 Encryption Write Operation Result ................................................................................. 412Table 109: TDMA Descriptor Definitions ........................................................................................................ 417Table 110: Security Accelerator Data Structure DWORD 0—Configuration ................................................... 426Table 111: Security Accelerator Data Structure DWORD 1—Encryption Pointers ......................................... 427Table 112: Security Accelerator Data Structure DWORD 2— Encryption Data Length ................................. 427Table 113: Security Accelerator Data Structure DWORD 3—Encryption Keys Pointer .................................. 428Table 114: Security Accelerator Data Structure DWORD 4—Encryption Initial Values Pointer ..................... 428Table 115: Security Accelerator Data Structure DWORD 5—MAC Source Pointer ....................................... 428Table 116: Security Accelerator Data Structure DWORD 6—MAC Digest ..................................................... 429Table 117: Security Accelerator Data Structure DWORD 7—MAC Initial Values Pointers ............................ 429



31 XOR Engine ................................................................................................................................... 434Table 118: Descriptor Status Word Definition ................................................................................................. 439Table 119: Descriptor CRC-32 Result Word Definition ................................................................................... 440Table 120: Descriptor Command Word Definition .......................................................................................... 440Table 121: Descriptor Next Descriptor Address Word .................................................................................... 442Table 122: Descriptor Byte Count Word ......................................................................................................... 442Table 123: Descriptor Destination Address Word ........................................................................................... 442Table 124: Descriptor Source Address #N Words .......................................................................................... 442Table 125: EOC/EOD interpretation ............................................................................................................... 450

32 Real-Time Clock (RTC) ................................................................................................................. 452Table 126: Alarm Interrupt Valid Bit Usage .................................................................................................... 454

A 88F6710/6707/6W11 Register Set ................................................................................................ 501Table 127: Standard Register Field Type Codes ............................................................................................ 501Table 128: Summary Map Table for the CPU Sub-system Registers ............................................................. 503Table 332: Summary Map Table for the DRAM Controller Registers ............................................................. 595Table 395: Summary Map Table for the NAND Flash Registers .................................................................... 665Table 409: Summary Map Table for the Device Bus Registers ...................................................................... 694Table 420: Summary Map Table for the Ethernet Controller Registers .......................................................... 703Table 591: Summary Map Table for the PCI Express 2.0 Registers .............................................................. 815Table 700: Summary Map Table for the USB 2.0 Registers ........................................................................... 891Table 716: Summary Map Table for the Serial-ATA Host Controller (SATAHC) Registers ............................ 899Table 803: Shadow Register Block Registers Map ........................................................................................ 963Table 804: Summary Map Table for the Serial Peripheral Interface (SPI) Registers ..................................... 964Table 816: Summary Map Table for the Time Division Multiplexing (TDM) Registers ................................... 972Table 864: Summary Map Table for the Secure Digital Input-Output (SDIO) Registers ................................. 996Table 916: Summary Map Table for the Audio Interface Registers .............................................................. 1026Table 957: Summary Map Table for the Inter-Integrated Circuit Interface (I2C) Registers .......................... 1051Table 966: Summary Map Table for the UART Registers ............................................................................ 1056Table 982: Summary Map Table for the GPIO Registers ............................................................................. 1067Table 1005: Summary Map Table for the MPP Registers .............................................................................. 1074Table 1008: Summary Map Table for the Power Management Unit (PMU) Registers ................................... 1076Table 1014: Summary Map Table for the Cryptographic Engine Registers .................................................... 1078Table 1088: Summary Map Table for the XOR Engine Registers .................................................................. 1105Table 1108: Summary Map Table for the Real Time Clock (RTC) Registers ................................................. 1121Table 1115: Summary Map Table for the Miscellaneous Registers ............................................................... 1125Table 1135: Summary Map Table for the IP Configuration Registers ............................................................ 1138Table 1144: Summary Map Table for the Clock Complex Registers .............................................................. 1144

List of Figures


List of Figures1 Product Overview ........................................................................................................................... 29

Figure 1: 88F6710 Block Diagram ................................................................................................................. 32Figure 2: 88F6707 Block Diagram ................................................................................................................. 33Figure 3: 88F6W11 Block Diagram ................................................................................................................ 34

2 Functional Overview ....................................................................................................................... 35

3 Address Map ................................................................................................................................... 46

4 Internal Architecture ....................................................................................................................... 61Figure 4: 88F6710, 88F6707, and 88F6W11 Clock and Power Domains ..................................................... 62Figure 5: Coherency Fabric Interconnect to Mbus and DRAM Controller ..................................................... 64Figure 6: SDRAM Interface Arbitration .......................................................................................................... 67Figure 7: Configurable Weights Arbiter .......................................................................................................... 68

5 System Considerations .................................................................................................................. 72

6 BootROM Firmware ........................................................................................................................ 81Figure 8: BootROM Firmware Flow ............................................................................................................... 81Figure 9: Binary Image Layout in the Boot Device ......................................................................................... 84Figure 10: Initialization and Boot Method Selection Flow ................................................................................ 89Figure 11: Boot Sequence ............................................................................................................................... 94

7 Marvell® Core Processor ............................................................................................................. 101

8 Level-2 Cache ................................................................................................................................ 102Figure 12: Level-2 Cache High-Level Block Diagram .................................................................................... 102Figure 13: pLRU 8-Way Tree Example .......................................................................................................... 109Figure 14: SRAM Initialization per Way ........................................................................................................ 111

9 Timers, Counters, and Watchdog ............................................................................................... 115Figure 15: Single Processor Timers Topology ............................................................................................... 115

10 Main Processor Interrupt Controller (MPIC) ............................................................................... 118Figure 16: Main Interrupt Controller High-Level Block Diagram ..................................................................... 118Figure 17: Interrupt Sources Block Diagram .................................................................................................. 120Figure 18: Interrupt IRQ Processing Flow ...................................................................................................... 123Figure 19: MSI/MSI-X Capturing Scheme Using the Software Trigger Interrupt, Single-CPU ...................... 125

11 CPU CoreSight™ Debug Capabilities ......................................................................................... 132Figure 20: 88F6710/6707/6W11 CoreSight Configuration ............................................................................. 133Figure 21: CoreSight Subsystem v7 Mode Details ........................................................................................ 134



Figure 22: CTI / CTM Connection Details ...................................................................................................... 135

12 DRAM Controller ........................................................................................................................... 139Figure 23: DDR3 Burst Write Example (BL=8) ........................................................................................... 142Figure 24: DDR3 Burst Read Example ........................................................................................................ 142Figure 25: DRAM Controller Mbus Read Buffers—Latency Sensitive Setting ............................................... 143Figure 26: DRAM Controller Mbus Read Buffers—Latency Sensitive Setting ............................................... 144Figure 27: DRAM Controller Mbus Read Buffers—Even Bandwidth Allocation ............................................. 145Figure 28: DRAM I/O Buffer .......................................................................................................................... 159

13 8-bit NAND Flash Interface Version 1.0 ...................................................................................... 162Figure 29: 8-bit NAND Flash Read Parameters Example .............................................................................. 164Figure 30: 8-bit NAND Flash Write Parameters Example .............................................................................. 165

14 NAND Flash Controller (NFC) Version 2.0 .................................................................................. 167Figure 31: Stacked Data Flash Memory System Example Using NF_CSn[0] and NF_CSn[1] ...................... 170Figure 32: Stacked Data Flash Memory System Example Using NF_CSn[0] and NF_CSn[2] ...................... 171Figure 33: ECC Code Generation .................................................................................................................. 175Figure 34: Hamming Error Detection Process ............................................................................................... 176Figure 35: Erase Semantic Flowchart ............................................................................................................ 181Figure 36: Reset Semantic Flowchart ............................................................................................................ 182Figure 37: tWC Timing Example .................................................................................................................... 189Figure 38: tRC Timing Example Using Cnt_Del ............................................................................................. 190Figure 39: tCS Timing Example ..................................................................................................................... 191Figure 40: First Command Event Causality Diagram ..................................................................................... 193Figure 41: Reset Command Event Causality Diagram .................................................................................. 195Figure 42: Read ID Command Event Causality Diagram ............................................................................... 196Figure 43: Write Command Event Causality Diagram ................................................................................... 198

15 Device Bus Controller .................................................................................................................. 201Figure 44: Device Bus Controller Block Diagram ........................................................................................... 201Figure 45: Device Bus Connectivity for up to 256 MB Address Space .......................................................... 203Figure 46: Device Bus Connectivity for up to 256 KB Address Space ........................................................... 204Figure 47: Address Multiplexing .................................................................................................................... 205Figure 48: Read Parameters Example .......................................................................................................... 207Figure 49: Write Parameters Example ........................................................................................................... 208Figure 50: READYn Extending Acc2First Example ....................................................................................... 210Figure 51: READYn Extending Acc2Next Example ....................................................................................... 210Figure 52: READYn Extending WrLow Example ........................................................................................... 210Figure 53: BURSTn/DEV_LASTn Example ................................................................................................... 211

16 Ethernet Networking Controller .................................................................................................. 215Figure 54: Ethernet Networking Controller Block Diagram .......................................................................... 215Figure 55: Ethernet Networking Controller Transmit Packet Walkthrough .................................................... 216Figure 56: Ethernet Networking Controller Receive Packet Walkthrough ..................................................... 217

List of Figures


Figure 57: Descriptors Management by Counters Transmit Queue ............................................................... 226Figure 58: Transmit Descriptor Description ................................................................................................... 227Figure 59: Descriptors Management by Counters Receive Queue ................................................................ 232Figure 60: Receive Descriptor Description .................................................................................................... 234Figure 61: Rx Packet Marvell Header Example ............................................................................................. 241Figure 62: Tx Packet with Marvell Header Example ...................................................................................... 243Figure 63: Rx Packet with DSA Tag Example (4B tag, TO_CPU Format) ..................................................... 244Figure 64: Tx Packet with a DSA Tag Example (FROM_CPU format, use_vidx = 0) ................................... 248Figure 65: Transmit Queues Arbitration and Bandwidth Limitation ................................................................ 252Figure 66: Transmit Controller Arbitration Flow ............................................................................................. 253

17 1G/2.5G Ethernet MAC ................................................................................................................. 262Figure 67: MII Connection .............................................................................................................................. 264Figure 68: RGMII Pin Interconnection Between MAC and PHY .................................................................... 265Figure 69: Ethernet Frame Classification ....................................................................................................... 271Figure 70: Bad Frame Procedure .................................................................................................................. 272

18 PCI Express Interface (PCIe) 2.0 ................................................................................................. 277Figure 71: High-level Block Diagram ............................................................................................................. 277Figure 72: Shallow Internal Loopback ............................................................................................................ 291Figure 73: Deep Internal Loopback ................................................................................................................ 291

19 Universal Serial Bus (USB 2.0) Interface .................................................................................... 293Figure 74: USB Port Block Diagram .............................................................................................................. 293

20 Serial-ATA (SATA) II Interface ....................................