HW2• 2.3-3• 2.3-5• 2.4-4• 2.4-6• 3.1-4 (Also, use google scholar to find one or two well cited papers on symmetric

models of MOSFET, and quickly study them.)• 3.2-3• 3.3-1

• Q: Given a NMOST with VB=VS=0 and V_GS =constant >V_T+0.1V, when V_D is gradually increased from 0 to VDD >> V_GS, how does C_GD vary with V_D? How much total charge goes into or leave the gate terminal?

• Q: In a scenario similar to last question, examine how C_DB changes as V_D is varied from 0 to VDD=4phi. Let mj =mjsw = 0.5 and phi=phi_0=const. For faster operation, should you use a larger V_D or smaller V_D?

• Q: Assume level 1 model, hand sketch gm, r_ds and g_ds as V_D changes.

CMOS Device Model

• Objective– Hand calculations for analog design– Non-idealities and their effects– Efficient and accurate simulation

• CMOS transistor models– Large signal model– Small signal model– Simulation model– Noise model

Large Signal Model• Nonlinear equations for solving dc values of

device currents, given voltages• Level 1: Shichman-Hodges (VT, K', , and

NSUB)• Level 2: with second-order effects (varying

channel charge, short-channel, weak inversion, varying surface mobility, etc.)

• Level 3: Semi-empirical short-channel model• Level 4: BSIM models. Based on automatically

generated parameters from a process characterization. Good weak-strong inversion transition.

Device is symmetric. Higher voltage side is drain, lower voltage side is source.

BSIM5 and PSP models will enforce this symmetry.

Transconductance when VDS is small

Transconductance when VDS is small

Voltage controlled resistor and attenuator

Non-uniform channel potentialnon-uniform gate-substrate voltage

and non-uniform threshold voltage

( ) ( )ox GS THQ x WC v v x V

2

( );

( )( )

12( )

2

n

D ox GS TH n

D n ox GS TH DS DS

dv xi Q vel vel

dxdv x

i WC v v x Vdx

Wi C v V v v

L

Good for VDS <VGS-VTH

After that, ID become saturated.

1

on

n ox GS T

rW

C v VL

Pro: voltage control of resistivity.Con: nonlinear resistor.

MOST Regions of Operation

• Cut-off, or non-conducting: vGS <VT

– iD=0

• Conducting: vGS >=VT

– Saturation: vDS > vGS – VT

– Triode or linear or ohmic or non-saturation: vDS <= vGS – VT

2

2ox DS

D GS T DS

μC W vi ((v V )v )

L

2

2) - V(v

L

WμC i TGS

oxD

With channel length modulation

)λv() - V(vL

WμC i DSTGS

oxD 1

22

) 22(0 | |φ - | |v| |φ V V fBSfTT

L

WK

L

WμC ox '

Capacitors Of The Mosfet

CBD and CBS include both the diffusion-bulk junction capacitance as well as the side wall junction capacitance. They are highly nonlinear in bias voltages.

C4 is the capacitance between the channel and the bulk. It is highly nonlinear and depends on the operation of the device. C4 is not measurable from terminals.

oxeffeffoxDeff CLWCLLWC )()2(2

effoxDeff WCGXOCLWCC )())((31

2/)(5 effLCGBOC

Gate related capacitances

)())((

)())((

)())((2

:state offin Transistor

3

1

52

effeffDoxGD

effeffDoxGS

effoxeffeffGB

WCGDOWLCCC

WCGSOWLCCC

LCGBOCLWCCC

)())((

))((32)(

))((32)(3

2

)(2

:state saturationin Transistor

3

21

5

effeffDoxGD

effeffoxeff

effeffoxeffDoxGS

effGB

WCGDOWLCCC

WLCWCGSO

WLCWLCCCC

LCGBOCC

))((5.0)(

))((5.0))((5.0

))((5.0)(

))((5.0)(5.0

)(2

:region in triode Transistor

23

21

5

effeffoxeff

effeffoxeffDoxGD

effeffoxeff

effeffoxeffDoxGS

effGB

WLCWCGDO

WLCWLCCCC

WLCWCGSO

WLCWLCCCC

LCGBOCC

Small signal model

Typically: VDB, VSB are in such a way that there is a reversely biased pn junction.

Therefore: gbd ≈ gbs ≈ 0

pointquiescent at GS

Dm v

ig

pointquiescent at BS

Dmbsmb v

igg

pointquiescent at DS

Dds v

ig

In saturation:

But

DoxDSDoxm ILWCVILWCg /2)1(/2

SB

T

T

D

SB

Dmbs v

V

V

i

v

ig

GS

D

T

D

v

i

V

i

mSBF

mSB

Tmmbs g

Vg

v

Vgg

2/1)2(2

DDS

Dods I

V

Igg

1

2 22ox oxDm D EB do

EB

C W C WIg I V g

L V L

mmbs gg

1 1

ds Dg I

*GB effC CGBO L

*GD effC CGDO W

2( )( )

3GS ox eff effC C L W

*

*DB drain

drain

C CJ A

CJSW P

*

*SB source

source

C CJ A

CJSW P

Example spice parameter

In non-saturation region

saturationin

)()(

m

TGSox

DSTGSox

ds

g

VVL

WCVVV

L

WCg

smallry veDSox

m VL

WCg

DSox

mbs VL

WCg

High Frequency Figures of Merit T

• AC current source input to G• AC short S, D, B to gnd• Measure AC drain current output• Calculate current gain• Find frequency at which current gain = 1.

• Ignore rs and rd, Cbs, Cbd, gds, gbs, gbd all have zero voltage drop and hence zero current

• Vgs = Iin /j(Cgs+Cgb+Cgd) ≈ Iin /j(Cgs+Cgd)

• Io = − (gm − jCgd)Vgs ≈ − gm Iin /j(Cgs+Cgd)

• |Io/Iin| ≈ gm/(Cgs+Cgd)

• At T, current gain =1

• T ≈ gm/(Cgs+Cgd)≈ gm/Cgs

• or

• AC current source input to G• AC short S, B to gnd• Measure AC power into the gate• Assume complex conjugate load• Compute max power delivered by the transistor• Find maximum power gain• Find frequency at which power gain = 1.

High Frequency Figures of Merit max

BSIM models• Non-uniform charge density• Band bending due to non-uniform gate voltage• Non-uniform threshold voltage

– Non-uniform channel doping, x, y, z– Short channel effects

• Charge sharing• Drain-induced barrier lowering (DIBL)

– Narrow channel effects– Temperature dependence

• Mobility change due to temp, field (x, y)• Source, drain, gate, bulk resistances

“Short Channel” Effects

• VTH decreases for small L

– Large offset for diff pairs with small L

• Mobility reduction:– Velocity saturation

– Vertical field (small tox=6.5nm)

– Reduced gm: increases slower than root-ID

Threshold Voltage VTH

• Strong function of L– Use long channel for VTH matching

– But this increases cap and decreases speed

• Process variations– Run-to-run– How to characterize?– Slow/nominal/fast– Both worst-case & optimistic

Effect of Velocity Saturation

• Velocity ≈ mobility * field

• Field reaches maximum Emax

– (Vgs-Vt)/L reaches ESAT

• gm become saturated:– gm ≈ ½nCoxW*ESAT

• But Cgs still 2/3 WL Cox

• T ≈ gm/Cgs = ¾ nESAT /L

• No longer ~ 1/L^2

Threshold Reduction• When channel is short, effect of Vd extends to S• Cause barrier to drop, i.e. Vth to drop• Greatly affects sub-threshold current: 26 mV Vth

drop current * e• 100~200 mV Vth drop due to Vd not uncommon 100’s or 1000 times current increase

• Use lower density active near gate but higher density for contacts

Other effects• Temperature variation• Normal-Field Mobility Degradation• Substrate current

– Very nonlinear in Vd

• Drain to source leakage current at Vgs=0– Big concern for static power

• Gate leakage currents– Hot electron– Tunneling – Very nonlineary

• Transit Time Effects

Consequences for Design • SPICE (HSPICE or Spectre)

– BSIM3, BSIM4 models– Accurate but inappropriate for hand analysis– Verification (& optimization)

• Design:– Small signal parameter design space:

• gm, CL (speed, noise)

• gm/ID, ID (power, output range, speed)

• Av0= gmro (gain)

– Device geometries from SPICE (table, graph);

– may require iteration (e.g. CGS)

Sweep V1Measure vgs

Intrinsic voltage gain of MOSFET

Intrinsic voltage gain = gm/go = vds/vgs for constant Id

Intrinsic voltage gain of MOSFET

Intrinsic voltage gain = gm/go = vds/vgs for constant Id

Sweep V1Measure vgs

-+

-+

Transconductance when VDS is small

Effect of changing VDS for a large VGS

Effect of changing VDS for a given VGS

Effect of changing VDS for a given VGS

Effect of changing VDS for various VGS

VGS<=VT

Effect of changing VDS for various VGS

Effect of changing VDS for various VGS