fyse420 digital electronics lecture2 - jyväskylän...

FYSE420 DIGITAL ELECTRONICS

Lecture2Lecture2

1

DIGITAL LOGIC

CIRCUIT ANALYSIS

& DESIGNNelson, Nagle, Irvin, Carrol

ISBN 0-13-463894-8

DIGITAL DESIGN

[1]

[2] DIGITAL DESIGNMorris Mano

Fourth edition

ISBN 0-13-198924-3

Digital DesignPrinciples and Practices

Fourth edition

Wakerly John F.

ISBN 0-13-186389-4

[2]

[3]

2

The design of an asynchronous sequential circuits

Design specification

Primitive state diagram

Primitive flow table

Asynchronous Sequential Logic

Reduced flow table

Minimized number of states

Transition table

Boolean functions of all exitation variables YiOr exitation functions of unclocked FF (SR latch)

Circuit diagram

Reduced state diagram

3©Loberg

Design example3 :

SR latch (unclocked FF)

Latch has two inputs : S , R

one output : Q

Sn Rn Qn+1

0 0 Qn1 0 1

Function tableOutput state depends on previous

output



1 0 10 1 01 1 --

No state transition when input SR=00

Latch goes to the state a when SR=01

Latch goes to the state b when SR=10

SR=11 input state is forbidden

Reduced state diagram


Reduced flow table

4©Loberg

C 0 0 0 stable state C after state AD 0 0 1 stable state D after state BA 0 1 0 stable state A

0 1 1 ------1 0 0 ------

S R Q

SR

state

A

00 01 11 10

B

C

A,0

B,1

C,0

-,-

-,-

-,-

-,-

-,-

A,-

C,-

D,-

B,-


The design of an asynchronous sequential circuits Design example3 :



a

1 0 0 ------B 1 0 1 stable state B

1 1 0 ------1 1 1 ------

C

D

C,0

D,1

-,-

-,-

A,- B,-

B,-A,-

00 01 11 10state

a

b

STATE

b,-

b,1

a,0

b,- a,-

a,0

SR

STATE,Q

Reduced flow table

b

5©Loberg

State diagram

a,0 b,1SR=10

SR=01

SR=00SR=00




00 01 11 10state

a

b

STATE

b,-

b,1

a,0

b,- a,-

a,0

SR

SR=01 SR=10

Circuit has two states a and b ONE internal state variable

Secondary variable : y1

Exitation variable : Y1

The state of the output Q is state of the Y

6

STATE

©Loberg

a, 0 b, 1SR=10

SR=00SR=00

Assign binary values to the states : a=0 , b=1Q=0 on the state a

Q=1 on the state b




a, 0 b, 1SR=01

SR=01 SR=10

State diagram

00 01 11 10state

a

b

STATE

b

b

a

b a

a

SR

Flow table

7

Transition table

©Loberg

00 01 11 10y1

0

1

Y1

1

1

0

1 0

0

SR

00 01 11 10state

a

b

STATE

b

b

a

b a

a

SR



Flow table Transition table


d

d

Boolean function for the exitation variable

Undetermined state : we can use -1- during

minimization procedure.

RySY 11 +=

Y1

SR00 01 11 10y1

0

1

1

1

0

1 0

0 1

1

K-map

8©Loberg


S

Q

Design example3 :



RQ

9©Loberg




Simulation Circuit

Q

R

S

Delay for generation of reset input R


10©Loberg

Design example3 :

SR latch (unclocked FF)The design of an asynchronous sequential circuits

R

S

Set SR=10 Reset SR=01 Set SR=10


Q

R

Simulated output sequence

Forbidden input 11

See transition table : Q=1 when SR=11

11©Loberg

Circuit has two inputs x1 and x2

Circuit has one output Z

Z is -1- when x1 = x2 = -1- and x2 goes high before x1 .

x1

x2

Z

x1x2=00

x1x2=01x x =01

00/0

01/001/011/0

When Z=1 it goes to -0- only when x1 goes -0-

The design of an asynchronous sequential circuits Design example4


x1x2=11

a,0

e,0

d,1

c,1

b,0f,0

x1x2=01

x1x2=00

x1x2=01

x1x2=11

x1x2=01

x1x2=00

x1x2=10

x1x2=11

x1x2=11

x1x2=10

x1x2=10

x1x2=10 x1x2=01

x1x2=00

x1x2=10

x1x2=11

11/1

11/0

a

e

d

c

bf 00/0

01/0

11/101/0

00/0

10/1

11/1

10/1

10/0

10/0 01/0

00/0

10/0

11/0

12©Loberg

a,0 b,0 -,- e,0

a,0 b,0 c,1 -,-

-,- b,0 c,1 d,1

a

b

c

00 01 11 10x1x2

state s

11/0

a

bf

00/0

01/0

00/0

01/0

11/101/010/0 01/0

00/0

11/0



a,0 -,- c,1 d,1

a,0 -,- f,0 e,0

-,- b,0 f,0 e,0

d

e

f

S,Z


e

d

c00/0

10/1

11/1

10/1

10/0

10/0 11/1

13©Loberg

a,e,f

b,c,d

a,0 b,0 f,0

a,0 b,0 c,1

e,0

d,1

00 01 11 10x1x2

s

S,Z

x1x2

a,0 b,0 -,- e,0

a,0 b,0 c,1 -,-

-,- b,0 c,1 d,1

a,0 -,- c,1 d,1

a

b

c

d

00 01 11 10x1x2

state s



k,0 l,0 k,0

k,0 l,0 l,1

k,0

l,1

k

l

00 01 11 10x1x2

s

S,Z

Reduced flow table

a,0 -,- f,0 e,0

-,- b,0 f,0 e,0

e

f

S,Z

Two states l and k One state variable yOn state k : y = 0

On state l : y = 1


14©Loberg

k,0 l,0 k,0

k,0 l,0 l,1

k,0

l,1

k

l

00 01 11 10x1x2

s

Reduced flow table

0,0 1,0 0,0

0,0 1,0 1,1

0,0

1,1

0

1

00 01 11 10x1x2

y

Combined transition and output table


On state k : y = 0 On state l : y = 1


k,0 l,0 l,1 l,1l

S,Z

0,0 1,0 1,1 1,11

Y,Z

0 1 0

0 1 1

0

1

0

1

00 01 11 10x1x2

y

Y

Transition table

Implementation with

SR latch

Implementation without

SR latch

15©Loberg

Implementation with SR latch


S

R

Q

Q

Yx1

x2

y

fS

fR


This feedback may be not used

y

16©Loberg

Exitation table of SR-latchTransition table Exitation functions fS and fR

0 0 - 1

SR

00 01 11 10

0q



q Q S R0 0 0 X0 1 1 01 0 0 1


1 0 - 11

Q

0 1 0

0 1 1

0

1

0

1

00 01 11 10x1x2

y

Y

Transition table

00 01 11 10

0

1

y

0,X 1,0 0,X 0,X

0,1 X,0 X,0 X,0

S,R

x1x2

Map for exitation functions fS and fR

1 0 0 11 1 X 0

17

Function table of SR-latch

©Loberg

00 01 11 10

0

1

y

0,X 1,0 0,X 0,X

0,1 X,0 X,0 X,0

S,R

x1x2






X 0 X X

1 0 0 0

x1x2

00 01 11 10

0

1

y

R

K-map for input R

0 1 0 0

0 X X X

x1x2

00 01 11 10

0

1

y

S

K-map for input S

21xxS = 21xxR =

Note!

S=R=1 x1x2 is forbidden

18©Loberg

0,0 1,0 0,0

0,0 1,0 1,1

0,0

1,1

0

1

00 01 11 10x1x2

y

Y,Z

0 0 0 0

0 0 1 1

x1x2

00 01 11 10

0

1

y

Z




Combined transition and output table

Z

K-map for output Z

1yxZ =

21xxS =

21xxR =

1yxZ =

S

R

Q

Q

Zx1

x2

19©Loberg

Race Condition

Race Condition

Two or more binary state variables (yi) change value in

response to a change in an input variable (x)


[1] p. 660


00

01

11

10Depends on delays

20©Loberg

Noncritical race

Same final stable statePresent stable state

y1

y1

y2

y2

The design of an asynchronous sequential circuits Race Condition


Critical race

Different final stable state

Present stable state

y1

y1

y2

y2

Different final stable state

For proper operation critical races must be avoided

21©Loberg

Examples of noncritical race

00 11

x0 1

00

y1y2

00 11

x0 1

00

y1y2

Initial total stable state y1y2x = 000

x : 0 1



11

11

11

01

11

10

Y1Y2

01

01

11

01

11

10

Y1Y2

(00

00

00 11

01

10

01)

01

11(00

00

00 11

01

10

11

11)

Final total stable

state y1y2x = 111

Final total stable

state y1y2x = 011

Possible transitions

22

Transition table A Transition table B

©Loberg

00 11

x0 1

00

y1y2

00 11

x0 1

00

y1y2


Examples of critical race

Initial total stable state y1y2x = 000


x : 0 1

01

11

10

01

11

10

11

11

10

01

11

10

(00

00

00

01

10

11) (00

00

00

1101

10

11)

Possible transitions

Final total stable

state y1y2x = (111),

011 or 101

Final total stable

state y1y2x = 111,

101Y1Y2 Y1Y2

23

Transition table C Transition table D

©Loberg

Races may be avoided by making a proper binary assignment to the state variables.

Only one state variable can change at any one time when

a state transition occurs in the flow table.

00 01

x0 1

00

y1y2

00 01

x0 1

00

y1y2

Initial total stable

state y1y2x = 000



00 01

11

11

10

00

01

11

10

00 01

11

10

10

00

01

11

10

00 01 11 10 00 01 11

Y1Y2

Final total stable

state y1y2x = 101

Final total stable

state y1y2x = 111

Cycle

Y1Y2

24

x : 0 1

Modified

transition table C

Modified

transition table D

©Loberg

If a cycle does not terminate with a stable state, circuit will be unstable.

00 01

11

x0 1

00

01

y1y2



11

10

01

01

11

10

Example transition tableY1Y2

01 11 10

25©Loberg

The EndThe End

26©Loberg

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