session 22 overview: high-speed data converters

376 • 2014 IEEE International Solid-State Circuits Conference 978-1-4799-0920-9/14/$31.00 ©2014 IEEE

ISSCC 2014 / SESSION 22 / HIGH-SPEED DATA CONVERTERS / OVERVIEW

Session 22 Overview: High-Speed Data ConvertersDATA CONVERTERS SUBCOMMITTEE

22.1 A 90GS/s 8b 667mW 64× Interleaved SAR ADC in 32nm 8:30 AMDigital SOI CMOSL. Kull, IBM Research, Rüschlikon, Switzerland and EPFL, Lausanne, Switzerland

In Paper 22.1, IBM Research (with EPFL) presents a 90GS/s 8b time-interleaved ADC in 32nm SOI CMOS. Itcontains 64 SAR ADC channels. It achieves above 33dB SNDR up to 19.9GHz input frequency and consumes667mW from a 1.2V supply.

22.2 A 69.5mW 20GS/s 6b Time-Interleaved ADC with Embedded 9:00 AMTime-to-Digital Calibration in 32nm CMOS SOIV. H-C. Chen, Carnegie Mellon University, Pittsburgh, PA

In Paper 22.2, Carnegie Mellon University presents a 20GS/s 6b time-interleaved ADC in 32nm SOI CMOS. Itcontains 8 flash ADC channels and features on-chip calibration to reduce inter-channel mismatches in thebackground. It achieves 30.7dB SNDR up to Nyquist and consumes 69.5mW from a 0.9V supply.

22.3 A 20GHz-BW 6b 10GS/s 32mW Time-Interleaved SAR ADC 9:30 AMwith Master T&H in 28nm UTBB FDSOI TechnologyS. Le Tual, STMicroelectronics, Crolles, France

In Paper 22.3, STMicroelectronics presents a 10GS/s 6b time-interleaved ADC in 28nm ultra thin body andBOX fully depleted SOI CMOS. It contains 8 SAR ADC channels. It uses a master T/H that enables 20GHz inputsampling without the need for timing skew calibration. It achieves 4.6 ENOB at 20GHz input and consumes32mW from a 1V supply.

This session demonstrates design techniques to realize data converters with unprecedented combinations of speed, resolution, andpower efficiency in advanced CMOS technologies. Papers in this session include a time-interleaved ADC with a sampling rate up to90GS/s, a time-interleaved DAC at 4.6GS/s conversion rate, and a time-based 2.2GS/s ADC. These converters are essential forsystems enhanced by digital signal processing, such as optical communications, wireline communications, broadband satellitereceivers, and cable systems.

Session Chair: Jieh-Tsorng WuNational Chiao-Tung University, Hsinchu, Taiwan

Session Co-Chair: Seung-Tak RyuKAIST, Daejeon, Korea

377DIGEST OF TECHNICAL PAPERS •

ISSCC 2014 / February 12, 2014 / 8:30 AM

22.4 A 1GS/s 10b 18.9mW Time-Interleaved SAR ADC with 10:15 AMBackground Timing-Skew CalibrationS. Lee, Massachusetts Institute of Technology, Cambridge, MA

In Paper 22.4, MIT presents a 1GS/s 10b time-interleaved ADC in 65 nm CMOS. It contains 8 SAR ADC channels. It features a full-rate 4b flash ADC for sub-ranging and timing skew calibration. It achieves 51.4dBSNDR at Nyquist and consumes 18.9mW from a 1V supply.

22.5 A 1.62GS/s Time-Interleaved SAR ADC with Digital Background 10:45 AMMismatch Calibration Achieving Interleaving Spurs Below 70dBFSN. Le Dortz, STMicroelectronics, Crolles, France and Supélec, Gif-sur-Yvette, France

In Paper 22.5, STMicroelectronics (with Supélec) presents a 1.62GS/s 9b time-Interleaved ADC in 40nmCMOS. It contains 12 SAR ADC channels. It uses a digital calibration unit to estimate and correct inter-channelmismatches in the converter backend. It achieves 48dB SNDR and demonstrates interleaving spurs below -70dBFS up to 750MHz input frequency, while consuming a total power of 93mW.

22.6 A 2.2GS/s 7b 27.4mW Time-Based Folding-Flash ADC with 11:15 AMResistively Averaged Voltage-to-Time AmplifiersM. Miyahara, Tokyo Institute of Technology, Tokyo, Japan

In Paper 22.6, the Tokyo Institute of Technology presents a 2.2GS/s 7b time-based folding ADC in 40nmCMOS. With no need for calibration, it achieves 37.4dB SNDR at Nyquist. It consumes 27.4mW from a 1.1Vsupply.

22.7 A 14b 4.6GS/s RF DAC in 0.18µm CMOS for Cable 11:45 AMHead-End SystemsD. McMahill, Maxim Integrated, Woodstock, GA

In Paper 22.7, Maxim Integrated presents a 4.6GS/s 14b time-interleaved DAC in 0.18µm CMOS. It containstwo current-steering DAC channels. It provides 80mA of output current and achieves -79dBc IMD with a500MHz output without trimming or calibration. It consumes a total power of 2.3W.

22

378 • 2014 IEEE International Solid-State Circuits Conference

ISSCC 2014 / SESSION 22 / HIGH-SPEED DATA CONVERTERS / 22.1

22.1 A 90GS/s 8b 667mW 64× Interleaved SAR ADC in 32nm Digital SOI CMOS

Lukas Kull1,2, Thomas Toifl1, Martin Schmatz1, Pier Andrea Francese1,Christian Menolfi1, Matthias Braendli1, Marcel Kossel1, Thomas Morf1,Toke Meyer Andersen1, Yusuf Leblebici2

1IBM Research, Rüschlikon, Switzerland, 2EPFL, Lausanne, Switzerland

Forthcoming optical communication standards such as ITU OTU-4 and100/400Gb/s Ethernet require ADCs with more than 50GS/s and at least 5 ENOBto enable complex equalization in the digital domain. SAR ADCs and interleavedADCs made impressive progress in recent years. First CMOS ADCs with at least6b and conversion rates exceeding 20GS/s were presented [1-3], proving thatinterleaved SAR ADCs are an optimal choice for high-speed ADCs with moderateresolution. We present an interleaved CMOS ADC architecture based on an asynchronous redundant SAR ADC core element. It was measured up to a sampling rate of 100GS/s and can be operated from a single supply voltage. At90GS/s, the measured SNDR stays above 36.0dB SNDR up to 6.1GHz and33.0dB up to 19.9GHz input frequency while consuming 667mW. The ADC isimplemented in 32nm digital SOI CMOS and occupies 0.45mm2.

Figure 22.1.1 shows a top-level overview of the ADC. The differential input is terminated by 2×50Ω, protected with reduced ESD-diodes and directly connect-ed to the 4 sampling and interleaving slices that feed buffered samples to 16sub-ADCs. Therefore a total of 64 sub-ADCs convert the analog samples. Theaggregated digital output is captured by a large high-speed memory block storing 8192 digitized samples. The architecture requires only 4 timing-criticalclock phases, namely those connected to the first input sampling switches.These critical phases are derived from a half-rate differential clock ck2 of up to50GHz, which is divided by 2 in CML and converted to CMOS levels. An externally controlled digital signal dskew serves to adjust the skew between the4 phases with a step size of less than 30fs. A separate sub-clock generationblock receives the 4 clock phases and generates all non-timing-critical sub-clocks for the interleaver and sub-ADCs.

The core of the ADC consists of the sampling stage and interleaving architecture,as shown in Fig. 22.1.2. Sampling is implemented in voltage mode. Each of the4 sampling switches M1 is connected in series with a 1 by 4 demux stage,formed by transistors M2, before connecting to the sampling capacitors Cs.Implementing 4 interleaved sampling switches and a 1:4 demux stage proved tobe optimum for highest bandwidth while still providing sufficient hold time onthe sampling capacitor to buffer the sampled voltage. Single NMOS samplingswitches are fast and provide sufficient linearity for an 8b ADC. Size and operat-ing point of the sampling transistors are optimized for high bandwidth and highlinearity across corners, with operating temperatures up to 100°C. One of the 4demux switches is enabled by en16 before the rising edge of ck4 and disabledafter the falling edge of ck4 to eliminate influences of en16 on the sampling win-dow. The sampling capacitor Cs is reset shortly before the sampling window byres16. The signal en16 is enabled before res16 is disabled to eliminate ISI bycanceling remaining charges on transistor M1 from the preceding samplingphase. This leaves about 120ps hold time of the sampled voltage on Cs. A sourcefollower (M3 and M4) is chosen to buffer the sampled voltage because of itssuperior speed, noise figure and linearity. For high linearity, the source followeris operated with an output common mode of close to half the supply voltage. Itsoutput common mode also defines the common mode of the sub-ADC andtherefore the comparator. Control of the comparator common mode enables agood trade-off between conversion speed and comparator input-referred noise[4]. The buffered voltage is connected through a second demux stage (M5) controlled by en64 to the capacitive DAC of a SAR ADC. Signal en64 is also usedto trigger the conversion of the asynchronous SAR ADC. Both demux stages inthe interleaver feature cross-coupled NMOS switches, with gates connected toGND to cancel signal feed-through.

The asynchronous SAR ADC shown in Fig. 22.1.3 features a redundant capacitive DAC with a constant common mode and alternate comparators forenhanced speed. The SAR ADC is described in detail in [4]. A falling edge onen64 starts the asynchronous conversion and a rising edge of en64 resets theADC if it did not finish. The alternate comparators eliminate the reset phase ofthe comparator from the critical path, thus increasing speed by about 30%.While one comparator is active, the other comparator resides in reset state, and

vice versa. The capacitive DAC is reset at the end of the conversion to eliminateISI and zero the offset of the comparators. A low-power switch-capacitor reference buffer [5] is controlled with Vgain from an R-3R ladder to adjust thegain of each SAR ADC. The digital input dgain is set externally and enables per-channel gain calibration.

The ADC is manufactured in a 32nm SOI CMOS process with an area of470x960μm2. The interleaver/sampler and 64 SAR ADCs occupy 370x960μm2

and the clock divider 90x100μm2. The ADC supply on the interleaver, includingsampler, CML clock divider and CML to CMOS stages (VDI), is 1.2V for 90GS/s,and the SAR ADC supply (VDA) is set to the same level for 90GS/s. To savepower, VDA can be lower than VDI for lower conversion rates. At 1.2V and 90GS/s,the measured total power consumption of 667mW consists of 56mW for theCML clock divider and CML to CMOS stages, 112mW for the interleaver/samplerand sub-clock generation, and 499mW for the SAR ADCs including drivers forthe memory block.

Gain calibration is performed off-chip with on-chip fine-grain adjustment on theR-3R ladders of each SAR ADC. The internal offset of the comparators is corrected in background in each SAR ADC, whereas the residual offset betweenthe ADC channels is subtracted off-chip. For each supply voltage and conversionrate, gain and offset are calibrated only once at 2.1GHz input frequency. For better sensitivity, skew is calibrated once at a higher input frequency of 19.9GHz.Bandwidth mismatch is not calibrated.

Figure 22.1.4(a) shows SNDR vs. input frequency. More than 36.0dB is achievedup to 6.1GHz and 33.0dB up to 19.9GHz. The measurement series at 100GS/s istaken with skew calibration disabled, therefore the SNDR at higher input frequencies is limited by phase mismatch of the 4 input clock phases. With skewcalibrated, lower SNDR at higher input frequencies mainly stem from thereduced amplitude due to the limited bandwidth, as shown in Fig. 22.1.4(b).Total jitter of individual measurements (8192 samples), including the externalclock and input signal generators, is estimated to approx. 60fs based on modulo-time plot analysis and SNR comparison at different input frequencies at90GS/s. This is in good agreement with jitter simulations that depending on corners, predict 30 to 50fs jitter. The ADC is measured with sampling frequencies from 56GHz to 100GHz (see Fig. 22.1.5(a)). Owing to the asynchronous design of the sub-ADC, the SNDR decreases gradually whensome SAR cycles are no longer completed. Figure 22.1.5(b) shows the powerconsumption vs. sampling frequency. As can be seen at 70GS/s, power consumption highly depends on VDA. 100GS/s was achieved at 1.27V on VDI andVDA with a reduced reset time of the capacitive DAC inside the SAR ADCs at the end of the conversion cycle. Best FoM is achieved at 70GS/s with 121fJ/conversion-step. FoM at 90GS/s is higher with 203fJ/conversion-step,mainly because of the increased voltage on the SAR ADCs.

SFDR of 41.4dB at 19.9GHz input frequency and full-scale input amplitude is limited by 3rd-order harmonic distortion (see Fig. 22.1.6(a)). Figure 22.1.6(b)compares the performance of high-speed CMOS ADCs with at least 6b resolution. As shown in the comparison table, this design exhibits the highestsampling frequency of previously reported 6b+ CMOS ADCs. The FoM is morethan 50% lower and the technology-adjusted area is 4 times smaller than other6b+, >20GS/s ADCs [1,7].

References:[1] Fujitsu Semiconductor Europe, LUKE-ES 55–65 GSa/s 8 bit ADC, Mar. 2012,http://www.fujitsu.com/downloads/MICRO/fme/documentation/c63.pdf,Accessed Sept. 2013.[2] Y. M. Greshishchev, et al., “A 40GS/s 6b ADC in 65nm CMOS,” ISSCC Dig.Tech. Papers, pp. 390–391, Feb. 2010.[3] P. Schvan, et al., “A 24GS/s 6b ADC in 90nm CMOS,” ISSCC Dig. Tech.Papers, pp. 544–545, Feb. 2008.[4] L. Kull, et al., “A 3.1mW 8b 1.2GS/s Single-Channel Asynchronous SAR ADCwith Alternate Comparators for Enhanced Speed in 32nm Digital SOI CMOS,”ISSCC Dig. Tech. Papers, pp. 468–469, Feb. 2013.[5] L. Kull, et al., “A 35mW 8b 8.8GS/s SAR ADC with Low-Power CapacitiveReference Buffers in 32nm Digital SOI CMOS,” IEEE Symp. VLSI Circuits, pp.260–261, June 2013.[6] E. Z. Tabasy, et al., “A 6b 10GS/s TI-SAR ADC with Embedded 2-Tap FFE/1-Tap DFE in 65nm CMOS,” IEEE Symp. VLSI Circuits, pp. 274-275, June 2013.[7] B. Murmann, “ADC Performance Survey 1997-2013,” [Online]. Available:http://www.stanford.edu/~murmann/adcsurvey.html.

978-1-4799-0920-9/14/$31.00 ©2014 IEEE



Figure 22.1.1: Architecture of the highly interleaved SAR ADC with a timingdiagram of the clock signals defining the sampling time.

Figure 22.1.2: Schematic details of the differentially implemented 1:64 interleaver.

Figure 22.1.3: SAR ADC architecture [4] with last demux stage of the interleaver and corresponding timing diagram.

Figure 22.1.5: SNDR and power vs. sampling frequency for different supplyvoltages.

Figure 22.1.6: Spectrum of a 19.9GHz full-scale input signal and performancecomparison table.

Figure 22.1.4: Measured SNDR and amplitude vs. input sine frequency for different sampling frequencies referred to 2.1GHz input frequency.

22

• 2014 IEEE International Solid-State Circuits Conference 978-1-4799-0920-9/14/$31.00 ©2014 IEEE

ISSCC 2014 PAPER CONTINUATIONS

Figure 22.1.7: Chip micrograph and layout. The 96kb memory block stores8192 samples with Hamming encoding.



22.2 A 69.5mW 20GS/s 6b Time-Interleaved ADC with Embedded Time-to-Digital Calibration in 32nm CMOS SOI

Vanessa Hung-Chu Chen, Lawrence Pileggi

Carnegie Mellon University, Pittsburgh, PA

Low-power time-interleaved ADCs with high sampling rates of over 10GS/s arein high demand for wireline communication systems. However, the time-interleaved channels suffer from process mismatch, particularly for timing skew.Although a power-consuming two-rank track-and-hold (T/H) can prevent suchtiming-skew problems, distributed T/Hs can be used for lower-power operationwith timing-skew calibration to meet the skew specifications of 200fsrms for 6bresolution and 10GHz input signals. Instead of using software calibration withFourier analysis [1-3], requiring a special input reference signal [4], or relying onthe statistics of the input signal [5], this work presents a low-complexity on-chipbackground calibration technique to reduce gain, offset, and delay mismatchesbetween channels. This enables small-size transistors to be used in comparatorsand clock delivery circuits to avoid serious noise coupling and save considerablepower for such an ultra-high-speed system. The presented 8-way time-interleaved 20GS/s 6b ADC achieves an SNDR of 30.7dB at Nyquist andconsumes only 69.5mW.

Figure 22.2.1 illustrates the time-interleaved ADC architecture. After power optimization between the channel number and clock buffers, it consists of 8flash-type sub-ADCs, one extra channel for background calibration, a delay-locked loop (DLL) as a phase generator, an 8b low-frequency current-DAC as areference signal source, and an on-chip calibration processor. The sub-ADCoperates at 2.5GS/s with 6b resolution and each sub-ADC is clocked 50ps afterthe previous channel. The DLL is driven by a 2.5GHz clock to generate 8 phasesfor each slice.

Figure 22.2.2 shows the sub-ADC architecture with timing diagram. The T/H utilizes bottom-plate sampling and the input switch is bootstrapped for betterlinearity and higher bandwidth. The fast-tracking feature that VGS of M1 alwaystries to go above VDD speeds up signal tracking compared to the conventionalbootstrapped switch [6]. The low input capacitance of the comparator arrayallows the use of a sampling capacitor of only 100fF. The comparator in the sub-ADC consists of a gain-enhanced pre-amplifier and a regenerative latching stage.The 63 pre-amplifiers are designed with unbalanced loading ratios to shift offsetdistributions to span the 300mVpp full-scale range that eliminates the need forreference resistors. Each pre-amplifier input is constructed of 12 selectableminimum-sized differential pairs to enable dynamic offset calibration [7]. Thiseffectively characterizes the comparator array with 126 checking steps to compensate for parasitic capacitor mismatches that occur during high-speedoperation. The digital outputs from Wallace tree encoder are decimated for test.

Since all the built-in offsets of sub-ADCs including the extra channel, ADCREF, arereferred to the same transfer curve generated by an on-chip current DAC, the offset and gain mismatches among all the channels are calibrated by dynamicoffset calibration along with the comparator offset variations. Then the timingskew is calibrated with ADCREF to build reference timing windows. A moving signal, VCAL, generated from the current DAC with a delay-variable clock isapplied to ADCREF as an input signal to generate a time-to-digital table, as shownin Fig. 22.2.3. ADCREF is clocked externally at CLKREF with a different clock periodof (8Ts+Ts), where Ts is the sampling period of the overall ADC, such that theedges of CLKREF coincide with the ideal sampling points of each sub-ADC. TheDAC input is a periodic signal with a period of 144Ts to generate a 2-level movingsignal. DAC clock, CLKDAC, is controlled by the programmable delay line with astep size ΔT of 100fs. While the sampling point falls within the range of tk to tk+1,ADCREF outputs HIGH as CLKDAC is programmed with delay tk, and ADCREF outputsLOW as CLKDAC is programmed with delay tk+1. 200 digital outputs are observedfor each delay to reduce the jitter influence on the calibration. By sensing all the8 transition points of CLKREF with this embedded time-to-digital conversion, thecorresponding delay-controlling information for calibrating the sampling point ofeach sub ADC is stored in the digital domain.

To calibrate sampling points of each sub-ADC sequentially, the correspondingdelay-controlling codes are used to adjust CLKDAC to generate moving signals for

each sub-ADC, as shown in Fig. 22.2.4. CLKDAC is programmed with 2 delay-controlling codes to generate a timing-checking window to detect the samplingpoint of the sub-ADC under calibration. As the sub-ADC outputs HIGH and LOWcorrespondingly, the sampling point of the sub-ADC is detected in the targetrange between tk and tk+1. The sub-ADC delay is feedback-controlled by choosinga combination set of 6 elements from 12 selectable units in the aligning buffer.Therefore, a large search space provides high-resolution tuning steps for delayalignment of sub-ADCs to CLKREF edges. Without the need of knowing lead/lagof the clock, analysis of sub-ADC outputs only requires accumulators to calculate the HGH/LOW status. The calibration requires low-complexity hardware and ensures that the condition of the sub-ADC under calibration issimilar to the situation during normal operation.

To allow background calibration, ADCREF is also used to periodically substitutefor the main channel that requires calibration next. ADCREF is primarily used tocollect the timing information of 8 sampling edges before starting timing skewcalibration. Therefore, the low-complexity calibration only requires the overheadof one extra sub-ADC, one DAC, and calibration logic, which comprises only25% of the overall area and 13.5% of power consumption when the calibrationis on.

The 6b time-interleaved ADC is implemented in a 32nm CMOS SOI process. Thecalibrated DNL and INL of the ADC are +0.47/-0.42 and +0.42/-0.38 LSB, respectively. Figure 22.2.5 shows the output spectrum with 8.18GHz inputbefore and after timing-skew calibration, and the measured SNDR versus inputfrequency at 20GS/s. The ADC achieves an SNDR of 34.8dB (5.49ENOB) at lowinput frequencies and 30.7dB (4.81ENOB) at Nyquist. The performance at highinput frequencies degrades due to external clock jitter (<0.1psrms), the clock circuitry jitter, and residual timing skew. The estimated total jitter is 0.3psrms

after removing harmonic tones, and the estimated timing skew after calibrationis <0.15psrms. Without recalibration, over the 0-to-70°C temperature range theSNDR is degraded by 10dB. However, the ADC can be completely recalibratedat a rate of 2Hz or below without interrupting its normal operation in order tocompensate for this temperature sensitivity. The total power consumption at20GS/s while calibration is off is 69.5mW (excluding I/O and input clock buffers)from a 0.9V supply voltage, of which 57.6mW is dissipated in the 8 sub-ADCs,and 11.9mW in the 8-phase generator. The occasionally-on calibration consumes 7.2mW in ADCREF, 3.2 mW in the DAC, and 0.5mW in the calibrationlogic. For comparison with other state-of-the-art works, the figure of merit ofpower/(2ENOB×fs) is used. The ADC achieves 123.9fJ/conv-step at Nyquist and77.3fJ/conv-step at low input frequencies. Performance and comparisons aresummarized in Fig. 22.2.6. The chip micrograph is shown in Fig. 22.2.7, and theADC occupies an active area of <0.25 mm2. For high-speed ADCs with over10GS/s sampling rates, the presented design achieves the best reported powerconsumption and figure of merit among those in our table of recent state-of-the-art ADCs in this category (Fig. 22.2.6).

Acknowledgments:The authors thank the support of FCRP C2S2 and R. Carley, J. Weldon, J.Paramesh, and E. Chen of CMU, J.-O. Plouchart of IBM, and C.-C. Lee of Realtekfor discussion.

References:[1] K. Poulton, et al., “A 20GS/s 8b ADC with a 1MB Memory in 0.18μm CMOS,”ISSCC Dig. Tech. Papers, pp. 318-319, Feb. 2003.[2] P. Schvan, et al., “A 24GS/s 6b ADC in 90nm CMOS,” ISSCC Dig. Tech.Papers, pp. 544-545, Feb. 2008.[3] Y. M. Greshishchev, et al., ”A 40GS/s 6b ADC in 65nm CMOS,” ISSCC Dig.Tech. Papers, pp. 390-391, Feb. 2010.[4] C.-C. Huang, C.-Y. Wang, and J.-T. Wu, “A CMOS 6-bit 16-GS/s Time-Interleaved ADC Using Digital Background Calibration Techniques,” IEEE J.Solid-State Circuits, vol. 46, no. 4, pp. 848–858, Apr. 2011.[5] M. El-Chammas and B. Murmann, “A 12-GS/s 81-mW 5-bit Time-InterleavedFlash ADC with Background Timing Skew Calibration,” IEEE J. Solid-StateCircuits, vol. 46, no. 4, pp. 838–847, Apr. 2011.[6] E. Alpman, et al., “A 1.1V 50mW 2.5GS/s 7b Time-Interleaved C-2C SAR ADCin 45nm LP Digital CMOS,” ISSCC Dig. Tech. Papers, pp. 76-77, Feb. 2009.[7] V. H.-C. Chen and L. Pileggi, “An 8.5mW 5GS/s 6b Flash ADC with DynamicOffset Calibration in 32nm CMOS SOI,” Symp. VLSI Circuits, pp. 264-265, June2013.

978-1-4799-0920-9/14/$31.00 ©2014 IEEE



Figure 22.2.1: Architecture of the 6b time-interleaved ADC. Figure 22.2.2: Structure of the sub-ADC.

Figure 22.2.3: The moving signal to sense the sampling edges of the clocks.

Figure 22.2.5: Measured output spectrum with Fin=8.18GHz and SNDR v.s.input frequency before and after timing-skew calibration at 20GS/s. Figure 22.2.6: Performance summary and comparison with the state of the art.

Figure 22.2.4: Timing skew calibration with the time-to-digital table andaligning buffers.

22



Figure 22.2.7: Chip micrograph.



22.3 A 20GHz-BW 6b 10GS/s 32mW Time-Interleaved SAR ADC with Master T&H in 28nm UTBB FDSOI Technology

Stéphane Le Tual1, Pratap Narayan Singh2, Christophe Curis3, Pierre Dautriche1

1STMicroelectronics, Crolles, France, 2STMicroelectronics, Greater Noida, India, 3STMicroelectronics, Grenoble, France

To sustain ever-growing data traffic, modern wireline communication devices(over copper or fiber optic media) require a high-speed ADC in their receive pathto do the digital equalization, or to recover the complex-modulated information.A 6b 10GS/s ADC able to acquire up to 20GHz input signal frequency and showing 5.3 ENOB in Nyquist condition is presented. It is based on a MasterTrack & Hold (T&H) followed by a time-interleaved synchronous SAR ADC, thusavoiding the need for any kind of skew or bandwidth calibration. Ultra Thin Bodyand BOX Fully Depleted SOI (UTBB FDSOI) 28nm CMOS technology is used forits fast switching and regenerating capability. The core ADC consumes 32mWfrom 1V power supply and occupies 0.009mm2 area. The FoM is 81fJ/conversionstep.

An input driver made of a PMOS GmR stage (Fig. 22.3.1) buffers the on-chip50Ω matched differential input signal. Gm is 25mS and R is 40Ω to keep lowimpedance driving of the Master T&H. The current consumed in this stage isabout 10mA. The high-frequency continuous-time signal is then sampled andheld by a 20μm×30nm Low-VTH (LVT) NMOS transistor using 1V Forward BodyBias (FBB) to further reduce its VTH and thus lower its ON resistance (Fig.22.3.3). A simple “top-plate sampling” scheme is used without the need for anyswitch bootstrapping or charge-injection cancellation. The sampling capacitor ismade of 100fF routing and metal capacitor. During each hold phase, the sampledcharges are successively shared with one of the 25fF sampling capacitors of thetime-interleaved SARs (Fig. 22.3.2). This eliminates the need for intermediatebuffering that would have been difficult to realize under 1V power supply with50ps half-period for settling time. Signal attenuation penalty is 100fF/125fF,which is acceptable for 6b-resolution ADCs. The 10GHz 0° and 90° externalclocks are used to create the 25ps Track pulses. When integrated onto an SoC,they may be derived from a 10GHz quadrature VCO.

A total of 8 clock cycles are needed to do the sampling, the 6b successiveapproximation, and the reset, leading to a SAR interleaving ratio of 8. Each SARis made of a compact comb capacitor array, a comparator, and 6b registers. Thecapacitor array is made of binary-weighted fingers using the minimum pitch ofthe technology to limit propagation effects in the finger connections [1]. Theresulting capacitor array width is less than 7μm. The comparator is made of apreamplifier followed by a clocked inverter [2] that drives a latch (Fig. 22.3.4).The speed performance of the comparator is mainly NMOS-based, and leveragesthe 1V FBB capability. The latch is not clocked and thus burns some current during its reset phase. As a result, it presents a fast regeneration time of <40psfor input smaller than 0.5mV, ensuring low BER at 10GS/s operation. The 6b registers are made of synchronous logic with a maximum of 4 gates delay intheir critical path.

Two reference voltages Vtop and Vbot, together with an intermediate voltage Vc,are embedded on chip. Vc is applied during SAR charge-transfer and reset phases. As described in [3], depending on latch decision, the top plate of eachcapacitor is switched from Vc to either Vtop or Vbot on the positive side of thecapacitor array, and from Vc to either Vbot or Vtop on the negative side of thearray. By contrast to the classical 2-reference-voltage “set and correct” successive approximation algorithm, this 2-reference-voltage plus 1-intermediate-voltage “decide right” scheme makes the switching operationsymmetrical, drawing the same current from the references whatever the decision is. It results in a very low dependency of the charge drawn from the references as a function of the input voltage, enabling a low-power design for thereferences (less than 2mA here). Additionally, only 5 capacitors instead of 6 inthe classical way are needed to do the 6b quantization.

After quantization, each SAR stores its 6b word in 2 ping-pong 512-word RAMsrunning at 10GHz/8/2=625MHz. The total 8K words are finally read at low speedthrough a JTAG controller.

The chip is fabricated in 28nm CMOS UTBB FDSOI technology, using 10 metallayers and MIM capacitors for decoupling. Each SAR occupies 50×13μm2

(0.0007mm2) and the complete ADC core is 80×115μm2 (0.009mm2). It ismounted in a soft polymeric substrate (PTFE) with a cavity for the die gluing,such that bonding wires are kept as small as possible (Fig. 22.3.7).

Measurement results at 10GS/s are presented in Fig. 22.3.5. Offset mismatchbetween the 8 SARs is not calibrated on-chip and leads to 1.5dB penalty indynamic range. In the following results, signal amplitude is thus set at -3dBFSand offset spurs are calibrated off-chip. At 4.8GHz input, ENOB is 5.3 and is thermal-noise limited. ENOB is still 4.6 at 20GHz input, limited by single-endedclock jitter (that can be calculated to 260fsrms). THD and SFDR are maintainedbelow 40dB over the whole bandwidth, and they are mainly due to input driverdistortion. No gain or skew spurs are visible, demonstrating the efficiency of theMaster T&H and the timing accuracy between the Master T&H and the 8 SARsampling capacitors.

This work compares favorably with [4-7], as depicted in Fig. 22.3.6. It shows81fJ/conversion step in Nyquist conditions with a very small 0.009mm2 area andit has up to 20GHz sampling capability without any need for gain & skew calibration, which makes it ideal for further higher-speed interleaving (100Gb/soptical links for instance).

In conclusion, we demonstrate in this work the efficiency of the pure passive“sampling and redistribute” concept for signals up to 20GHz. Together with thelow-power capability of the 28nm CMOS UTBB FDSOI technology, we can reach10GS/s operation while keeping the power consumption at 32mW under 1V supply.

Acknowlegments:The authors thank Alex Zabroda for initial concept discussions, Philipp Ritter andMartin Müller from Saarland University for module fabrication & chip assembly,and Dimitri Goguet for bench set-up and measurements.

References:[1] J. Bach, “Capacitive Array”, US Patent 7,873,191 B2, May 2005.[2] D. Schinkel, et al., “A Double-Tail Latch-Type Voltage Sense Amplifier with18ps Setup+Hold Time,” ISSCC Dig. Tech. Papers, pp. 314-315, Feb. 2007.[3] S. Le Tual, et al., “Differential Successive Approximation Analog to DigitalConverter”, US Patent 8,497,795 B2, June 2010.[4] M. El-Chammas and B. Murmann, “A 12-GSps 81-mW 5-bit Time-InterleavedFlash ADC With Background Timing Skew Calibration,” IEEE J. Solid-StateCircuits, vol. 46, pp. 838-847, Apr. 2011.[5] S. Verma, et al., “A 10.3GS/s 6b Flash ADC for 10G Ethernet Applications,”ISSCC Dig. Tech. Papers, pp. 462-463, Feb. 2013.[6] E. Z. Tabasy, et al., “A 6b 10GS/s TI-SAR ADC with Embedded 2-Tap FFE/1-Tap DFE in 65nm CMOS,” IEEE Symposium on VLSI Circuits, pp. C274-C275,June 2013.[7] L. Kull, et al., “A 35 mW 8b 8.8 GS/s SAR ADC with Low-Power CapacitiveReference Buffers in 32nm Digital SOI CMOS,” IEEE Symposium on VLSICircuits, pp. C260-C264, June 2013.

978-1-4799-0920-9/14/$31.00 ©2014 IEEE



Figure 22.3.1: ADC block diagram. Figure 22.3.2: Master T&H and charge-redistribution timing diagram.

Figure 22.3.3: Fully Depleted Silicon-on-Insulator LVT transistors (flipped-well).

Figure 22.3.5: Output spectrum at 10GS/s. Figure 22.3.6: Performance summary and state-of-the-art comparison.

Figure 22.3.4: Comparator schematic.

22



Figure 22.3.7: Die photo in its chip-on-board cavity



22.4 A 1GS/s 10b 18.9mW Time-Interleaved SAR ADC with Background Timing-Skew Calibration

Sunghyuk Lee, Anantha P. Chandrakasan, Hae-Seung Lee

Massachusetts Institute of Technology, Cambridge, MA

SARs are one of the most energy-efficient ADC architectures for medium resolution and low-to-medium speed. To improve the limited bandwidth of SARADCs, the time-interleaved (TI) structure is often used [1,2]. However, TI ADCshave several issues caused by mismatches between channels, such as offset,gain, and timing-skew errors. Unlike the other errors, timing-skew causes errorsthat increase with input signal frequency. Considering that the TI structure istypically employed to increase bandwidth, timing-skew can be a dominant errorsource of TI ADCs. Recent works [1,3] have demonstrated a background timing-skew calibration using a dedicated additional channel as a timing reference. Inthis work, we present a TI SAR ADC that enables background timing-skew calibration without a separate timing reference channel and enhances the conversion speed of each channel.

Figure 22.4.1 shows the block diagram and timing waveform of the 8-way TISAR ADC. The ADC is composed of a clock generator, a flash ADC, 8 SAR ADCs,and digital circuits for bit combining and multiplexing. The timing-skew estimator controls the programmable delay circuits in the clock generator to correct the timing-skew. The flash ADC, operating at the full sampling rate (Φ)of the TI ADC, is multiplexed to resolves 4 MSBs of each of the SAR channels[4]. Because the full-speed flash ADC does not suffer from timing-skew errors,the flash ADC output is also used as the timing reference to estimate timing-skew of SAR ADCs. SAR ADCs resolve 7 LSBs with 1b redundancy at 1/8 of thesampling rate (Φ1~ Φ8).

The implementation of the flash ADC is shown in Fig. 22.4.2. Each comparatorsamples input signals with a bottom plate switch on two capacitors with differentsizes, which are then switched to the reference voltages. When the referencevoltages settle, the comparators are enabled. The sampling comparators haveseveral advantages over the conventional flash comparators that compare theinput directly with a reference voltage [5]. These include rail-to-rail input range,zero static power, and true fully differential implementation. Although conventional flash comparators with two differential input pairs are topologicallyfully differential, they suffer from lower PSRR and CMRR when input or reference voltages are large. Also, because the sampling circuit of the flash comparator is a scaled version of a SAR ADC, the sampled signals between theSAR and the flash are closely matched. This is important in this work, becausethe sampling clocks of the SAR ADCs must be aligned as closely to the samplingclock of the flash ADC as possible to minimize the timing skew correction range.

Figure 22.4.3 shows the 10b SAR ADC composed of 1024 unit capacitors, acomparator, and SAR logic. MSB DACs have 14 unary-weighted capacitors (sizeof 64) that are controlled by the output of the flash ADC. LSB DACs are composed of binary-weighted capacitors (size of 1 to 64) that are controlled bythe SAR logic. 1b redundancy is added between the flash ADC and the SAR conversion to cover the error from the flash ADC and to extract the timing-skewinformation. Since MSB DACs are set by the flash ADC output, only 7 successiveapproximations are required for a 10b SAR conversion. The final output of eachchannel (DCHANNEL) is the weighted sum of the flash ADC output (DFLASH) and thelower output bits of SAR conversion (DLSAR), DCHANNEL = 64*DFLASH + DLSAR. Toavoid using a high-frequency clock and to increase SAR conversion speed, anasynchronous SAR logic is implemented [6]. A dynamic latch with an offset control is used as the SAR comparator. An offset calibration block, which is acapacitor bank with switches, is added at the output of the comparator. To savearea and power consumption, a 1fF unit capacitor, shown in Fig. 22.4.3, is custom designed. It is a combination of the MIM and MOM structures. The benefit of the MIM structure is that the top and bottom plates can be shieldedfrom each other in the capacitor array and each capacitor can be accessed without adding parasitic capacitance. To increase the density of the capacitance,interdigitated MOM structures are added on M4 and connected to M3 and M5.The programmable delay circuit for the sampling clock is implemented with variable capacitors. 3b binary-weighted capacitors are added in the samplingclock path for coarse (~2ps/code) and fine (~0.8ps/code) delay control.

In this paper, we propose timing-skew calibration based on minimizing the variance of the difference between the flash ADC and channel outputs. The basicprinciple of the timing-skew calibration is to align the falling edge of the SARADC sampling clocks to the falling edge of the flash ADC sampling clock.Considering the threshold variation of the sampling switches, in actuality, thefalling edge of the SAR sampling clock is adjusted so that the sampled signal ofSAR ADCs is the same as the sampled signal of the flash ADC. When the sampled signal of the flash ADC is different from the sampled signal of the SARADC, the coarse estimation from flash ADC is inaccurate. The 1b redundancy inthe SAR conversion corrects the flash ADC errors. In fact, the lower output bitsof SAR conversion (DLSAR) represent precisely the difference between the flashADC output (DFLASH) and the corresponding channel output (DCHANNEL). Thus, thetiming skew minima correspond to the minima of the DLSAR variance. The DLSAR

is first sorted according the DFLASH, then the delay of the SAR sampling clocksthat minimizes the variance of the DLSAR, VAR(DLSAR), is computed. Because thecomputation processes only small signals represented in a short word (DLSAR),we believe the computation is simpler than extending the correlation-based calibration to a multi-bit timing reference [3]. Since it does not have any constraint on the input signal and does not interrupt the normal ADC operation,this calibration can run in the background to track temperature and voltage variations. To save power, the calibration may be initiated only when temperature or voltage fluctuation is detected. Because each comparator in theflash ADC has a sampling circuit, the effective sampling instance of the flashADC may vary depending on the input level. However, the sampling skew amongflash comparators is statistically averaged out by the variance-based calibration.

Figure 22.4.4 shows measured data for the timing-skew calibration. VAR(DLSAR)is plotted against coarse delay control codes of the SAR sampling clocks. 128Kdata are used to calculate each variance value. All channels show a smooth curvewith one minimum. The same process is repeated for the fine delay code to complete the calibration. To demonstrate the possibility of background calibration and to avoid errors from a deterministic input signal, the calibrationis performed over 4 different input frequencies and 2 different input amplitudes,and the differences were insignificant.

The ADC is implemented in 65nm CMOS using 0.78mm2 (Fig. 22.4.7) area. Thetiming skew estimation algorithm is implemented off-chip. Offset errors of theSAR ADCs are calibrated first with a zero-differential DC input. Capacitive SARADCs have negligible gain errors, and the output spectrum with a low-frequencysignal confirmed that gain errors are negligible. The measured output spectrumwith a high-frequency input signal is shown in Fig. 22.4.5. Before the timing-skew calibration, the error tones from timing-skew limit the SNDR andSFDR. After background timing-skew calibration, typical results of 51.4dB SNDR(8.2 ENOB), 60.0dB SFDR, and ±1.0 LSB INL/DNL are achieved at 1GS/s with a479MHz input signal. The power consumption is 18.9mW (clock 3.34mW, flashADC 5.04mW, SAR ADCs 9.18mW, reference 1.35mW), which corresponds to62.3fJ/step FoM. The SNDR versus input frequency, shown in Fig. 22.4.5, illustrates the effectiveness of the timing-skew calibration clearly. Figure 22.4.6summarizes the performance with a comparison to the previously publishedworks with fs>0.8GS/s, SNDR >45dB, and FoM <180fJ/step.

Acknowledgements:This work was supported by MIT Center for Integrated Circuits & Systems,Samsung Fellowship, and TSMC university shuttle program.

References:[1] D. Stepanovic and B. Nikolic, “A 2.8 GS/s 44.6 mW Time-Interleaved ADCAchieving 50.9 dB SNDR and 3 dB Effective Resolution Bandwidth of 1.5 GHz in65 nm CMOS,” IEEE J. Solid-State Circuits, vol. 48, no. 4, pp. 971-982, Apr.2013.[2] H. Hong, et al. “An 8.6 ENOB 900MS/s Time-Interleaved 2b/cycle SAR ADCwith a 1b/cycle Reconfiguration for Resolution Enhancement,” ISSCC Dig. Tech.Papers, pp. 470-471, Feb. 2013.[3] M. El-Chammas and B. Murmann, “A 12-GS/s 81-mW 5-bit Time-InterleavedFlash ADC With Background Timing Skew Calibration,” IEEE J. Solid-StateCircuits, vol. 46, no. 4, pp. 838-847, Apr. 2011.[4] B. Sung, et al. “A Time-Interleaved Flash-SAR Architecture for High SpeedA/D Conversion,” Proc. IEEE ISCAS, pp. 984-987, May 2009.[5] S. H. Lewis and P. R. Gray, “A Pipelined 5-Msample/s 9-bit Analog-to-DigitalConverter,” IEEE J. Solid-State Circuits, vol. 22, no. 6, pp. 954-961, Dec. 1987.[6] S.-W. Chen and R. Brodersen, “A 6b 600MS/s 5.3mW Asynchronous ADC in0.13μm CMOS,” ISSCC Dig. Tech. Papers, pp. 574-575, Feb. 2006.

978-1-4799-0920-9/14/$31.00 ©2014 IEEE



Figure 22.4.1: Block diagram of the TI SAR ADC. Figure 22.4.2: Implementation of the 4b flash ADC (A single-ended version isshown for simplicity).

Figure 22.4.3: Implementation of the 10b SAR ADC (A single-ended version isshown for simplicity).

Figure 22.4.5: Measured output spectrum before and after timing-skew calibration. Figure 22.4.6: Performance summary and comparison table.

Figure 22.4.4: Measured variance of DLSAR against coarse delay of SAR ADCsampling clock (top) with the examples of the DLSAR histogram (bottom) forchannel 1.

22



Figure 22.4.7: Micrograph of the test chip in 65nm CMOS.



22.5 A 1.62GS/s Time-Interleaved SAR ADC with Digital Background Mismatch Calibration Achieving Interleaving Spurs Below 70dBFS

Nicolas Le Dortz1,2, Jean-Pierre Blanc1, Thierry Simon1, Sarah Verhaeren1, Emmanuel Rouat1, Pascal Urard1, Stéphane Le Tual1, Dimitri Goguet1, Caroline Lelandais-Perrault2, Philippe Benabes2

1STMicroelectronics, Crolles, France, 2Supélec, Gif-sur-Yvette, France

Today’s applications such as broadband satellite receivers, cable TVs, and software-defined radios require highly efficient ADCs with high sampling ratesand high resolutions. A time-interleaved ADC (TIADC) is a popular architectureused to achieve this goal. However, this structure suffers from mismatchesbetween the sub-converters, which cause errors on the output signal, and moresignificantly, decrease the SFDR. These mismatches can be a severe limitationin applications such as satellite reception, where both narrowband and widebandsignals are used. This paper introduces digital derivative-based estimation oftiming mismatches. Gain, offset and skew mismatch calibrations are performedentirely in the digital domain through equalization.

Recently, multi-GS/s designs using mixed-signal techniques to reduce theeffects of mismatches have been published [1-3]. Mixed calibration techniquesexhibit good performance but they require additional development time. Thisprototype, done in 40nm CMOS technology, implements a 1.62GS/s 12-channel9b TIADC with embedded digital background mismatch calibration. It demonstrates the efficiency of a generalizable and scalable co-design methodology where the analog core is designed without special care for the mismatches. The mismatches are suppressed by a separately designed digitalbackground mismatch calibration unit. Over the range of 0 to 750MHz, the on-chip implementation of this architecture has interleaving spurs below 70dBFSand a SNDR higher than 48dB for a power consumption of 93mW.

The overall structure, shown in Fig. 22.5.1, consists of 12 interleaved 135MS/s9b radix-2 SAR converters followed by a digital mismatch calibration unit. EachSAR resolves 9b in 12 clock cycles. The 1Vpp-diff input signal is delivered to thesub-ADCs via a 1.7V buffer in order to limit kickback noise. Each SAR embedsits own T/H circuit, and bottom-plate sampling is used to reduce charge injection. The top-plate sampling switch is a transmission gate that uses low-Vt

high-performance analog (HPA) transistors to reduce Ron input signal dependency and thus, keep a good linearity (Fig. 22.5.2). In order to reduce thearea while preserving good ratios between the capacitors, a compact, customlayout, lateral structure is used in the 9b radix-2 capacitive DAC as illustrated inFig. 22.5.2 [4,5]. The common bottom plate consists of a metal comb connectedto the input of a latch comparator. The capacitor top plates are made of severalmetal fingers inserted into the bottom-plate comb structure. The capacitor values are proportional to the number and the length of the fingers. The topplates can either be connected to the reference voltages Vn=250mV, Vp=750mV,and Vm=500mV, or the input signal Vin. The sequence of conversion steps shownin Fig. 22.5.1 is managed by the SAR logic that generates the control signals forthe comparator and for the switches.

The 9b samples from the 12 interleaved ADCs are delivered in parallel to the digital mismatch calibration unit that runs in background in order to track mismatch variations. The calibration requires the input signal to be wide-sensestationary and band-limited to the Nyquist frequency. There is no adaptive feedback loop, meaning the signal is corrected after a single iteration, eliminating the potential stability issues encountered with adaptive techniques.

Offset mismatch is cancelled by equalizing the averages of each sub-ADC outputto the average of sub-ADC0 output. The relative offset of one sub-ADC is estimated as the difference between the modified moving averages of its outputsamples and the ones of sub-ADC0. The estimated offsets are then subtractedfrom their respective sub-ADC outputs samples. A random sequence is added tothe estimated offset before the subtraction to spread the residual offset mismatch spurs across the entire spectrum. The 12b offset-corrected samplesare then transmitted to the gain mismatch calibration unit where gain mismatchis corrected. The relative gain each sub-ADC is calculated as the ratio between

the modified moving average of its samples’ absolute values and the modifiedmoving average of sub-ADC0 samples’ absolute values. Gain mismatch is corrected by dividing each sub-ADC’s output by its corresponding gain estimate.

Skew mismatch calibration, whose principle is illustrated in (Fig. 22.5.3), is performed in the last stage. Each sub-ADC output can be seen as a sum of anideal signal and an error term proportional to the timing offset and the signalderivative. The ideal signal is orthogonal to its derivative, meaning that averagingthe product between the sub-ADC output samples and their corresponding derivative samples eliminates the ideal signal component while leaving a skew-dependent term. This term, proportional to the derivative power and the sub-ADC timing offset, is used in the skew calibration unit to recover timing skewestimates. The estimated error signal, calculated as the product between thederivative and the timing skew estimate, is then subtracted from the sub-ADCoutput to recover the ideal samples [6]. The signal derivative is obtained bypassing the TIADC gain-corrected samples through a differentiating FIR filter [6],whose coefficients are chosen such that its frequency response is accurate up to750MHz. After skew mismatch calibration, the 12×12b digitally corrected signalsare multiplexed and delivered at the output of the chip.

The test chip is fabricated using STMicroelectronics 40nm CMOS technologyand is comprised of two of the previously described TIADCs (Fig. 22.5.7). Thedigital part has a 1.1V supply voltage similar to the analog core and the SARlogic. It is synthesized from a parametric C-code using Calypto Catapult C High-Level-Synthesis tool, making this flow quickly adaptable to any technology andany TIADC architecture.

Fig. 22.5.4 shows the measured performances versus input signal frequency.The SNDR progressively decreases from 51dB at DC to 48dB at a 750MHz inputfrequency, while the SFDR is higher than 62dBFS. The mismatch tones are keptbelow 70dBFS up to 750MHz. This is higher than previously published designs,which achieve, at best, 60dBFS [3] up to 90% of the Nyquist frequency. Above750MHz, the performance deteriorates due to the limited accuracy of the derivative filter in that frequency range. For full-scale sine inputs, the SFDR isultimately limited by the harmonic distortion caused by the input buffer non-linearity. The THD is maintained below -58dB up to the Nyquist frequency. Thisis as good as previously published designs [1-3] that use additional linearity calibration circuitry. Figure 22.5.5 shows the performances of the TIADC on amodulated signal, which is more likely found in practical applications. In thiscase, the buffer non-linearity is not a limitation, whereas mismatches createunwanted frequency components. At Fs=1.62GS/s the power consumption of the0.83mm2 TIADC including the digital background calibration, the references, andthe input buffer is 93mW. The digital unit occupies 40% of the total area andconsumes 53% of the total power when running continuously (Fig. 22.5.4). Thisoverhead is offset by the achieved high SFDR and the ability to easily resynthesize the digital unit for any TIADC architecture or technology. In addition, the digital calibration energy overhead will decrease with CMOS technology scaling due to improved digital efficiency.

Acknowledgement:The authors would like to thank Andreia Cathelin and Borivoje Nikolić for theiradvice and support.

References:[1] E. Janssen, et al., “An 11b 3.6GS/s Time-Interleaved SAR ADC in 65nmCMOS,” ISSCC Dig. Tech. Papers, pp. 464-465, Feb. 2013.[2] K. Doris, et al., “A 480mW 2.6GS/s 10b 65nm CMOS Time-Interleaved ADCwith 48.5dB SNDR up to Nyquist,” ISSCC Dig. Tech. Papers, pp. 180-181, Feb.2011.[3] D. Stepanovic and B. Nikolic, “A 2.8 GS/s 44.6 mW Time-Interleaved ADCAchieving 50.9 dB SNDR and 3 dB Effective Resolution Bandwidth of 1.5 GHz in65 nm CMOS,” IEEE J. Solid-State Circuits, vol. 48, no. 4, pp. 971-982, April2013.[4] J. Bach, “Capacitive Array,” US Patent 7,873,191 B2, May 2005.[5] S. Le Tual, et al, “Integrated Capacitive Device and Integrated Analog DigitalConverter Comprising Such a Device,” US Patent Application 2013/0003255 A1,June 2011.[6] V. Divi and G. Wornell, “Blind Calibration of Timing Skew in Time-InterleavedAnalog-to-Digital Converters,” IEEE J. Selected Topics in Signal Processing,vol.3, no.3, pp.509-522, June 2009.

978-1-4799-0920-9/14/$31.00 ©2014 IEEE



Figure 22.5.1: Overall structure of the Time-Interleaved ADC and sequence ofconversion operations.

Figure 22.5.2: Bottom-plate sampling and capacitive DAC schematic with lateral capacitor array layout (not entirely represented).

Figure 22.5.3: Skew mismatch estimation and correction principles.

Figure 22.5.5: TIADC output spectrum before and after mismatch compensation with a sinusoid at 600MHz and a 10MHz bandwidth QAM16modulated signal at Fcarrier = 607MHz.

Figure 22.5.6: Performance comparison with state of the art for input frequencies up to 90% of the Nyquist frequency.

Figure 22.5.4: Performances of the TIADC over the Nyquist frequency range fora -1dBFS sine input and power consumption repartition.

22



Figure 22.5.7: Photo of the die comprised of 2 x 0.83 mm2 Time-InterleavedADCs.



22.6 A 2.2GS/s 7b 27.4mW Time-Based Folding-Flash ADC with Resistively Averaged Voltage-to-Time Amplifiers

Masaya Miyahara, Ibuki Mano, Masaaki Nakayama, Kenichi Okada, Akira Matsuzawa

Tokyo Institute of Technology, Tokyo, Japan

High-speed low-resolution ADCs are widely used for various applications, suchas 60GHz receivers, serial links, and high-density disk drive systems. Flasharchitectures have the highest conversion rate without employing timeinterleaving. Moreover, flash architectures have the lowest latency, which isoften required in feedback-loop systems. However, the area and powerconsumption are exponentially increased by increasing the resolution since thenumber of comparators must be 2N. A folding architecture is a well-known technique to reduce the number of comparators in an ADC while maintaininghigh sampling rate and low latency [1,2]. Folding architectures were previouslyrealized by generating a number of zero crossings with folding amplifiers.However, the conventional folding amplifiers consume a large amount of powerto realize a fast response. In contrast, a folding ADC with only dynamic powerconsumption and without using amplifiers is reported in [3]. However, only afolding factor of 2 is realized, and therefore the number of comparators isreduced by half.

This paper presents a 2.2GS/s 7b time-based folding ADC with resistively averaged voltage-to-time amplifiers (V-T amps). This time-based folding architecture consists of simple logic cells with a folding factor of 8 instead of theconventional static amplifiers. This reduces the number of comparators from128 to 32 for a 7b resolution. Resistively averaged V-T amps have a low offsetvoltage and a high conversion gain to relax the offset requirement for the SR-latch. This ADC achieves an SNDR of 37.4dB at Nyquist frequency withoutany calibration technique.

Figure 22.6.1 shows the block diagram of the ADC. The input signal is sampledon passive S/H circuits with the total sampling capacitance of 300fF. An array of25 V-T amps, 10 of which are dummies to generate extra folding points andovercome the edge effects in resistive averaging networks, converts the sampledvoltages into pulse signals that have a delay time depending on input voltage levels. Next, pulse signals are inputted to the coarse SR latch and the time-basedfolder (TF) blocks. The coarse SR latches compare the delay time and determinethe upper 4b digital code. Four TFs output folded delay signals to the fine interpolated SR latches. The fine interpolated SR latches convert the delay signalto the lower 4b digital code. The encoder corrects coarse and fine digital codesand converts 7b data with 1b redundancy. Finally, 7b data are retimed by D-FFs.

Figure 22.6.2 shows the dynamic V-T amps with resistive averaging. The V-Tamp is based on the dynamic preamp of double-latch-type comparator [4] witha positive feedback circuit. During the reset phase (φL =0), M7 and M8 pre-chargethe DP and DN nodes to the supply voltage. After the reset phase, φL turns to high,M7 and M8 are turned off and M9 is turned on. At DP and DN nodes, the voltagedrops with a rate determined by the input differential voltage, and an input-dependent Δtd builds up in a short time of around 100ps. M5 and M6 forma positive feedback circuit to enhance the gain of the V-T conversion. M3 and M4

control the positive feedback to a suitable ratio because too much positive feedback degrades the linearity of the V-T conversion. In this design, the gainsof the V-T conversion with and without positive feedback are 1.1ps/mV and0.24ps/mV, respectively. The V-T conversion gain with positive feedback isenough to eliminate an offset calibration technique for coarse and fine SRlatches. A resistive averaging technique is a well-known technique used to reduce the mismatch of conventional static amplifiers [5]. This architecture isalso effective in a dynamic amplifier without increasing power consumptionbecause it has no static current path. The offset voltage of the dynamic amplifiercan be reduced to about 1/3.

Figure 22.6.3 shows the TF architecture and the circuit implementation. Delaytimes of V-T amps are slightly different depending on each reference voltage.The first mountain fold can be realized by using OR gates to select the faster

delay signals; D1_1 is DN0 OR DP2 and D1_2 is DN4 OR DP6. The second valley foldcan be realized by using an AND gate to select the slower delay signals; D2_1 isD1_1 AND D1_2. Finally, DF1 can be realized by D2_1 AND D2_2. These logic cellshave symmetrical input to obtain the same transition time from D1 or D2 to output. This architecture consists of simple logic cells with only dynamic powerconsumption. Moreover, this TF performs in very short time, about 100ps,because only 3 cascaded OR and AND cells are required to realize the folding factor of 8. TF block outputs four folding signals, DF1, DF2, DF3 and DF4, to realizeinterpolated signals in the following fine SR latch block.

Figure 22.6.4 shows the fine SR latch circuit with a phase interpolator [6]. First,to realize the time-domain interpolation, the rising slope of the folding signal ismoderated. A 3b phase interpolator consists of 2-stage cascaded inverters. Theinterpolation ratio of the 2b stage is realized by changing the number of theinverters connected to each input, with ratios of 1:3, 2:2, or 3:1. The next interpolator has a fixed ratio of 1:1. Finally, the phase-interpolated delay signalis converted into a digital code by the SR latch, which consists of NAND gates.The coarse SR latch has the same structure without interpolators. The offsetvoltage of the SR latch is negligible because the steep rising signals are less sensitive to Vt mismatch of the transistor. Moreover, the gain of V-T amps effectively reduces the input-referred offset voltage of the SR latch. Therefore, nooffset calibration is required.

The chip is fabricated in a digital 40nm LP CMOS technology and the occupiedarea is 0.052mm2, as shown in Fig. 22.6.7. The supply voltage is 1.1V with apower consumption of 27.4mW (3.3mW for reference ladder, 19.4mW for analog, and 4.7mW for digital) at a sampling rate of 2.2GS/s. The differentialinput signal range is 1.0Vpp. The output code is decimated by 8 in the measurement. The measured DNL and INL are +0.6/-0.6 and +1.0/-1.0 LSB, respectively. Figure 22.6.5 shows the measured SNR, SFDR, and SNDR vs. sampling rate and input frequency. An SNDR of 38.3dB is measured up to2.2GS/s with a 100MHz input frequency. Also, an SNDR of 37.4dB is obtained at2.2GS/s with Nyquist frequency of 1.1GHz. The FoMw of 210fJ/conv.-step andthe FoMs of 143.3dB at Nyquist frequency are achieved.

Figure 22.6.6 shows the performance summary and comparison of flash and folding ADCs achieving a conversion rate of several GS/s [7-9].

Acknowledgments:This work was partially supported by MIC, Berkeley Design Automation for theuse of the Analog Fast SPICE(AFS) Platform, and VDEC in collaboration withCadence Design Systems, Inc.

References:[1] Y. Nakajima, et al., “A Background Self-Calibrated 6b 2.7GS/s ADC WithCascade-Calibrated Folding-Interpolating Architecture,” IEEE J. Solid-StateCircuits, vol. 45, pp. 707-718, Apr. 2010.[2] T. Yamase, et al., “A 22-mW 7b 1.3-GS/s Pipeline ADC with 1-bit/stageFolding Converter Architecture,” Symp. VLSI Circuits, pp. 124-125, June 2011. [3] B. Verbruggen, et al., “A 2.2mW 5b 1.75GS/s Folding Flash ADC in 90nmDigital CMOS,” ISSCC Dig. Tech. Papers, pp. 252-253, Feb. 2008.[4] M. Miyahara, et al., “A Low-Noise Self-Calibrating Dynamic Comparator forHigh-Speed ADCs”, IEEE A-SSCC, pp. 269-272, Nov. 2008.[5] K. Makigawa, et al., “A 7bit 800Msps 120mW Folding and Interpolation ADCUsing a Mixed-Averaging Scheme,” Symp. VLSI Circuits, pp. 124-125, June2006.[6] D. Miyashita, et al., “A -104dBc/Hz In-Band Phase Noise 3GHz All Digital PLLwith Phase Interpolation Based Hierarchical Time to Digital Convertor,” Symp.VLSI Circuits, pp. 112-113, June 2011.[7] B. Murmann, “ADC performance survey 1997-2013,” [Online]. Available:http://www.stanford.edu/˜murmann/adcsurvey.html.[8] Y. -S Shu, “A 6b 3GS/s 11mW Fully Dynamic ADC in 40nm CMOS withReduced Number of comparators,” Symp. VLSI Circuits, pp. 26-27, June 2012.[9] V. H. -C. Chen and L. Pileggi, “An 8.5mW 5GS/s 6b Flash ADC with DynamicOffset Calibration in 32nm CMOS SOI,” Symp. VLSI Circuits, pp. 264-265, June2013.

978-1-4799-0920-9/14/$31.00 ©2014 IEEE



Figure 22.6.1: Block diagram of the time-based folding flash ADC.Figure 22.6.2: Voltage-to-time amplifier with positive feedback for gain boosting and resistive averaging.

Figure 22.6.3: Time-based folder architecture and circuit implementation.

Figure 22.6.5: Measured SNDR vs. sampling frequency and input frequency.Figure 22.6.6: Performance comparison of flash and folding ADCs with sampling rate of several GS/s.

Figure 22.6.4: Interpolated fine SR latches.

22



Figure 22.6.7: Die micrograph.



22.7 A 14b 4.6GS/s RF DAC in 0.18µm CMOS for Cable Head-End Systems

Brian Brandt1, Dan McMahill2, Miaochen Wu1, Paul Kalthoff3, Ajay Kuckreja4, Geir Ostrem3

1Maxim Integrated, North Chelmsford, MA, 2Maxim Integrated, Woodstock, GA,3Maxim Integrated, Colorado Springs, CO, 4Maxim Integrated, Boulder, CO

Cable head-end systems typically employ multiple QAM modulator signal chainsto synthesize the entire TV spectrum for triple-play services, resulting in highpower, cost, and size. The DAC reported here can directly synthesize 160 DOCSIS 3.0 compliant 6MHz QAM channels, spanning the entire cable band of43 to 1003MHz. It thereby enables low-cost, low-power head-end systems fornew cable standards such as the converged cable access platform (CCAP) fortriple/quad play services.

Figure 22.7.1 shows the cable DAC system, comprising a 40nm digital up converter (DUC) and a 180nm DAC co-packaged in a 12×17mm2 BGA multi-chipmodule. The DAC is the primary focus of this paper. The DUC performs QAMmapping, root raised cosine pulse shaping, resampling, and digital RF up-conversion of Forward Error Corrected (FEC) encoded data with full agility. Acascade of interpolation filters, complex modulators, and channel combinersallows modulation of the signal to any frequency from 43 to 1003MHz. The DUCoutput is passed to a simple digital pre-distortion (DPD) block to attenuate a particular residual frequency spur that is associated with the 2-channel interleaving employed in the DAC, as described later. The 4.6GS/s 14b output ofthe DPD is de-multiplexed by 4× and sent to the DAC at 1.15GS/s via 56 LVDSpairs. In the DAC, the LVDS data is latched using a synchronization clock pro-duced by a DLL. The data is then multiplexed into two 2.3GS/s streams for inputto a pair of time-interleaved 14b sub-DACs. Finally, the two sub-DAC outputs arere-timed by a butterfly switch operating at 4.6GS/s. A clock generator provideslow-jitter timing signals to the butterfly and sub-DACs.

The interleaved DAC architecture allows 4.6GS/s operation in 180nm CMOS [1].The butterfly circuit enables this interleaving while simultaneously achieving lowdistortion by retiming the sub-DAC outputs to both edges of a 2.3GHz clock. Thebutterfly serves a second important purpose of retiming the outputs of the segments within each sub-DAC core [2]. To reduce static and dynamic nonlinearity, each 14b sub-DAC is segmented into 4 unary current source arrayscomprising the 5 MSBs, a 4b array, a 3b array, and a 2b LSB array. Because oftiming mismatches, the outputs of these arrays can change at slightly differenttimes. The resulting glitches, which normally degrade dynamic performance, areblocked from the main DAC output by the butterfly switch, which selects theother (settled) sub-DAC output during this time period.

A unique challenge resulting from the interleaved architecture is that the imageof second harmonic distortion in each sub-DAC (at 2.3GHz − 2FSIG) will not generally be fully canceled in the combined DAC output spectrum. This spur haslow amplitude, is very repeatable from part to part, and is constant over temperature because of small unavoidable systematic mismatches and couplings in the layout. As in interleaved ADCs, digital correction of interleaveerrors is advantageous. The simple DPD circuit shown in Fig. 22.7.2 reduces thisspur by >8dB over the entire frequency band and temperature range. A fixed 6-tap FIR filter precedes an adjustable gain/phase block with 2 programmablecoefficients. In practice, gain and phase calibration for individual parts is unnecessary. Next, the signal is squared and modulated by an alternating ±1sequence before summation with the original signal. The DPD occupies0.08mm2 and does not reduce any other spurs, which are sufficiently controlledby careful design and layout.

Figure 22.7.3 depicts a single current source with switches and switch drivers.Two levels of latching are used to fully attenuate signal-dependent delays fromthe decoder. When conducting, each switch also serves as a cascode with itsgate and drain biased at 1.8V. Segmentation, along with careful layout, non-minimum transistor sizes, and randomized current source placement, eliminatethe need for trimming or calibration. Figure 22.7.4 shows a half-circuit of the differential butterfly switch in which 2 differential pairs operating 180° out ofphase alternately steer currents from the 2 interleaved sub-DACs to either theoutput load or the dummy load. An identical half-circuit (not shown) producesthe OUTM DAC output. A low-jitter differential clock drives the two inverters,whose outputs are ac coupled to M1/M2. One of the cross-coupled PMOS pull-up devices (M3/M4) pulls one differential pair input up to 1.8V+Vgs, while

the other input is driven to about 0.25V+Vgs. As a result, the sources of M1/M2,which connect to the drain of the cascode switch in Fig. 22.7.3, are biased at1.8V while their drains are set to 3.3V–Vgs by M7/M8. Accordingly, M1/M2 canbe faster low-voltage 180nm transistors since they are protected from the 3.3Vsupply during normal operation. To protect them during startup, shutdown, oran inactive clock, M5/M6 are turned on by a simple detector (not shown) whenever the supplies or bias currents are not valid or the clock is inactive.

One of the distinguishing features of this DAC is its high output current capabilityof 80mA compared to the typical 16, 20, or 50mA of prior designs [3-6]. TheQAM modulator in the cable head-end is followed by a chain of amplifiers. HighDAC output power minimizes the noise contribution from these amplifiers andeliminates one stage of amplification, thereby reducing system power and cost.To achieve low distortion at the high output power level, the static 40mA currentin Fig. 22.7.4 is added to the 0-to-80mA signal current from the sub-DACs. Thisimproves the settling and large signal behavior of the butterfly switch by reducing current variation in critical signal path transistors. This additional dccurrent is absorbed in the external inductor typically connected to differentialDAC outputs. The chip includes 25Ω resistors on each DAC output (Fig. 22.7.4)to minimize overshoot in the DAC output due to package inductance.

Figure 22.7.5 presents typical measured 2-tone intermodulation distortion(IMD), a better indicator of linearity performance than SFDR for communicationsystems. Low distortion is maintained across the entire cable band. AdjacentChannel Power Ratio (ACPR) is also of primary importance and this DACachieves 55dBc for 160 DOCSIS channels. Notable in the measured results inFig. 22.7.6 are the high update rate and resolution, the low distortion, and thehigh output current achieved in a 180nm technology without trimming or calibration. Several system advantages stem from the high update rate includingsimpler reconstruction filtering with smaller phase errors, reduced quantizationnoise density, and facilitation of DPD for correcting power amplifier distortion.Also the 4.6GS/s update rate provides gain flatness of 1.3dB across the 960MHzcable bandwidth, minimizing the need for analog equalization following the DAC.While power dissipation and die area are comparatively high, they are lessimportant because its performance and output current capability enable a dramatic power and cost reduction at the system level of the cable head-end.This DAC signal chain replaces 20-to-40 octal or quad QAM modulator signalchains that dissipate 500 to 1000W in legacy systems. Each sub-DAC sinks160mA at 3.3V (530mW) comprising an 80mA signal current and two 40mA dccurrents, which improve distortion as described earlier. The low-jitter clock generator consumes 440mA at 1.8V (790mW) due in large part to driving thelarge switches needed to support the high output current and the comparativelylarge parasitic capacitances of the 180nm technology. Thus, most of the DAC’spower dissipation is directly related to producing high output current at 4.6GS/swith low distortion in a 180nm technology. The remaining 450mW is consumedin digital logic, DLL and interface circuits, bias generation, and generally providing wide design margins to enable a robust product with high yield overprocess, supply, and temperature (−40 to 110°C) variations. The DPD dissipatesabout 60mW while the DUC dissipates 2.9W at 0.9V when processing 160 QAMchannels. Figure 22.7.7 shows a die photo of the DAC.

Several techniques are key to achieving the DAC’s performance level, includingan interleaved architecture, a butterfly circuit for segment and interleave retiming, targeted and simple DPD, and design for high output current. The highspeed, low distortion, and high output power achieved in a low-cost CMOS technology without trimming or calibration, enable a significant power, size, andcost reduction for cable head-end systems.

References:[1] D. McMahill and A. Kuckreja, High Speed Digital-to-Analog Converter withLow Voltage Device Protection, US Patent 8,498,086, July 2013.[2] G. Ostrem and A. Kuckreja, Wide band digital to analog converters and methods, including converters with selectable impulse response, US Patent6,977,602, Dec. 2005.[3] G. Engel, et al., “A 14b 3/6GHz Current-Steering RF DAC in 0.18μm CMOSwith 66dB ACLR at 2.9GHz,” ISSCC Dig. Tech. Papers, pp. 458-459, 2012.[4] W. Tseng, et al., “A 12b 1.25GS/s DAC in 90nm CMOS with >70dB SFDR upto 500MHz,” ISSCC Dig. Tech. Papers, pp. 192-193, Feb. 2011.[5] C.-H. Lin, et al., “A 12b 2.9GS/s DAC with IM3 <-60dBc Beyond 1GHz in65nm CMOS,” ISSCC Dig. Tech. Papers, pp. 74-75, Feb. 2009.[6] W.T. Lin, et al., “A 12b 1.6GS/s 40mW DAC in 40nm CMOS with >70dB SFDRover Entire Nyquist Bandwidth,” ISSCC Dig. Tech. Papers, pp. 474-475, Feb.2013.

978-1-4799-0920-9/14/$31.00 ©2014 IEEE



Figure 22.7.1: Cable DAC system (actual DAC implementation is differential). Figure 22.7.2: Digital pre-distortion block diagram.

Figure 22.7.3: Current source, switches, and switch drivers.

Figure 22.7.5: Typical measured IMD performance. Figure 22.7.6: Performance summary and comparison.

Figure 22.7.4: Butterfly switch half-circuit.

22



Figure 22.7.7: Die photo (DAC only, normally packaged flip-chip in an MCM).

session 22 overview: high-speed data converters

Documents