reverse-order-restoration-based static test compaction for synchronous sequential circuits

IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, VOL. 22, NO. 3, MARCH 2003 293

Reverse-Order-Restoration-Based StaticTest Compaction for Synchronous

Sequential CircuitsRuifeng Guo, Member, IEEE, Sudhakar M. Reddy, Fellow, IEEE, and Irith Pomeranz, Fellow, IEEE

Abstract—We present a new static test sequence compactionprocedure called reverse-order-restoration (ROR) for synchronoussequential circuits. It improves the efficiency of the basic vectorrestoration-based compaction procedure by reversing the order ofthe vectors in the original test sequence. This reduces the number offaults to be resimulated after every restoration step. We extend theROR procedure to a class of radix reverse order vector restorationprocedures. These procedures dynamically increase the number ofvectors to be restored in each step and, thus, speed up the vectorrestoration process. We also investigate techniques to improve thecompaction levels achieved by the ROR-based compaction proce-dure. By combining reverse order vector restoration and vectoromission, higher compaction levels are achieved. Experimental re-sults on test sequences generated by several test generators showthe effectiveness of the proposed techniques.

Index Terms—Sequential circuits, static compaction, testsequence compaction.

I. INTRODUCTION

T HE COST of testing a very large scale integration circuitis significantly affected by the length of its test sequence.

Longer test sequences require more tester memory and takelonger times to apply, and, therefore, have a higher cost. Inorder to reduce the length of the test sequence generated for asynchronous sequential circuit, compaction techniques are oftenused. Note that test compaction techniques are different fromtest data compression techniques, which are used to reduce testdata volume and in some cases also to reduce the rate of testdata delivery to and from the circuit under test. Test compactionschemes reduce the test lengths, and test data compression

Manuscript received May 7, 2002; revised September 13, 2002. This workwas supported in part by the National Science Foundation under Grant MIP-9725053 and in part by the Semiconductor Research Corporation under Grant98-TJ-645. This paper is based on the following papers authored by R. Guo, S.M. Reddy, and I. Pomeranz: “On Speeding-Up Vector Restoration Based StaticCompaction of Test Sequences for Sequential Circuits,”Proc. 7th Asian TestSymp., Dec. 1998, pp. 467–471; “PROPTEST: A Property Based Test PatternGenerator for Sequential Circuits Using Test Compaction,”Proc. Design Au-tomation Conf., June 1999, pp. 653–659; “On Improving Static Test Compactionfor Sequential Circuits,”Proc. 14th Int. Conf. Very Large Scale Integration De-sign, Jan. 2001, pp. 111–116. This paper was recommended by Associate EditorK. Chakrabarty.

R. Guo was with the Department of Electrical and Computer Engineering,University of Iowa, Iowa City, IA 52242 USA, and is now with the DiagnosisTechnology Department, Intel Corporation, Hillsboro, OR 97124 USA (email:[email protected]).

S. M. Reddy is with the Department of Electrical and Computer Engineering,University of Iowa, Iowa City, IA 52242 USA.

I. Pomeranz is with the School of Electrical and Computer Engineering,Purdue University, West Lafayette, IN 47907 USA.

Digital Object Identifier 10.1109/TCAD.2002.807885

schemes can then be used on the compacted test sequences.There are two categories of compaction algorithms: dynamiccompaction and static compaction. Dynamic compaction isperformed concurrently with the test generation process. Itcan be considered as part of the test generator [1]–[4]. Staticcompaction techniques are used after test generation, as apost processing step. Thus, static compaction does not requiremodifications to existing test generation procedures. In manycases, the test sequences generated by test generation procedureswith dynamic compaction techniques can be further compactedusing a static test compaction technique.

Various static compaction algorithms have been proposed inthe past [5]–[17]. In [5] and [6],reordering and overlappingare proposed for a set of test subsequences in order to producea single sequence of minimal length. Similarly, the procedureof [7] is applicable to test sets comprised of multiple testsubsequences.

Three static compaction techniques were proposed byPomeranz and Reddy [8] for the case where a single test se-quence is given. They are based onvector omission, insertion,and selection. During the vector omission procedure, testvectors are omitted from the test sequence one at a time orin subsequences. The success of this procedure in achievinghigh levels of compaction has led several other researchers todevelop vector omission-based compaction procedures. Onesuch procedure is the one proposed by Hsiaoet al.[9]. Theprocedure uses repeated states, or states that appear twice ormore along the test sequence, to find subsequences that canbe omitted without reducing the fault coverage. Efficiencyin this procedure is often achieved at a significant loss inthe ability to compact test sequences. An improved versionof this subsequence removal procedure is presented in [10].Because heuristic techniques are used in [9] and [10], somefaults detected by the original sequence may not be detectedby the compacted sequence, which leads to a reduction in faultcoverage.

Vector restorationwas proposed by Pomeranz and Reddy[11] as a more computationally efficient alternative to vectoromission. Vector restoration-based test compaction proceedsas follows. First, all or most of the test vectors are omittedfrom the test sequence. Test vectors are then restored one ata time or in subsequences only as necessary to restore thefault coverage of the original sequence. The restoration-basedprocedure [11] showed significant run time advantages overthe omission-based procedure [8]. Several recently devel-oped static compaction techniques [12]–[15], including the

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294 IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, VOL. 22, NO. 3, MARCH 2003

research reported in this work, belong to the class of vectorrestoration-based static compaction procedures, which arenow regarded as the most effective way to implement staticcompaction procedures for reducing the length of sequentialcircuit test sequences.

Several static test compaction procedures which deal withspecial constraints or special circuit designs were also proposed.A test sequence compaction method for sequential circuits withreset is proposed in [16]. In [17], a method to achieve highercompaction level when some loss of fault coverage is admis-sible was investigated.

In this paper, we investigate techniques to further improvethe run time of vector restoration-based compaction. Duringtest vector restoration, a fault simulator is called to simulatethe targeted faults. Most of the time in the compaction processis spent on fault simulation. Specifically, much of the timeis spent resimulating faults for which vector restoration hasalready been performed, but which may not be detected afteradditional vectors are restored for other faults. In [11], a methodto avoid resimulation was investigated. This method reducedrun time at the cost of reduced compaction level. In order toreduce the resimulation time without losing compaction, twoissues are considered here: 1) reducing the number of faultsthat need to be resimulated and 2) reducing the number ofsubsequences that need to be resimulated. We first proposea procedure which reverses the order of the vectors in theoriginal sequence and, thus, reduces the number of faults tobe resimulated during vector restoration. A reverse order isobtained since subsequences are restored starting from theend of the original test sequence, and placed in order ofrestoration in the compacted sequence. Reversing the order ofvectors implies that a restored subsequence is included in thecompacted test sequence before any subsequence restored later.Consequently, all the faults detected by the restored compactsequence continue to be detected as additional subsequencesare restored. Hence, the faults detected earlier do not needto be resimulated. This procedure is extended to a class ofradix reverse-order-restoration (RROR) compaction proceduresthat restore more than one vector in each step. The numberof vectors restored in consecutive steps increases such thatnecessary vectors can be restored quickly for the target faultswhich need long subsequences to be detected. Finally, weinvestigate a technique to improve the compaction level ofthe reverse-order-restoration (ROR) procedure by combiningit with a vector omission-based compaction procedure [8]. Wealso use a parallel pattern fault simulation for a single faultto speed up the vector restoration process.

It should be noted that ROR was independently done in[13] and [14]. However, in [13], test vectors are restored suchthat the target faults are detected assuming the initial stateof the circuit is unknown. In the proposed procedure, thecurrent compacted sequence is used as a prefix for the restoredsubsequence for the new set of target faults. This allows usto restore shorter subsequences since the current compactedsequence could have driven both the fault-free and the faultycircuits into fully or partially known states and could even haveactivated the target faults. To further improve the compactionlevel, we use the omission-based compaction procedure [8]

to omit vectors at any position along a restored subsequence.This is in contrast to the segment pruning procedure in [14]that omits vectors in consecutive positions at the beginning ofthe restored subsequences. These differences lead, in general,to higher levels of compaction than the procedures describedin [13] and [14].

This paper is organized as follows. In Section II, we brieflyreview the basic restoration and omission-based compactionalgorithms. In Section III, we present the ROR procedure.Section IV describes a class of reverse order compactionmethods, RROR. The mixed-mode test sequence compactiontechnique, which combines the vector restoration and vectoromission techniques, is given in Section V. Experimental resultson the compaction of test sequences generated by severaltest generators are reported for the compaction proceduresdescribed. Section VI summarizes the paper.

II. PRELIMINARIES

In this section, we provide a brief review of the ROR [11] andthe omission-based [8] compaction algorithm. The followingnotation is used in this work.

The test sequence to be compacted is denoted by T and thecompacted sequence is denoted by. The length of T is de-noted by L. The test vector at time unit of T is denoted by ,

i . The set of faults detected by T is denoted by .The set of faults detected for the first time at time unitis de-noted by . We denote by the first detection timeof a fault under the original test sequence T. During test com-paction by vector restoration, a group of target faults isselected and test vectors are restored to detect the target faults.After a subsequence is restored, fault simulation is con-ducted to drop the detected faults.

A. Basic Vector Restoration Procedure

The main idea of the restoration-based compaction algorithmis summarized in the following procedure.

Procedure: Vector Restoration (T, )

1) Set . Set , where is a prefixof that synchronizes the fault-free circuit.

2) From , find faults with the latest detection times anduse them as the set of target faults, .

3) Restore vectors from into the test sequence until allthe faults in are detected.

4) If any previously targeted faultf becomes undetected,restore more vectors into until f is detected.

5) Set .6) Simulate and drop the detected faults from .7) If is not empty, go to Step 2.Note that in the basic vector restoration procedure, the re-

stored vectors or subsequences are included inin the sameorder as they appear in the original test sequence. Once a testsubsequence is restored, the previously restored vectors that ap-pear in later time units will have to be resimulated to make surethat they still detect the same faults as before the new subse-quence was restored. This is illustrated next.

Suppose that initially, . Let the first subset offaults F considered by procedure vector restoration result in the

GUO et al.: ROR-BASED STATIC TEST COMPACTION FOR SYNCHRONOUS SEQUENTIAL CIRCUITS 295

Fig. 1. Example sequential circuit to show fault detection.

restoration of the subsequence T. We obtain . Letthe set of faults detected by be . Next, let the subset offaults F result in the restoration of the subsequence T. Sincethe faults are considered by decreasing order of their detectiontimes, and since we keep the restored subsequences in the orig-inal order, we obtain T T . Consider a fault f in

. This fault is detected when Tis applied immediately after. If T is inserted between and T, f is not guaranteed

to be detected any more. This is because the additional vectorsbetween and T may cause the circuit state to change, thus,preventing activation and/or propagation of fault f. For example,consider the circuit given in Fig. 1. Let the target fault be nodeF stuck-at-one. Let AB , ABand AB . The sequence T detects thetarget fault. However, the sequence T T does not detectthe target fault. To resolve this issue, in Step 4 we simulateand restore additional vectors if faults, which were detected ear-lier, become undetected after the restoration of a subsequence.

We point out that there is a version of the restoration-basedcompaction procedure, which was described in [11]. Thisprocedure restores subsequences in the order they appear in theuncompacted test sequence. It does not require resimulationof faults after restoring a subsequence, thus, speeding up thecompaction procedure. However, the speedup is obtained atthe expense of lower compaction levels, since synchronizationis required as part of every restored subsequence.

B. Omission-Based Compaction Algorithm

The main idea of the vector omission-based compaction al-gorithm [8] is summarized next. Given a test sequence T, faultsimulation is conducted to find the set of faults detected by T.Then, starting from the beginning of the test sequence, test vec-tors are omitted one at a time (or in subsequences) and fault sim-ulation is performed. If the same faults continue to be detectedafter omitting a vector, the vector is removed from the sequence.Otherwise, the vector is retained.

The following procedure, adapted from the original omis-sion-based compaction algorithm [8], is used in Step 11 of theproposed mixed-mode compaction procedure given later in Sec-tion V. The inputs to the procedure are T, the test sequence to becompacted, and F, the set of faults detected by sequence T. Theprocedure returns a compacted test sequence. For the givenfault set F, we assume that the detection time of each fault isalso given.

Procedure: Vector Omission (T, F )

1) Set for every . (as in [8],if the th vector is omitted from , and it

is 0 otherwise).

2) Set .3) Set . Using as target faults, simu-

late the test sequence assuming that vectors withare omitted from .

4) If not all the faults in are detected, set .5) Set . If , go to Step 3.6) Let be the test sequence consisting of all the vectors in

with (the vectors in appear in thesame order as they appear in).

7) Return .

III. REVERSEORDER RESTORATION

The resimulation process in Step 4 of the basic vectorrestoration procedure sometimes makes it time consuming. Inthis section, we describe an improved version of the vectorrestoration procedure, which is calledreverse ordervectorrestoration. Similar to the procedures described in [12], aprefix of the test sequence is restored first, and then, groupsof selected faults are considered. The main difference betweenthe earlier works and the one described here is in the way therestored subsequences are used to create a new test sequence.Here, the restored subsequences are placed in the new sequencein reverse order of their inclusion in the original test sequenceT. In earlier works [6]–[12], the restored subsequences appearin the same order as they appear in the original sequenceT. As we will show later, this helps save simulation effortas more subsequences are restored. The other modificationwe made is to first restore a user specified short prefix ofthe original test sequence instead of restoring the shortestprefix that synchronizes the fault-free circuit. This addressesthe tradeoff between the compaction level and CPU time.

A. Algorithm Description

As in Procedure Vector Restoration, we consider faults by de-creasing order of their detection times. Thus, the subsequenceswe find, which need to be restored into the compacted sequence

, are such that subsequences ending at higher time units arefound earlier than subsequences ending at lower time units. InProcedure Vector Restoration, the subsequences are kept in theiroriginal order. In the procedure proposed here, we reverse theorder of the subsequences. To illustrate this point, let the cur-rent compacted sequence be, and let detect the set of faults

. Suppose that a subsequence Tis restored in order to detecta subset of faults F. Since T ends at a lower time unit thanthe subsequences in , and since we reverse the order of therestored subsequences, we place Tat the end of . We, thus,obtain T . The advantage gained by restoring subse-quences in this manner is that the set of faultsdetected by

is guaranteed to be detected byeven after updating it byconcatenating Tto it, and, thus, the faults in do not need tobe resimulated. To take full advantage of this observation, westore the circuit states after simulating for faults that are notdetected by . These final states are used as initial states forsimulation of the next subsequence added to. Thus, resim-ulation does not need to be carried out for the yet undetectedfaults as well.


The detailed description of the procedure referred to as RORis given next. We use an arrayrestoredto indicate which vectorsare restored. We set if time unit is restored,otherwise, we set .

Procedure: ROR (T, , K)is the input sequence, is the output sequence, and

is a user specified integer

1) Fault simulate T. Find the first detection time ofeach fault . Let be the set of detected faults. Let

be the number of faults in .2) Let be a time unit specified by the user. Set

for and setfor . Let be the re-

stored sequence.3) For each fault in with , drop

from .4) Fault simulate the faults in using . Record the

states of the fault-free and faulty circuits for the yetundetected faults at the end of the application of.

5) If , stop. is the resulting test sequence.6) Find the K highest detection time units for faults in .

Use the faults detected at the K highest time units as theset of target faults . Drop all the faults in from

.7) Set for each fault in . Let

denote the subsequence restored while considering.

8) Using as the set of target faults and asthe input sequence, perform fault simulation using therecorded states as the initial states. (Note thatcontains all the faults detected by in the originalsequence but not by the already restored sequences).

9) If all the faults in are detected by , go to Step11.

10) For each undetected fault in , call ProcedureRestore_additional_vector( ). (This procedureis to be explained next.) For each time unitu withrestored , setrestored . Update andif a test vector at any time unit which detects at least onefault in the original sequence is restored, include thefaults detected at that time unit in . Go to Step 8.

11) Using as the input sequence, simulate startingfrom the stored states and drop the detected faults.Record the states reached after simulating onthe fault-free and faulty circuits with the yet undetectedfaults.

12) Append to the end of .13) Go to Step 5.In Procedure ROR, Step 1 performs one pass of fault simu-

lation to collect the detection time unit for each detected fault.Steps 2–4 restore a user specified prefix . can be spec-ified as the synchronizing sequence for the fault-free circuit, orit can be a short test sequence with several vectors. Generally,longer prefix leads to faster compaction process but longerprefix sequence may also lead to longer compacted sequencebecause the prefix is just copying some starting vectors in theoriginal sequence to the compacted sequence and there is no

TABLE IVECTORRESTORATION FORTWO FAULTS

compaction on the prefix sequence. Step 5 checks whether thealready restored vectors detect all the originally detected faults.If not all the faults detected by the original test sequence are de-tected, Steps 6–13 will select a set of undetected faults as targetfaults and vectors will be restored to detect the target faults.During each iteration of the Steps 6–13, if more target faults areselected (larger value of K), the compaction process is generallyfaster, but we may lose compaction level. Hence, we suggest thevalue of K should be a small number in order to achieve bettercompaction level.

The procedure Restore_additional_vector() used in Step 10restores new vectors for the undetected target faults. For eachundetected fault, one new vector is restored before the next passof simulation is performed to check its detection status. The re-stored vector is at time unit which is the highest time unitthat is lower than with i or 2. In the proce-dure Restore_additional_vector(), for a newly restored vectorat time unit we set i . Later, in Step 10 of themain compaction procedure, we change the value of ifrom two to one. This helps us avoid restoring more than onetest vector when two faults point to the same time unitwhichis lower than their detection times and has restoredi . Forexample, consider the situation illustrated in Table I.

At some stage, if the faults in (8) and (10) are notdetected, it is necessary to restore additional vectors. For ,Restore_additional_vector(8) will set . Then,for , Restore_additional_vector(10) goes back to timeunit six and finds that time unit six has already been restoredby another undetected fault. In this case, it will return withoutrestoring additional vectors. In contrast, if we set, vector five will be restored for . This may restore more

test vectors than necessary and adversely affect the compactionlevel.

Procedure: Restore_additional_vector(u)

1) If ( AND u ), set u .2) else if u

a) Set . Go to the previous time unitb) Go to Step 1

3) else Return if u , do nothingThe compaction procedure stops when all the faults detected

by the original test sequence are detected by the restored test se-quence. It should be noted that Procedure ROR is not guaranteedto always reduce the test sequence length. In the worst case, thecompacted sequence could be longer than the initial sequence bythe length of . This happens when every vector (including

) has to be restored and is restored twice. However, aswe observed in our experiments, all the test sequences generatedby ATPG systems can be significantly reduced by ROR.

We use an example to show how the target faults are selectedand how to restore vectors for the targets faults. Consider a testsequence of length 12 given in Table II. After one pass fault


TABLE IIFAULTS DETECTED AT EACH TIME UNIT

Fig. 2. Example for reverse order vector restoration.

simulation, the faults detected at each time unit are shown inthe table, e.g. fault is detected at time unit one, fault isdetected at time unit two, and so on. The execution of the com-paction procedure is depicted in Fig. 2. Suppose we selectto contain one test vector, then test vectoris restored as theprefix. The states for the faulty circuits and the fault-free cir-cuit are stored after the simulation of . These stored statesare used as the initial states for the following vector restorationprocess. Suppose we set K , then the highest two detectiontime units are selected. In this example, time units 10 and 12are selected, and the faults detected at these two time units arethe target faults, i.e. . New vectors need tobe restored to detect the target faults. First, vectorsandare restored, because the target faults are detected at these timeunits. Then the fault simulator is called to check whether all thetarget faults are detected. Suppose that faultis detected butfaults and remain undetected. Then more vectors need tobe restored. In this example, vectoris restored to detect fault

and vector is restored to detect fault . The fault simu-lator is called again to check whether all the target faults are de-tected. If fault is still not detected, we restore vector. Now,if all the target faults are detected, we put the restored vectors

at the end of and get the new com-pacted sequence . The sequence made upof these restored subsequences, shown in Fig. 2 within the shad-owed boxes, is used as a prefix for subsequent vector restoration.

Before we select the next set of target faults, we simulatethe newly restored subsequence and checkwhether the restored subsequence detects other undetectedfaults. In the case of the given example as shown in Fig. 2, faults

, are detected and they will be dropped from andwill not be targeted later. The compaction procedure will selectthe next set of target faults from the yet undetected faults andnew vectors will be restored to detect the target faults. In thisexample, faults and are not detected yet, and are selected

as target faults. More vectors are restored to detect these targetfaults. After restoring vectors , , and , assume that thesetwo faults are detected. Then we append to the endof the already restored test sequence and get the new compactedsequence . Because all thefaults detected by the original sequence are now detected by thiscompacted sequence, the compaction procedure stops and thefinal compacted sequence is ,whose length is 25% less than the original test sequence length.

Note that in the restored test sequence, the order of appear-ance of the restored subsequences in the original sequence isreversed. This is the main difference from the earlier works [11]and the procedures we introduced in [12] where the test vec-tors appear in the order they appeared in the original sequence.It results from the fact that the compacted test sequence is ob-tained by appending new restored subsequences to an existingsequence. This reduces the number of faults simulated under thenew subsequence, since none of the faults detected by the pre-viously selected subsequences needs to be simulated again.

With a minor change, the proposed test compaction techniquecan be adapted to handle designs with multiple clock domains.The main requirement is a fault simulator that can handle suchdesigns.

B. Experimental Results for ROR

Experimental results of the procedure described above areincluded in this section. The proposed procedure is implementedin the C language and run on a 400-MHz Pentium II PC runninga Linux operating system. The parallel fault simulator HOPE[18], [19] is used as the fault simulator in our implementation.We consider ISCAS89 and ADDENDUM93 benchmark circuitsand several synthesized circuits from the University of Illinois.The test sequences are the ones generated by the test generatorSTRATEGATE [20].


TABLE IIICOMPACTION RESULTS FORSTRATEGATE TEST SEQUENCES

The length of the initial restored sequence in Step 2 of the pro-cedure can affect the total number of faults to be targeted duringtest compaction and also affect the total test compaction time.A long prefix makes the compaction faster but may result in alower compaction level. In our experiments with the ROR-basedcompaction procedure, for all the circuits, we keep a prefix ofone vector. The compaction results for these circuits are shownin Table III.

In Table III, we report the results for K , 2, and 5. Wegive the test length before and after compaction for each valueof K. We also give the run times in s. The last row gives thetotal number of test vectors in the compacted sequences and thetotal CPU time for all the circuits listed in the table. Comparingthe results for different values of K, it can be seen that whenK , the ROR compaction procedure achieves the best com-paction level, while the CPU times for different values of K arecomparable. For the sake of comparison, we give the results ofthe earlier restoration-based procedure, procedure sorted-ordercompaction (SOK), described in [12]. Out of the three proce-dures in [12], Procedure SOK with K achieves the bestcompaction for most of the circuits. The CPU time reported forProcedure SOK is also measured on the same machine. Com-pared with the results obtained by Procedure SOK, the RORprocedure needs shorter time for all the circuits while keepingthe high level of compaction. The total test sequence length andthe total compaction time for all the benchmark circuits consid-ered given in the last row of Table IV show the effectivenessof the proposed algorithm. It can be seen that in total, a 75%savings in run time over that for Procedure SOK in [12] is ob-tained without sacrificing the compaction level. Moreover, theROR procedure achieves higher compaction levels in a shortertime when K and K .

Table IV gives the compaction results when we iterativelyrun the ROR compaction procedure with K until thelength of the sequences cannot be reduced any further. Werefer to the iterative version of ROR as ITE-ROR. Comparingto one pass of ROR, iterative application of ROR reduces thetotal length of the test sequences from 8373 to 7606. The run

TABLE IVITERATIVE COMPACTION RESULTS FORSTRATEGATE TESTSEQUENCES

time however increases by a factor of about five. Comparingto ITE-ROK in [12], which achieves the highest compactionlevel among the three iterative procedures developed in [12],ITE-ROR reduces the compaction time by 81.5%. For mostof the circuits, the test sequence length obtained by ITE-RORis shorter than that obtained by the ITE-ROK procedure. Thetotal length of the compacted sequences by ITE-ROR is 7.5%shorter than that obtained by ITE-ROK.

We also applied procedure ROR with K to the test se-quences generated by [21], a deterministic test sequence gener-ator, and the test compaction results are reported in Table V. Foreach circuit, after the circuit name and the original test sequencelength, we report the length of the compacted test sequence andthe CPU time of the compaction procedure. It can be seen thatthe total number of test vectors for all the circuits has been re-duced from 16 752 to 5949, which is a reduction of 64.5%, whilethe total compaction time is only 67.0 s. In Table V, we also givethe results for SECO [14], which is a vector restoration-basedcompaction procedure with segment pruning techniques. SECOis run on a Sun UltraSparc II workstation and, hence, we cannot


TABLE VCOMPACTION RESULTS FORHITEC TEST SEQUENCES

TABLE VICOMPACTION RESULTS FORRANDOM SEQUENCES OFLENGTH 40 000

compare the run time directly. However, when we compare thetest sequence lengths, for all the available 16 circuits, RORachieves much higher compaction levels than SECO. The totaltest sequence length after compaction by ROR is 38.6% shorterthan that obtained by SECO.

We also applied the proposed compaction technique torandom sequences of 40 000 vectors. The results of this studyare given in Table VI. In the first column of Table VI, wegive the time in seconds for fault simulation of 40 000 vectors,followed by the number of faults detected. Under column ROR,we give the run time in seconds, the number of faults detected,the compacted sequence length, and the percentage reductionin sequence length. The last column gives the normalizedcompaction time to one pass of fault simulation. It can beobserved that the compaction adds very little to the run timefor fault simulation of the original sequence. For example, fors1423 the run time for one pass of fault simulation is 40.29 sand the total time for running the compaction procedure, whichincludes an initial fault simulation step, is 42.00 s. The last rowof Table VI gives the average test length reduction percentageand the average normalized time. On the average, ROR uses1.10 times fault simulation time and reduces the randomsequence length by 98.99%. Another point to be noted is thatthe test lengths reduce dramatically while the numbers of faultsdetected sometimes increase. The increase in fault coveragesobtained by compacted test sequence over that obtained byuncompacted sequence was also observed in [8].

IV. SPEED-UP TECHNIQUES

The compaction methods we describe next are variations ofthe ROR method described above. They form a class of methods,RROR, which we introduce here to further speed up the RORprocedure.

In the ROR method described above, when the number oftarget faults K is set to one, the compacted sequence is extendedby one vector at a time to find a sequence that detects the targetfault. Thus, we call it linear reverse order restoration (LROR).To restore vectors, the LROR procedure performsiterationswhere the target fault is simulated under a test sequence whoselength increases by one at every iteration. When K faults aretargeted, the test length is increased by at most K vectors withevery restoration step, which is also a linear increase. It wasobserved that a process of this type can be speeded up by usingbinary search [8]. In the context of vector restoration, binarysearch implies that vectors are restored in iteration. Thus,to restore 15 vectors, LROR performs 15 iterations, whereasusing binary search, the first iteration restores one vector, thesecond iteration restores two vectors for a total ofvectors, the third iteration restores four vectors for a total of

vectors, and the fourth iteration restores the requiredvectors, thus, completing the restoration

in four iterations instead of 15. Binary search of this type wasalso used by Bommuet al. [13]. In this work, we extend thenotion of binary search toradix searchin a procedure we referto as RROR. Under radix search with a radix, vectors arerestored in iteration. We use in our implementation.Notice that RROR includes LROR as a special case with radix

.One of the issues to be considered in radix search, also occur-

ring in binary search, is that the number of vectors restored in thelast iteration may be too large. For example, consider the casewhere ten vectors need to be restored. Binary search will requirefour iterations and will restore 15 vectors instead of ten. To re-move the unnecessary vectors, we perform a second radix searchon the vectors added in the last iteration. Suppose that vectors

to were added in the last iteration. Letbe the length of the subsequence betweenand . We con-sider the addition of vectors instead of the vectors addedin the last iteration. If this is sufficient to detect the target faults,we continue the radix search with the sequence of length,otherwise, we continue the radix search over the sequence oflength that remains.

For example, consider the case of binary search where eightvectors were added in the last iteration. We consider the additionof four vectors instead of eight. If this is sufficient to detectthe target faults, we consider the addition of only two vectors,otherwise, we consider the addition of six vectors, and so on.

Another important point to be noted for both LROR andRROR is the following. If, during the restoration, we includein an input vector, say , that detects some yet undetectedfaults different from the target faults with which we started,we augment the set of target faults by including all the faultsdetected at . The restoration is then done by consideringsequences of vectors prior to of length , , , and soon. This helps us avoid adding long subsequences for the newfaults added to the set of target faults.


TABLE VIIRESULTSUSING LROR AND RROR PROCEDURES

A. Experimental Results for RROR Procedures

In this section, we report the test sequence compactionresults of the radix reverse order compaction procedures. Weused radii , 1.5, 1.8, and 2.0. For two larger ISCAS89benchmark circuits s15850.1 and s38584.1, we compacted arandom sequence of length 40 000 since the test sequences forthese circuits generated by STRATEGATE were not available.These results are given in Table VII. Following the circuit name,we give the length of the test sequences of STRATEGATE or40 000 for the larger benchmark circuits given in the last tworows. Next, we give the length of the compacted sequences andrun time for the LROR method. In the next eight columns, wegive the normalized compacted test sequence length and runtimes for the RROR methods. The normalized test sequencelength and run times for these methods are obtained by dividingthe values for the radix method by the values for the linearmethod given in columns three and four. In the third rowfrom the bottom of the table, we give the average values ofthe normalized test sequence length and run times computedover all the circuits above this row.

The following points can be noted from Table VII.

i) For the smaller benchmark circuits, the linear compactionmethod gives, on the average, approximately 10% bettertest length compaction but requires proportionatelylonger run times. For some circuits these differences arehigher. On the average, among the RROR procedures, theprocedure with (i.e. binary restoration) performsthe poorest.

ii) For the two larger benchmark circuits, the run times ofthe radix compaction methods are much smaller (ap-proximately by a factor of two on the average) than thatfor the linear compaction method. The radix compactionmethods lead to compacted test sequences for circuits38584.1 that are 24% to 42% longer than those obtainedby LROR.

V. ADDITIONAL TECHNIQUES TOIMPROVE THE

COMPACTION PROCEDURE

We next investigate a technique to further improve thecompaction levels obtained by RROR and investigate usingparallel pattern fault simulation in the subsequence restorationprocedure. The use of parallel pattern fault simulation was alsoused in [15]. In the RROR procedures described above, afterrestoring a subsequence, the subsequence is placed at the endof the compacted sequence being developed. All the vectorswhich are included in the restored subsequence will appearin the final compacted sequence. From our observation, someof the vectors in the restored subsequences are not necessaryto detect the target faults. These vectors can be omitted and,thus, a higher compaction level can be expected. We usethe omission-based compaction procedure [8] to achieve thishigher level of compaction. This method allows us to omitvectors at any position along a subsequence that detects a set oftarget faults, unlike the segment pruning procedure in [14] thatomits vectors in consecutive positions at the beginning of thesubsequence. Based on the results in [15], we also implementeda method that uses a parallel pattern single fault simulatorduring subsequence restoration to speed up the restorationprocedure without losing compaction efficiency.

A. Mixed-Mode Compaction Algorithm

In this section, we describe the mixed-mode test compactionprocedure. The basic idea of the proposed procedure is thefollowing. After a restored subsequence is obtained, andbefore it is appended to the end of the already restored sequence,

, is processed by an omission-based compaction methodto reduce its length. In this way, we avoid including unnecessaryvectors in , and we reduce its final length. We use linearROR with K in the mixed-mode compaction algorithmdescribed below. In a straightforward manner, one can useROR with K or RROR with radix other than one in thisprocedure.


Fig. 3. Parallel pattern simulation for vector restoration.

Procedure:Mixed_Mode_Test_Sequence_Compaction(T)1-10) Steps 1–10 are the same as those in Procedure ROR

with .11) Let .12) Using as the input sequence and as the ini-

tial state, simulate and drop the detected faults.Record the states reached after simulating onthe fault-free and faulty circuits with the yet undetectedfaults.

13) Append to the end of .14) Go to Step 5.When Step 11 is reached, we have a subsequencethat

detects the faults in . We use the vector omission-basedprocedure vector omission ( , ) of Section II-B to omitsome vectors from not needed to detect faults in .This is the main difference between the mixed-mode methodand the original ROR compaction method.

Next, we describe the parallel pattern simulation method usedto speed up the vector restoration process. A similar techniquewas used in SIFAR [15] to accelerate the vector restorationprocess.

As stated above, during vector restoration, after identifyingthe vector at the highest time unit where at least one fault isdetected, we begin to restore vectors using parallel fault simu-lation to detect a set of target faults . Each time a vectoris restored, fault simulation is carried out to check whether thetarget faults are detected or not. By using parallel pattern simu-lation, the vector restoration process can be accelerated. Insteadof targeting all the faults detected at the highest time unit, par-allel pattern simulation targets only a single fault while mul-tiple patterns are simulated concurrently, i.e., it uses each bitin a computer word to simulate a different test pattern. The de-tailed simulation process is essentially the same as the one usedin SIFAR [15]. Some differences from [15] are discussed later.Next, we give a sketch of this procedure.

Using the 32 bits of a computer word, 16 pairs of patternsare simulated for the good machine and the faulty machine.The odd bits are used to simulate the good machine andthe even bits are used to simulate the faulty machines. Fig. 3shows three consecutive simulation steps. In these three words,

bits zero and one simulate the subsequence, bits two andthree simulate the subsequence beginning with ,bits four and five simulate the subsequencebeginning with , and so on. Bits 30 and 31 simulate thesubsequence beginning with (thecomputer words following the third one required to completethis subsequence are not shown in the figure). After eachsimulation pass, the current test vector simulated in every pairof bits is increased by one. Once a pair of bits reaches thehighest time unit , the next subsequence is started in thispair of bits. For example, bits zero and one will simulate thesubsequence beginning with after simulating , whilebits two and three will simulate the subsequence beginningwith after simulating , and so on.

After the target fault is detected, parallel fault simulation isconducted to determine other faults detected among those de-tected at by the original sequence and not yet detected bythe current compacted sequence. If there are faults not detectedamong these faults, again one of them is randomly selected asthe target fault and parallel pattern simulation is again conductedto restore more vectors.

Note that during parallel pattern simulation, we check the de-tectability of the target fault by a sequence simulated in a pair ofbits only after is simulated. This guarantees that the parallelpattern simulation gives exactly the same results as the originalcompaction method which uses parallel fault simulation only.This is one difference between our parallel pattern simulationmethod and the one in SIFAR described in [15], which checksthe detectability of the target fault after each pass of simulationand, hence, may identify a shorter subsequence. However, as theexperimental results presented later show, the proposed method,in general, leads to shorter compacted test sequences. The otherdifference between our compaction procedure with parallel pat-tern single fault simulation and SIFAR [15] is that even thoughat any given time a single fault is simulated to identify the nec-essary vectors to be restored as in SIFAR, unlike SIFAR, whichappends the restored vectors to the end of the already restoredsequence immediately, we first check the detectability of all theother faults with the same detection time unit. Only if all of themare detected, we append the restored vectors to the end of the


TABLE VIIICOMPACTION RESULTS FORHITEC [21] TEST SEQUENCES

TABLE IXADDITIONAL COMPACTION RESULTS FORHITEC [21] TESTSEQUENCES

already restored test sequence. Thus, we avoid losing fault cov-erage after one pass of compacting a test sequence. In SIFAR,additional vectors are restored after one complete pass of com-paction to detect any faults not detected.

B. Experimental Results of MISC

We report the test sequence compaction results using themixed-mode test compaction procedure, which is referred toas MISC. We also implemented an iterative version of MISC,which is called ITE-MISC, to iteratively compact the testsequence until two consecutive runs of MISC get the same testsequence length.

Table VIII shows the compaction results for the test se-quences generated by the deterministic test generator HITEC[21]. Additional compaction results on HITEC test sequencesare reported in Table IX for larger ISCAS89 circuits. FromTable VIII, it can be seen that one run of MISC can reduce thetotal sequence length (which is the sum of the test sequencelengths for all the circuits considered) by 69.2% while theiterative MISC version can further improve the compactionlevel by an additional 4.7%. For 15 of the 17 circuits inTable VIII, MISC obtained shorter test sequences than LROR.The improvement is especially noticeable for circuits s382,s400, s526, s820, and s832. In Table VIII, we also list the com-paction results reported by SIFAR [15] and SECO [14], bothrestoration-based compaction procedures. As discussed earlier,SECO [14] also uses a restricted omission-based method calledsegment pruning [14] to omit some vectors from the beginningof a restored subsequence in order to improve compactionefficiency. It can be seen that for 14 of the 17 circuits, MISCgave shorter sequences than SIFAR and the total sequencelength obtained by SIFAR is approximately 20% higher thanthat by MISC. When compared to SECO [14], for all the 16 cir-cuits for which SECO data is available, MISC generates muchshorter sequences than SECO and the total sequence lengthgenerated by SECO is 83% higher than that of MISC. The last

four columns in Table VIII are the compaction results of theiterative MISC and iterative LROR. It can be seen that iterativeMISC achieves better compaction than iterative LROR. Sincedifferent procedures used different fault simulators and wererun on different machines, direct comparison of CPU times arenot applicable. Generally, because of the two phase compactionin MISC (restoration omission), it needs more time thanthe procedures which only use restoration techniques. Thiscan be seen when we compare the CPU time with the LRORalgorithm, which is run on the same machine as MISC. Similarobservations can be made from Table IX.

Table X shows the compaction results for the test sequencesgenerated by the simulation-based test generator STRATE-GATE [20]. From Table X, it can be seen that one run ofMISC can reduce the total sequence length by 77.8% whilethe iterative MISC version can further improve the compactionlevel by 2.5%. For 19 of the 22 circuits, MISC obtained higheror the same compaction level as LROR. For circuits s1423 andam2910, MISC achieves much better compaction than LROR.Similar conclusions can be drawn when we compare MISCwith SIFAR. The total sequence length shows that the proposedmixed-mode compaction procedure achieves better compactionthan LROR and SIFAR, which used the restoration techniqueonly. In Table X, we also list the compaction results of theiterative versions of the three compaction procedures. It can beseen that iterative MISC produces the shortest sequences formost of the circuits compared to iterative LROR and iterativeSIFAR.

VI. SUMMARY

We proposed several techniques to speed up restoration-basedstatic test sequence compaction for synchronous sequential cir-cuits. Every time a subsequence was restored to detect a subsetof target faults, the restored subsequence was added to the endof a test sequence developed during the compaction process.This resulted in reduced simulation effort compared to previousfast implementations of restoration-based procedures that hadto reconsider faults when test vectors prior to their detectiontimes were restored. A class of ROR test compaction methods,called RROR, were proposed to further speed up the vectorrestoration process. These procedures dynamically increase thenumber of test vectors to be restored at each step. To further re-duce the test lengths obtained, we proposed a mixed-mode statictest sequence compaction procedure. This procedure is based on


TABLE XCOMPACTION RESULTS FORSTRATEGATE [20] TEST SEQUENCES

the reverse order vector restoration compaction technique andthe vector omission-based compaction algorithm. During vectorrestoration, before a subsequence is added to the compactedsequence, the vector omission-based method is used to omitsome vectors from the restored subsequence. Experimental re-sults presented in this paper demonstrated that the mixed modecompaction algorithm can reduce the test sequence length gen-erated by several ATPG systems by up to 80%.

The following observation regarding power dissipation andbus contention during test is important. For some designs notall input sequences are applicable in normal operation. In de-riving tests for such designs, the test generation procedure mayneed to be aware of the illegal sequences that cause bus con-tention and/or excessive peak or average power dissipation. Ifthe original tests are derived under these conditions, then thetest compaction procedure proposed here should be enhancedto avoid violating these conditions.

REFERENCES

[1] I. Pomeranz and S. M. Reddy, “Dynamic test compaction for syn-chronous sequential circuits using static compaction techniques,” inProc. Annu. Symp. Fault-Tolerant Comput., June 1996, pp. 53–61.

[2] T. J. Lambert and K. K. Saluja, “Methods for dynamic test vector com-paction in sequential test generation,” inProc. 9th Int. Conf. VLSI De-sign, Jan. 1996, pp. 166–169.

[3] S. T. Chakradhar and A. Raghunathan, “Bottleneck removal algorithmfor dynamic compaction in sequential circuits,”IEEE Trans. Computer-Aided Design, vol. 16, pp. 1157–1172, Oct. 1997.

[4] T. Hosokawa, T. Inoue, T. Hiraoka, and H. Fujiwara, “Static and dynamictest sequence compaction methods for acyclic sequential circuits usinga time expansion model,” inProc. Asian Test Symp., Nov. 1999, pp.192–199.

[5] B. So, “Time Efficient Automatic Test Pattern Generation Systems,”Ph.D dissertation, Dept. of Elec. Eng., Univ. of Wisconsin, Madison,WI, 1994.

[6] T. M. Niermann, R. K. Roy, J. H. Patel, and J. A. Abraham, “Test com-paction for sequential circuits,”IEEE Trans. Computer-Aided Design,vol. 11, pp. 260–267, Feb. 1992.

[7] F. Corno, P. Prinetto, M. Rebaudengo, and M. Conza Reorda, “Newstatic compaction techniques of test sequences for sequential circuits,”in Proc. Eur. Design Test Conf., Mar. 1997, pp. 37–43.

[8] I. Pomeranz and S. M. Reddy, “On static compaction of test sequencesfor synchronous sequential circuits,” inProc. 33rd Design AutomationConf., June 1996, pp. 215–220.

[9] M. S. Hsiao, E. M. Rudnick, and J. H. Patel, “Fast algorithm for staticcompaction of sequential circuit test vectors,” inProc. 15th Annu. VLSITest Symp., April 1997, pp. 188–195.

[10] M. S. Hsiao and S. T. Chakradhar, “State relaxation based subsequenceremoval for fast static compaction in sequential circuits,” inProc. Eur.Design Automation Test Conf., Feb. 1998, pp. 572–576.

[11] I. Pomeranz and S. M. Reddy, “Vector restoration based static com-paction of test sequence for synchronous sequential circuits,” inProc.Int. Conf. Computer Design, Oct. 1997, pp. 360–365.

[12] R. Guo, S. M. Reddy, and I. Pomeranz, “Procedures for static com-paction of test sequences for synchronous sequential circuits,” inProc.Eur. Design Automation Test Conf., Feb. 1998, pp. 583–587.

[13] S. Bommu, K. Doreswamy, and S. Chakradhar, “Static test sequencecompaction based on segment reordering and accelerated vector restora-tion,” in Proc. Int. Test Conf., 1998, pp. 954–961.

[14] S. Bommu, S. Chakradhar, and K. Doreswamy, “Static compaction usingoverlapped restoration and segment pruning,” inProc. IEEE/ACM Int.Conf. Computer-Aided Design, Nov. 1998, pp. 140–146.

[15] X. Lin, W.-T. Cheng, I. Pomeranz, and S. M. Reddy, “SIFAR: statictest compaction for synchronous sequential circuits based on single faultrestoration,” inProc. VLSI Test Symp., May 2000, pp. 205–212.

[16] Y. Higami, Y. Takamatsu, and K. Kinoshita, “Test sequence compactionfor sequential circuits with reset states,” inProc. 9th Asian Test Symp.,Dec. 2000, pp. 165–170.

[17] S. Bommu, S. Chakradhar, and K. Doreswamy, “Resource-constrainedcompaction of sequential circuit test sets,” inProc. 13th Int. Conf. VLSIDesign, Jan. 2000, pp. 398–405.

[18] H. K. Lee and D. S. Ha, “HOPE: an efficient parallel fault simulatorfor synchronous sequential circuits,” inProc. Design Automation Conf.,June 1992, pp. 336–340.

[19] , “New technique for improving parallel fault simulation in syn-chronous sequential circuits,” inProc. Int. Conf. Computer-Aided De-sign, Oct. 1993, pp. 10–17.

[20] M. S. Hsiao, E. M. Rudnick, and J. H. Patel, “Sequential circuit test gen-eration using dynamic state traversal,” inProc. Eur. Design Test Conf.,March 1997, pp. 22–28.

[21] T. M. Niermann and J. H. Patel, “HITEC: a test generation package forsequential circuits,” inProc. Eur. Conf. Design Automation (EDAC),1991, pp. 214–218.

Ruifeng Guo (S’97–M’00) received the B.S. degreein electronics from Nankai University, Tianjin,China, in 1993, the M.S. degree in electronics fromPeking University, Beijing, China, in 1996, and thePh.D degree in electrical and computer engineeringfrom the University of Iowa, Iowa City, in 2000.

Since 2000, he has been working with the Testand Diagnosis Technology Group, Intel Corporation,Hillsboro, OR. His research interests include ATPGfor VLSI circuits, test sequence compaction, faultdiagnosis, and design for testability.


Sudhakar M. Reddy (S’68–M’68–SM’84–F’87)received the undergraduate degree in electricaland communication engineering from OsmaniaUniversity, Hyderabad, India, the M.S. degree fromthe Indian Institute of Science, Bangalore, India, andthe Ph.D. degree in electrical engineering from theUniversity of Iowa, Iowa City.

Since 1968, he has been a member of the facultyof the Department of Electrical and Computer Engi-neering, University of Iowa, where he is currently aProfessor. He has been active in the areas of testable

designs and test generation for logic circuits since 1972.Dr. Reddy is a member of Tau Beta Pi, Eta Kappa Nu, and Sigma Xi. He has

been an Associate Editor and twice a Guest Editor of the IEEE TRANSACTIONS

ON COMPUTERS. He is an Associate Editor of the IEEE TRANSACTIONS ON

COMPUTER-AIDED DESIGN OFINTEGRATED CIRCUITS AND SYSTEMS. In 1990,he was made a University of Iowa Foundation Distinguished Professor.

Irith Pomeranz (M’89–SM’96–F’99) received theB.Sc degree (summa cum laude) in computer engi-neering and the D.Sc degree in electrical engineeringfrom the Technion—Israel Institute of Technology,Haifa, Israel, in 1985 and 1989, respectively.

From 1989 to 1990, she was a Lecturer in the De-partment of Computer Science, Technion. From 1990to 2000, she was a faculty member in the Departmentof Electrical and Computer Engineering, Universityof Iowa. In 2000, she joined the School of Electricaland Computer Engineering, Purdue University, West

Lafayette, IN, where she is currently a Professor. Her research interests includetesting of VLSI circuits, design for testability, synthesis, and design verification.

Dr. Pomeranz was a recipient of the National Science Foundation YoungInvestigator Award in 1993, and of the University of Iowa Faculty ScholarAward in 1997. She serves as an Associate Editor of theACM Transactionson Design Automationand as an Associate Editor of the IEEE TRANSACTIONS

ON COMPUTERS. She served as Guest Editor of the IEEE TRANSACTIONS

ON COMPUTERS, January 1998 special issue on Dependability of ComputingSystems, and as Program Co-chair of the 1999 Fault-Tolerant ComputingSymposium.

reverse-order-restoration-based static test compaction for synchronous sequential circuits

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